JPH06151429A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH06151429A JPH06151429A JP30353592A JP30353592A JPH06151429A JP H06151429 A JPH06151429 A JP H06151429A JP 30353592 A JP30353592 A JP 30353592A JP 30353592 A JP30353592 A JP 30353592A JP H06151429 A JPH06151429 A JP H06151429A
- Authority
- JP
- Japan
- Prior art keywords
- film
- alloy
- films
- connection hole
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 15
- 229910052735 hafnium Inorganic materials 0.000 claims abstract description 5
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 abstract description 27
- 239000000956 alloy Substances 0.000 abstract description 27
- 229910018594 Si-Cu Inorganic materials 0.000 abstract description 25
- 229910008465 Si—Cu Inorganic materials 0.000 abstract description 25
- 238000004544 sputter deposition Methods 0.000 abstract description 11
- 238000013508 migration Methods 0.000 abstract description 7
- 230000005012 migration Effects 0.000 abstract description 6
- 230000004913 activation Effects 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 24
- 239000010936 titanium Substances 0.000 description 9
- 229910000881 Cu alloy Inorganic materials 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910018523 Al—S Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910018540 Si C Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高信頼性を有する多層
配線を形成することができる、半導体装置およびその製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of forming multi-layer wiring having high reliability and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、半導体装置の微細化・高集積化に
伴い、配線の信頼性、すなわちエレクトロマイグレーシ
ョンやストレスマイグレーションが問題となっている。
配線材料としては、スパッタリング法を用いて堆積した
純アルミニウム（Ａｌ）、またはシリコン（Ｓｉ）、チ
タン（Ｔｉ）、銅（Ｃｕ）、Ｇｅ、Ｈｆ、Ｂ、Ｐｄ等を
含有したＡｌ合金が用いられている。2. Description of the Related Art In recent years, with miniaturization and high integration of semiconductor devices, reliability of wiring, that is, electromigration and stress migration has become a problem.
As the wiring material, pure aluminum (Al) deposited by sputtering or an Al alloy containing silicon (Si), titanium (Ti), copper (Cu), Ge, Hf, B, Pd, or the like is used. ing.
【０００３】従来、半導体装置における多層配線を形成
する方法として、図２に示すように、半導体基板１上に
形成された第１の絶縁膜２に第１の接続孔３を形成し、
さらに第１の配線４、５を形成する。また同様に第１の
配線８、９を第２の絶縁膜６上に形成するという方法が
用いられている。ここで１０はパッシベーション膜を示
す。Conventionally, as a method of forming a multilayer wiring in a semiconductor device, as shown in FIG. 2, a first connection hole 3 is formed in a first insulating film 2 formed on a semiconductor substrate 1,
Further, first wirings 4 and 5 are formed. Similarly, a method of forming the first wirings 8 and 9 on the second insulating film 6 is used. Here, 10 indicates a passivation film.
【０００４】しかし、半導体装置の微細化・高集積化に
伴い、接続孔の径に対する接続孔の深さの比（アスペク
ト比）が高くなる。この結果、スパッタリング法により
堆積した配線は、接続孔において段差被覆性（ステップ
カバレジ）が低下するため初期の段階で断線に至った
り、エレクトロマイグレーションやストレスマイグレー
ションにより断線を引き起こすという信頼性上の問題が
あった。However, with the miniaturization and higher integration of semiconductor devices, the ratio of the depth of the connection hole to the diameter of the connection hole (aspect ratio) becomes higher. As a result, the wiring deposited by the sputtering method has a problem in reliability that the step coverage (step coverage) in the connection hole is deteriorated, resulting in disconnection at an early stage, or electromigration or stress migration. there were.
【０００５】上記のような問題を解決する方法として、
図３に示すように、半導体基板１１上に、第１の接続孔
１３を有した第１の絶縁膜１２を形成し、さらにＡｌ−
Ｓｉ−Ｃｕ合金膜のぬれ性を改善するために第１のＴｉ
膜１４、１５を堆積した後、第１のＡｌ−Ｓｉ−Ｃｕ合
金膜１６、１７を基板温度500℃でスパッタリング法に
より堆積し、第１のＡｌ−Ｓｉ−Ｃｕ合金膜１６、１７
を流動させて第１の接続孔１３に埋め込む。また同様に
第２の接続孔１９を有した第２の絶縁膜１８を形成し、
さらにＡｌ−Ｓｉ−Ｃｕ合金膜のぬれ性を改善するため
に第２のＴｉ膜２０、２１を堆積した後、第２のＡｌ−
Ｓｉ−Ｃｕ合金膜２２、２３を基板温度500℃でスパッ
タリング法により堆積し、第２のＡｌ−Ｓｉ−Ｃｕ合金
膜２２、２３を流動させて第２の接続孔１９に埋め込む
という方法がある。ここで２４はパッシベーション膜を
示す（例えば、アイ・イー・イー・イー・ヴィー・エル
・エス・アイ・マルチレベル・インターコネクション・
コンファレンス(1991)第170頁から第176頁（IEEE VLSI
Multilevel Interconnection Conference (1991) pp.17
0-176））。As a method for solving the above problems,
As shown in FIG. 3, a first insulating film 12 having a first connection hole 13 is formed on a semiconductor substrate 11, and Al-
In order to improve the wettability of the Si-Cu alloy film, the first Ti
After depositing the films 14 and 15, first Al—Si—Cu alloy films 16 and 17 are deposited by a sputtering method at a substrate temperature of 500 ° C., and the first Al—Si—Cu alloy films 16 and 17 are deposited.
To be embedded in the first connection hole 13. Similarly, a second insulating film 18 having a second connection hole 19 is formed,
Further, after the second Ti films 20 and 21 are deposited in order to improve the wettability of the Al-Si-Cu alloy film, the second Al-
There is a method in which the Si—Cu alloy films 22 and 23 are deposited by a sputtering method at a substrate temperature of 500 ° C., and the second Al—Si—Cu alloy films 22 and 23 are fluidized to be embedded in the second connection hole 19. Here, 24 indicates a passivation film (for example, I E E V E L S I multi-level interconnection.
Conference (1991) pp. 170-176 (IEEE VLSI
Multilevel Interconnection Conference (1991) pp.17
0-176)).
【０００６】この場合のＴｉ膜は、Ａｌ−Ｓｉ−Ｃｕ合
金膜とＴｉ膜を反応させることにより界面エネルギーを
低下させ、Ａｌ−Ｓｉ−Ｃｕ合金膜のぬれ性を改善し、
接続孔への埋め込みを容易にするという効果がある。The Ti film in this case lowers the interfacial energy by reacting the Al-Si-Cu alloy film with the Ti film to improve the wettability of the Al-Si-Cu alloy film,
This has the effect of facilitating embedding in the connection hole.
【０００７】このような方法を用いれば、接続孔におけ
る配線のステップカバレジの低下を防止できるので、エ
レクトロマイグレーションやストレスマイグレーション
による断線不良を防止することができる。By using such a method, it is possible to prevent the step coverage of the wiring in the connection hole from being lowered, so that it is possible to prevent disconnection defects due to electromigration or stress migration.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、Ａｌ−Ｓｉ−Ｃｕ合金膜とＴｉ膜の反応
が不十分となり、ぬれ性が悪くなることがあるために、
接続孔へのＡｌ−Ｓｉ−Ｃｕ合金膜の埋め込みの再現性
に問題があった。つまり、接続孔内に空洞が発生し、信
頼性が低下するという問題があった。However, in the above-mentioned structure, the reaction between the Al-Si-Cu alloy film and the Ti film becomes insufficient, and the wettability may deteriorate.
There was a problem in the reproducibility of embedding the Al-Si-Cu alloy film in the connection hole. That is, there is a problem that a cavity is generated in the connection hole and reliability is lowered.
【０００９】本発明は上記の問題点に鑑み、接続孔への
Ａｌ合金膜の完全埋め込みの再現性を確保することがで
きる半導体装置を提供することを目的とする。In view of the above problems, it is an object of the present invention to provide a semiconductor device capable of ensuring the reproducibility of complete embedding of an Al alloy film in a connection hole.
【００１０】[0010]
【課題を解決するための手段】本発明は上記問題点を解
決するため、接続孔に埋め込まれたＡｌ合金膜の下地に
ハフニウム（Ｈｆ）膜を有するという構成を備えたもの
である。In order to solve the above problems, the present invention has a structure in which a hafnium (Hf) film is provided as a base of an Al alloy film embedded in a connection hole.
【００１１】[0011]
【作用】本発明は上記した構成によって、Ｔｉ膜とＡｌ
合金膜の反応に比べて、Ｈｆ膜とＡｌ合金膜の方が反応
が容易であり、Ａｌ合金膜と下地膜との間の界面エネル
ギーが低下するため、Ａｌ合金膜の下地膜に対するぬれ
性を改善することができる。したがって、空洞が発生す
ることなく、Ａｌ合金膜の接続孔への完全埋め込みが可
能となり、エレクトロマイグレーションやストレスマイ
グレーションによる断線不良を防止することができる。The present invention has a Ti film and an Al by the above-mentioned structure.
Compared with the reaction of the alloy film, the reaction between the Hf film and the Al alloy film is easier and the interfacial energy between the Al alloy film and the underlying film is lowered, so that the wettability of the Al alloy film with respect to the underlying film is reduced. Can be improved. Therefore, it is possible to completely embed the Al alloy film in the connection hole without generating a cavity, and it is possible to prevent disconnection failure due to electromigration or stress migration.
【００１２】[0012]
【実施例】本発明の実施例を図面を参照しながら説明す
る。Embodiments of the present invention will be described with reference to the drawings.
【００１３】図１は、本発明の実施例における半導体装
置の製造方法の工程断面図を示すものである。FIG. 1 is a sectional view showing the steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【００１４】まず図１ａでは、半導体素子を形成したシ
リコン基板２５上に、第１の絶縁膜２６を形成し、900
℃の雰囲気中で熱処理を行う。次にフォトリソグラフィ
ー法とドライエッチング法を用いて第１の接続孔２７を
開口する。第１の絶縁膜２６には、ＣＶＤ法によるＢ及
びＰを含んだシリコン酸化膜を用いる。First, in FIG. 1a, a first insulating film 26 is formed on a silicon substrate 25 having a semiconductor element formed thereon, and a 900
Heat treatment is performed in an atmosphere of ° C. Next, the first connection hole 27 is opened by using the photolithography method and the dry etching method. As the first insulating film 26, a silicon oxide film containing B and P by the CVD method is used.
【００１５】次に図１ｂでは、第１の絶縁膜２６上に第
１のＨｆ膜２８、２９を形成し、さらに第１のＡｌ−Ｓ
ｉ−Ｃｕ合金配線３０、３１を形成する。Ａｌ−Ｓｉ−
Ｃｕ合金配線３０、３１の形成には、基板温度を300℃
から550℃の間に保持した状態で堆積を行うスパッタリ
ング法を用いる（高温スパッタ法）。この形成法を用い
た場合、Ａｌ−Ｓｉ−Ｃｕ合金膜が高温にさらされなが
ら堆積されるため、堆積の過程でＡｌ−Ｓｉ−Ｃｕ合金
膜の流動が起こり、第１の接続孔２７に第１のＡｌ−Ｓ
ｉ−Ｃｕ合金配線３１を完全に埋め込むことが可能にな
る。また、第１のＨｆ膜２８、２９も同様にスパッタリ
ング法を用いて形成する。このＨｆ膜は、Ａｌ−Ｓｉ−
Ｃｕ合金膜と反応することによって、接続孔側壁に対す
るＡｌ−Ｓｉ−Ｃｕ合金膜のぬれを改善して、埋め込み
を容易にする効果がある。Ｈｆ膜とＡｌ膜が反応して化
合物を生成するための活性化エネルギーは1.5 eVであ
り、Ｔｉ膜とＡｌ膜の場合の1.8 eVという値よりも小さ
いので、Ｔｉ膜よりもＨｆ膜を下地膜として用いたほう
が反応しやすく、界面エネルギーを下げることができ
る。したがって、Ａｌ−Ｓｉ−Ｃｕ膜のぬれ性が良くな
り、接続孔へのＡｌ−Ｓｉ−Ｃｕ合金膜の埋め込みが容
易となる。Ａｌ−Ｓｉ−Ｃｕ合金配線３０、３１は、フ
ォトリソグラフィー法とドライエッチング法を用いて形
成する。Next, in FIG. 1b, first Hf films 28 and 29 are formed on the first insulating film 26, and further the first Al--S film is formed.
The i-Cu alloy wirings 30 and 31 are formed. Al-Si-
The substrate temperature is 300 ° C. to form the Cu alloy wirings 30 and 31.
A sputtering method is used in which deposition is performed while maintaining the temperature between 1 to 550 ° C (high temperature sputtering method). When this forming method is used, since the Al-Si-Cu alloy film is deposited while being exposed to high temperature, the flow of the Al-Si-Cu alloy film occurs during the deposition process, and the first connection hole 27 receives the first Al-S of 1
It becomes possible to completely embed the i-Cu alloy wiring 31. Further, the first Hf films 28 and 29 are similarly formed by using the sputtering method. This Hf film is Al-Si-
By reacting with the Cu alloy film, there is an effect that the wetting of the Al—Si—Cu alloy film on the side wall of the connection hole is improved and the filling is facilitated. The activation energy for reacting the Hf film with the Al film to generate a compound is 1.5 eV, which is smaller than the value of 1.8 eV for the Ti film and the Al film. It is easier to react and the interfacial energy can be lowered. Therefore, the wettability of the Al-Si-Cu film is improved, and the Al-Si-Cu alloy film can be easily embedded in the connection hole. The Al-Si-Cu alloy wirings 30 and 31 are formed by using a photolithography method and a dry etching method.
【００１６】次に図１ｃでは、第１の絶縁膜２６及びＡ
ｌ−Ｓｉ−Ｃｕ合金配線３０、３１上に第２の絶縁膜３
２を形成し、第２の絶縁膜３２の平坦化を行う。第２の
絶縁膜３２にはプラズマＣＶＤ法を用いたシリコン酸化
膜を使用し、平坦化には、レジストを用いたエッチバッ
ク法を使用している。次にフォトリソグラフィー法とド
ライエッチング法を用いて第２の接続孔３３を開口す
る。Next, referring to FIG. 1c, the first insulating film 26 and A
The second insulating film 3 is formed on the l-Si-Cu alloy wirings 30 and 31.
2 is formed, and the second insulating film 32 is flattened. A silicon oxide film using a plasma CVD method is used for the second insulating film 32, and an etchback method using a resist is used for planarization. Next, the second connection hole 33 is opened by using the photolithography method and the dry etching method.
【００１７】次に図１ｄでは、スパッタリング装置内で
Ａｒスパッタエッチングを行うことにより、第２の接続
孔３３の底部の表面処理を行い、その後、第２の絶縁膜
３２上に第２のＨｆ膜３４、３５をスパッタリング法に
より形成し、さらに第２のＡｌ−Ｓｉ−Ｃｕ合金配線３
６、３７を形成する。Next, in FIG. 1d, the surface of the bottom of the second connection hole 33 is surface-treated by performing Ar sputter etching in the sputtering apparatus, and then the second Hf film is formed on the second insulating film 32. 34 and 35 are formed by a sputtering method, and the second Al-Si-Cu alloy wiring 3 is further formed.
6 and 37 are formed.
【００１８】第２のＡｌ−Ｓｉ−Ｃｕ合金配線３６、３
７の形成には、Ａｌ−Ｓｉ−Ｃｕ合金配線３０、３１の
形成方法について示したように、基板温度を300℃から5
50℃の間に保持した状態で堆積を行うスパッタリング法
を用いる。この形成法を用いた場合、Ａｌ−Ｓｉ−Ｃｕ
合金膜が高温にさらされながら堆積されるため、堆積の
過程でＡｌ−Ｓｉ−Ｃｕ合金膜の流動が起こり、第２の
接続孔３３に第２のＡｌ−Ｓｉ−Ｃｕ合金配線３６を完
全に埋め込むことが可能になる。第２のＡｌ−Ｓｉ−Ｃ
ｕ合金配線３６、３７は、フォトリソグラフィー法とド
ライエッチング法を用いて形成する。Second Al--Si--Cu alloy wiring 36, 3
7 is formed by changing the substrate temperature from 300 ° C. to 5 ° C. as described in the method of forming the Al—Si—Cu alloy wirings 30 and 31.
A sputtering method is used in which deposition is performed while maintaining the temperature at 50 ° C. When this forming method is used, Al-Si-Cu
Since the alloy film is deposited while being exposed to high temperature, the Al-Si-Cu alloy film flows during the deposition process, and the second Al-Si-Cu alloy wiring 36 is completely formed in the second connection hole 33. It becomes possible to embed. Second Al-Si-C
The u alloy wirings 36 and 37 are formed by using a photolithography method and a dry etching method.
【００１９】最後に図１ｅでは、Ｐを含んだシリコン酸
化膜とシリコン窒化膜の積層構造から成るパッシベーシ
ョン膜３８を全面に形成する。Finally, in FIG. 1e, a passivation film 38 having a laminated structure of a silicon oxide film containing P and a silicon nitride film is formed on the entire surface.
【００２０】なお、本実施例においては、２層配線の構
造を示したが、３層以上の多層配線構造においても同様
の効果がある。Although the structure of the two-layer wiring is shown in this embodiment, the same effect can be obtained in the multi-layer wiring structure of three or more layers.
【００２１】[0021]
【発明の効果】以上のように本発明は、Ａｌ合金膜と反
応して化合物を生成するための活性化エネルギーが低い
Ｈｆ膜を下地膜として用いるため、Ａｌ合金膜と下地膜
との間の界面エネルギーを下げ、Ａｌ合金膜のぬれ性を
改善することができる。したがって、接続孔内に空洞が
生じることなく完全埋め込みを達成できるので、エレク
トロマイグレーションやストレスマイグレーションによ
る不良を防止することが可能となる。As described above, according to the present invention, since the Hf film having a low activation energy for reacting with the Al alloy film to generate a compound is used as the underlayer film, the Hf film between the Al alloy film and the underlayer film is The interface energy can be lowered and the wettability of the Al alloy film can be improved. Therefore, complete burying can be achieved without forming a cavity in the connection hole, so that defects due to electromigration or stress migration can be prevented.
【図１】本発明の第１の実施例における半導体装置の製
造方法の工程断面図FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】従来技術における半導体装置の製造方法の工程
断面図FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a conventional technique.
【図３】従来技術における半導体装置の製造方法の工程
断面図FIG. 3 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a conventional technique.
２５ シリコン基板 ２６ 第１の絶縁膜 ２７ 第１の接続孔 ２８,２９ 第１のＨｆ膜 ３０,３１ 第１のＡｌ−Ｓｉ−Ｃｕ合金配線 ３２ 第２の絶縁膜膜 ３３ 第２の接続孔 ３４,３５ 第２のＨｆ膜 ３６,３７ 第２のＡｌ−Ｓｉ−Ｃｕ合金配線 ３８ パッシベーション膜 25 Silicon Substrate 26 First Insulating Film 27 First Connection Hole 28,29 First Hf Film 30,31 First Al-Si-Cu Alloy Wiring 32 Second Insulating Film Film 33 Second Connection Hole 34 , 35 Second Hf film 36, 37 Second Al-Si-Cu alloy wiring 38 Passivation film
Claims (2)
と、 前記接続孔の内部、および前記絶縁膜上に形成されたハ
フニウム膜と、 前記接続孔の内部に埋め込まれたアルミニウム合金膜と
を備えた半導体装置。1. An insulating film having a connection hole formed on a semiconductor substrate, a hafnium film formed inside the connection hole and on the insulating film, and an aluminum alloy film embedded inside the connection hole. A semiconductor device comprising:
を設ける工程と、 前記接続孔の内部および前記絶縁膜上にハフニウム膜を
形成する工程と、 前記ハフニウム膜上にアルミニウム合金膜形成し、前記
接続孔内部にアルミニウム合金膜を埋め込む工程と、を
備えたことを特徴とする半導体装置の製造方法。2. A step of forming a connection hole in an insulating film provided on a semiconductor substrate, a step of forming a hafnium film inside the connection hole and on the insulating film, and an aluminum alloy film formation on the hafnium film. And a step of burying an aluminum alloy film inside the connection hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30353592A JPH06151429A (en) | 1992-11-13 | 1992-11-13 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30353592A JPH06151429A (en) | 1992-11-13 | 1992-11-13 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06151429A true JPH06151429A (en) | 1994-05-31 |
Family
ID=17922163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30353592A Pending JPH06151429A (en) | 1992-11-13 | 1992-11-13 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06151429A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100363976B1 (en) * | 1998-11-27 | 2002-12-11 | 샤프 가부시키가이샤 | Process for manufacturing a semiconductor device |
-
1992
- 1992-11-13 JP JP30353592A patent/JPH06151429A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100363976B1 (en) * | 1998-11-27 | 2002-12-11 | 샤프 가부시키가이샤 | Process for manufacturing a semiconductor device |
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