JPH06151350A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Especially when ion implantation is performed on an extremely fine region, it is only necessary to devise a resist patterning without adding a special process and without using a special resist. To enable accurate ion implantation without affecting other areas. [Structure] A step of forming a LOCOS 22 on the surface of the semiconductor substrate 20, a step of forming a resist film 28 on the surface of the semiconductor substrate 20, and a step of forming an ion implantation opening 30 in the resist film 28. A method of manufacturing a semiconductor device having at least the following: when forming an ion implantation opening 30 in the resist film 28, the ion implantation opening 3 is formed around the ion implantation opening 30.
A dummy opening region 32 is formed on the LOCOS 22 to isolate the resist film 28 in which 0 is formed from other resist films 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a special resist without adding a special process when ion implantation is performed particularly in an extremely fine region. The present invention relates to a method for manufacturing a semiconductor device, which allows accurate ion implantation without affecting other regions, simply by devising a resist patterning method.

[0002]

2. Description of the Related Art Semiconductor devices have become more and more miniaturized in recent years. In addition, in order to improve the performance of the semiconductor device,
Alternatively, for the purpose of manufacturing a semiconductor device for a special purpose, there is a demand for ion implantation of impurities into a specific fine region. For example, as shown in FIGS. 7 and 8, there is a case where a MOS transistor is formed on the surface of the semiconductor substrate 2 and a specific impurity is desired to be ion-implanted only into the drain region 4 of the MOS transistor.

In such a case, prior to the ion implantation, the selective oxidation element isolation region (LO) is formed on the surface of the semiconductor substrate 2.
COS) 6 is formed by the LOCOS method to form the gate insulating film 8 and the gate electrode 10, and then the semiconductor substrate 2
The surface of is covered with a resist film 12. After that, an ion implantation opening 14 is formed in the resist film 12 in a pattern to be ion-implanted, and ions are implanted through the opening 14. The ion implantation for forming the source region 5 is performed in another process.

[0004]

However, in such a conventional semiconductor device manufacturing process, for example, heat at the time of ion implantation is applied to the resist film, and as shown by an arrow A in FIG. A tensile stress due to heat acts on 12 along the surface direction, and the deformation of the resist film 12 due to the tensile stress concentrates at the edge of the opening 14, and the opening wall is inclined. When the opening wall of the opening 14 is inclined, the substantial film thickness of the resist film 12 located above the source region 5 is reduced. Therefore, at the time of ion implantation through the opening 14, there is a problem that the ion implantation is performed through the resist film 12 even for the source region 5 which should not be implanted.

The present invention has been made in view of the above circumstances, and particularly when ion implantation is performed on an extremely fine region, a special process is not added, and a special resist is not used. An object of the present invention is to provide a method for manufacturing a semiconductor device, which can perform ion implantation accurately without affecting other regions only by devising patterning.

[0006]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a selective oxidation element isolation region on the surface of a semiconductor substrate, and a step of forming a selective oxidation element isolation region on the surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: forming a resist film; and forming an ion implantation opening in the resist film, wherein the ion implantation opening is formed in the resist film. In this case, a dummy opening region for isolating the resist film in which the ion implantation opening is formed from another resist film is formed around the ion implantation opening on the selective oxidation element isolation region. And

[0007]

According to the method of manufacturing a semiconductor device of the present invention, when the ion implantation opening is formed in the resist film, the resist having the ion implantation opening formed around the ion implantation opening is formed. A dummy opening region for isolating the film from another resist film is formed on the selective oxidation element isolation region.
Therefore, the resist film does not have a large area, and even if heat is applied to the resist film, the tensile stress generated in the resist film does not concentrate on the pattern of the ion implantation opening. Therefore, the opening wall of the ion implantation opening is not deformed and tilted by the tensile stress. As a result, when the ions are implanted through the opening, the regions where the ions should not be implanted are not implanted. During the ion implantation, the ions are also implanted from the dummy opening region toward the surface of the semiconductor substrate. However, since the selective oxidation element isolation region is formed below the dummy opening region, the semiconductor substrate is not formed. There is no effect on the elements built above.

By using the manufacturing method of the present invention, it becomes easy to partially change the impurity concentration of the fine impurity diffusion region. For example, it becomes easy to manufacture a high breakdown voltage transistor in which only the drain region of a MOS transistor has an LDD structure. Further, it becomes easy to form a diffusion region for lowering breakdown voltage of the same conductivity type as the channel stopper region, which is connected to the channel stopper region around the lower side of the drain region of the MOS transistor.
This facilitates manufacturing of a memory cell transistor having excellent data writing characteristics.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the drawings.
1 is a plan view of a main part showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the main part taken along line II-II shown in FIG. 1, and FIGS. FIGS. 5 and 6 are cross-sectional views of a main part showing a manufacturing process of a semiconductor device according to a specific example, and FIGS. 5 and 6 are cross-sectional views of a main part showing a manufacturing process of a semiconductor device according to another specific example of the present invention.

As shown in FIGS. 1 and 2, in the embodiment of the present invention, first, for example, L is formed on the surface of a P-type semiconductor substrate 20.
The selective oxidation element isolation region (LOCO
S) 22 is formed in an element isolation pattern. LOCOS2
A gate insulating film 24 is formed on the surface of the semiconductor substrate 20 located between the two by a thermal oxidation method. The thickness of the LOCOS 22 is not particularly limited, but is, for example, 300 to 800.
It is about nm. The oxidation temperature for forming LOCOS 22 is also not particularly limited, but is, for example, 850 to 1000.
It is about ° C. The thickness of the gate insulating film 24 is not particularly limited, but is, for example, about 20 to 50 nm.

Next, a gate electrode 26 is formed in a predetermined pattern on the surface of the gate insulating film 24. Gate electrode 26
Is a polysilicon film formed by, for example, the CVD method.
It is obtained by processing into a predetermined pattern by an etching means such as IE. The gate electrode 26 is not limited to the polysilicon film, and may be formed of a metal film such as aluminum, a metal silicide film such as tungsten silicide, or a polycide film which is a composite film of metal silicide and polysilicon. Gate electrode 2
The film thickness of 6 is not particularly limited, but is, for example, 100 to 3
It is about 00 nm.

After forming the gate electrode 26, a resist film 28 is formed on the entire surface of the semiconductor substrate 20. Next, in this embodiment, the resist film 28 is processed by the photolithography method to form the ion implantation opening 30 in a pattern corresponding to the portion to be the drain region 34. The ion implantation opening 30 is not formed in the portion corresponding to the source region 36.

In this embodiment, at the time of patterning the resist film 28, the ion implantation openings 30 are formed around the ion implantation openings 30 along with the ion implantation openings 30.
A dummy opening region 32 is formed on the LOCOS 22 to isolate the resist film 28 in which 0 is formed from other resist films 28. There is no particular restriction on the pattern of the dummy opening region 32 except that it is formed on the LOCOS 22,
The distance L from the portion where the source region 36 is formed is 1 μm
The above is preferable.

In the method of manufacturing the semiconductor device of this embodiment, when the ion implantation opening 30 is formed in the resist film 28, the ion implantation opening 30 is formed around the ion implantation opening 30. A dummy opening region 32 for isolating the resist film 28 on which is formed from another resist film 28,
It is formed on the LOCOS 22. Therefore, the resist film 2
8 does not have a large area, and even if heat is applied to the resist film 28, the tensile stress generated in the resist film 28 does not concentrate on the pattern of the ion implantation opening 30. Therefore, the opening wall 31 of the ion implantation opening 30 is not deformed and tilted by the tensile stress. As a result, in the ion implantation through the opening 30, the source region 36 which should not be ion-implanted is not ion-implanted.

At the time of ion implantation, ions are also implanted from the dummy opening region 32 toward the surface of the semiconductor substrate 20, but since the LOCOS 22 is formed below the dummy opening region 32, Semiconductor substrate 2
There is no effect on the elements built on zero.

Next, a more specific method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. In the embodiment shown in FIGS. 3 and 4, first, as shown in FIG. 3, the gate electrode 26 is formed in the same manner as in the above-described embodiment, and then the resist film 28a is formed on the entire surface of the semiconductor substrate. Next, the resist film 28a is patterned by photolithography. At that time, an ion implantation opening 30a having an opening corresponding to the drain region of the MOS transistor is formed. Moreover, this opening 30a
At the same time, the dummy opening region 3 is formed around the ion implantation opening 30a so as to isolate the resist film 28a having the ion implantation opening 30a from other resist films 28a.
2a is formed on the LOCOS 22.

Next, ion implantation is performed through the ion implantation opening 30a to form an N ⁻ region 40 having a relatively low impurity concentration in a portion corresponding to the drain region 34a of the MOS transistor. At that time, for the same reason as in the above-described embodiment, the opening wall portion 31a of the ion implantation opening portion 30a is not inclined. As a result, in the ion implantation through the opening 30a, the source region 36a, which should not be ion-implanted, is not ion-implanted.

Next, as shown in FIG. 4, a resist film 28 is formed.
a is removed, and a part of the gate electrode 26 and the drain region 34 are removed.
A resist film 41 that covers a part of a is formed, and second-stage ion implantation is performed on the surface of the semiconductor substrate 20.
At the time of this ion implantation, a relatively high concentration N ⁺ region 42 is formed in the source region 36a, and a relatively high concentration N ⁺ region 43 is formed in a part of the drain region 34a. As a result, in the MOS transistor of the present embodiment, only the drain region 34a has a structure similar to a so-called LDD structure (broadly called an LDD structure), and the breakdown voltage of the MOS transistor is improved.

That is, in this embodiment, the manufacture of the high breakdown voltage transistor becomes easy. Although the conductivity type of the impurity diffusion regions of the source / drain regions is N type in this embodiment, it may be P type which is the opposite conductivity type. In that case, the conductivity type of the semiconductor substrate 20 is reversed.

Next, another embodiment of the present invention will be described. In this embodiment, first, as shown in FIG. 5, a gate electrode 26 is formed in the same manner as in the above-described embodiment, and then a resist film 28b is formed on the entire surface of the semiconductor substrate 20. Next, the resist film 28b is patterned by photolithography. At this time, the ion implantation opening 30b is formed in a pattern corresponding to the drain impurity diffusion layer of the MOS transistor. Moreover, a dummy opening region 32b for isolating the resist film 28b having the ion implantation opening 30b from the other resist film 28b is formed on the LOCOS 22 along with the opening 30b. Form.

Next, ion implantation is performed through the ion implantation opening 30b to form a P ⁺ breakdown voltage lowering diffusion region 44 in a portion corresponding to the drain region 34b of the MOS transistor. The diffusion region 44 is an impurity diffusion region of P ⁺ which is connected to the channel stopper region 46 and has the same conductivity type as the channel stopper region 46. At that time, for the same reason as the above-mentioned embodiment,
The opening wall 31b of the ion implantation opening 30b does not tilt. Therefore, in the ion implantation through the opening 30b, the source region 36b which should not be ion-implanted is not ion-implanted.

Next, as shown in FIG. 6, a resist film 28 is formed.
b is removed, and second-stage ion implantation is performed on the surface of the semiconductor substrate 20 using the gate electrode 26 as a mask. During this ion implantation, a relatively high concentration N ⁺ region 50 is formed in the source region 36b, and a relatively high concentration N ⁺ region 43 is formed in the drain region 34b in a self-aligned manner with respect to the gate electrode 26. To do.

As a result, in the MOS transistor of this embodiment, since the withstand voltage lowering diffusion region 44 of the same conductivity type as that of the channel stopper region is previously formed around the drain region 34b only under the drain region 34b, the drain region 34b is not formed. Withstand voltage decreases, and this MOS transistor is
When used for a memory cell transistor such as a ROM, hot carriers are easily generated and the data writing characteristics are improved. On the source side, the breakdown voltage does not decrease, and the data erasing characteristic utilizing the tunnel effect is good.

That is, in this embodiment, it becomes easy to manufacture a memory cell transistor having excellent data writing characteristics. Although the conductivity type of the impurity diffusion regions of the source / drain regions is N type in this embodiment, it may be P type which is the opposite conductivity type. In that case, the semiconductor substrate 2
0, the conductivity type of the breakdown voltage lowering diffusion region 44 and the channel stopper region 46 are reversed.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention.

[0026]

As described above, according to the present invention, particularly when ion implantation is performed on an extremely fine region, without adding a special process and without using a special resist, Only by devising the patterning of the resist, it becomes possible to perform ion implantation accurately without affecting other regions. Therefore, by using the manufacturing method of the present invention, it becomes easy to partially change the impurity concentration of the fine impurity diffusion region. For example, LD only the drain region of the MOS transistor
The high breakdown voltage transistor having the D structure is easily manufactured. In addition, a memory cell transistor having excellent data write characteristics, which is formed below the drain region of the MOS transistor, is connected to the channel stopper region, and has a diffusion region for lowering breakdown voltage of the same conductivity type as that of the channel stopper region. Will be easier to manufacture.

[Brief description of drawings]

FIG. 1 is a plan view of relevant parts showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts taken along the line II-II shown in FIG.

FIG. 3 is a sectional view of a key portion showing the manufacturing process of the semiconductor device according to the more specific example of the present invention.

FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment;

FIG. 5 is a sectional view of a key portion showing the manufacturing process of the semiconductor device according to the more specific example of the present invention. Is.

FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment;

FIG. 7 is a main-portion plan view showing the manufacturing method of the semiconductor device according to the conventional example.

8 is a cross-sectional view of a main part taken along the line VIII-VIII shown in FIG.

[Explanation of symbols]

20 ... Semiconductor substrate 22 ... Selective oxidation element isolation region (LOCOS) 24 ... Gate insulating film 26 ... Gate electrodes 28, 28a, 28b ... Resist film 30, 30a, 30b ... Ion implantation opening 31, 31a, 31b ... Opening wall Part 32, 32a, 32b ... Dummy opening region 34, 34a, 34b ... Drain region 36, 36a, 36b ... Source region 40 ... N ^- region 42, 43 ... N ⁺ region 44 ... Breakdown voltage reducing diffusion region 46 ... Channel stopper region 48, 50 ... N ⁺ area

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical location H01L 21/336 29/784 7210-4M H01L 27/10 434 7377-4M 29/78 301 P

Claims (4)

[Claims] 1. A step of forming a selective oxidation element isolation region on the surface of a semiconductor substrate, and a resist film is formed on the surface of the semiconductor substrate, and an ion implantation opening is formed in the resist film. A method of manufacturing a semiconductor device having at least a step, wherein an ion implantation opening is formed around the ion implantation opening when the ion implantation opening is formed in the resist film. A method of manufacturing a semiconductor device, wherein a dummy opening region for isolating the resist film from another resist film is formed on the selective oxidation element isolation region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity concentration of an impurity diffusion region formed in the semiconductor substrate is partially changed. 3. The method of manufacturing a semiconductor device according to claim 1, wherein only the drain region of the MOS transistor formed on the semiconductor substrate has an LDD structure. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the channel stopper region is connected to the lower periphery of the drain region of the MOS transistor formed on the semiconductor substrate and is connected to the channel stopper region. A method of manufacturing a semiconductor device, comprising forming a diffusion region for lowering breakdown voltage of the same conductivity type.