JPH06151104A - Positive temperature coefficient thermistor element - Google Patents

Abstract

PURPOSE:To increase reliability by carrying out a grinding process of the peripheral side surface of a semiconductor porcelain having plated layers on both principal surfaces thereof along the direction perpendicular to the plated surfaces, thereby to prevent degradation of the F breakdown strength characteristics. CONSTITUTION:On both principal surfaces of a barium titanate semiconductor porcelain 1 shaped in a circular flat plate having a predetermined thickness, plated layers 2 of nickel or the like having a predetermined thickness are formed. The undesired plated layer depositing on the peripheral side surface 1a of the semiconductor porcelain 1 is removed by carrying out a grinding process along the direction perpendicular to the plated layers 2 formed on both principal surfaces, or the thickness direction of the semiconductor porcelain 1. By this, degradation of the F breakdown strength characteristics can be prevented to increase reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a positive temperature coefficient thermistor element (hereinafter referred to as PTC element).

[0002]

2. Description of the Related Art Conventionally, a PTC element is generally constructed by using a barium titanate-based semiconductor porcelain having a positive characteristic that a resistance value increases as the element temperature rises. As shown in FIG. 2, a plating layer 2 made of nickel or the like and a silver paste or the like are baked on both main surfaces of the semiconductor porcelain 1 in the shape of a circular flat plate having a predetermined thickness. The electrode layer 3 is formed. Then, in forming the plating layer 2 covering both surfaces of the semiconductor porcelain 1, after performing the plating treatment over the entire surface of the semiconductor porcelain 1, the unnecessary plating layer adhered on the peripheral side surface 1a of the semiconductor porcelain 1 is formed. The procedure of removing only this is adopted, and the unnecessary plating layer at this time is removed by the grinding process along the circumferential direction of the semiconductor ceramic 1.

[0003]

By the way, in the PTC element, when an inrush current more than its own flash withstand voltage characteristic (F withstand voltage characteristic: breakdown characteristic against inrush current) flows, a layered crack as shown in FIG. It is known that destruction occurs. Further, when the PTC element is produced according to the conventional procedure, the unnecessary plating layer is removed by the grinding process along the circumferential direction of the semiconductor ceramic 1. Therefore, the semiconductor ceramic 1 from which the plating layer is removed is removed.
There are innumerable grinding flaws along the circumferential direction on the circumferential side surface (in the figure,
As a result, a layered crack is likely to occur when an inrush current flows, and the F breakdown voltage characteristic of the PTC element is deteriorated.

The present invention was devised in view of such inconveniences, and an object thereof is to provide a PTC element capable of preventing deterioration of F breakdown voltage characteristics and improving reliability.

[0005]

In the PTC element according to the present invention, in order to achieve such an object, the peripheral side surface of the semiconductor porcelain having plating layers formed on both main surfaces is oriented in a direction perpendicular to the plating layers. Grinding along

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing a simplified outer shape of a PTC element according to this embodiment.

This PTC element is equipped with a barium titanate-based semiconductor porcelain 1 in the form of a circular flat plate having a predetermined thickness, and both main surfaces of this semiconductor porcelain 1 are plated with a predetermined thickness of nickel or the like. Layer 2 has been formed.
The unnecessary plating layer (not shown) attached to the peripheral side surface 1a of the semiconductor ceramic 1 is oriented in a direction orthogonal to the plating layers 2 formed on both main surfaces thereof, that is,
It is removed by grinding along the thickness direction of the semiconductor porcelain 1. The thin lines in FIG. 1 indicate innumerable grinding flaws left on the peripheral side surface of the semiconductor ceramic 1 from which the plating layer has been removed.

By the way, in forming these plating layers 2, the conventional procedure is to perform a plating treatment over the entire surface of the semiconductor porcelain 1 and then remove only the plating layers adhering to the peripheral side surface 1a. Similar to the example.
When performing the grinding process along the thickness direction of the semiconductor porcelain 1, although not shown, a predetermined number of semiconductor porcelains 1 are stacked in advance along the thickness direction and a wax (wax material) is used. After being solidified by hardening, a group of semiconductor ceramics 1 in the shape of a long rod is rotated along the circumferential direction and the side surfaces along the longitudinal direction are ground. Further, when the electrode layer 3 is formed by baking a silver paste or the like on each of the plating layers 2 thus formed, the PTC element is completed.

Next, the inventor of the present invention evaluated the F breakdown voltage test and reliability in order to compare the characteristics of the PTC element according to the present embodiment having the above-described configuration and the PTC element having the conventional configuration. A low temperature adiabatic load test was conducted to obtain the test results shown in Table 1. Therefore, these characteristic comparison tests will be described.
First, in these tests, the composition of the semiconductor porcelain 1 was (Ba _{0 .796} S) in both the example product and the conventional product.
r _{0 · 20} Y _{0 · 004} ) Ti _{1 · 005} O ₃ + 0.0007MnO + 0.
02 SiO ₂ , and the size of each PTC element after baking is 14 mm in diameter and 3 mm in thickness, while the number of samples in the F breakdown voltage test is 100.
The number of samples in the low temperature adiabatic load test is set to 10.
In addition, the setting condition during the low temperature adiabatic load test is AC1.
40V, ambient temperature -40 ℃, load resistance 0Ω, test time 1
It is set to 000 hr. Note that ρ (Ω · cm) in Table 1
Indicates the specific resistance value, and ΔR (%) indicates the resistance change rate with respect to the initial resistance value.

[0010]

[Table 1]

According to Table 1, although the specific resistance values of the example product and the conventional product are not so different from each other, the F breakdown voltage of the example product is better than that of the conventional product. It can be seen that the characteristics are significantly improved, and ΔR is improved. Further, in the conventional example product, the destruction may occur due to the low temperature adiabatic load test, whereas in the example product, such destruction is not observed at all, so it is clear that the reliability is improved. .

[0012]

As described above, the P according to the present invention
In the TC element, the unnecessary plating layer is removed by grinding the peripheral side surface of the semiconductor porcelain having the plating layer formed on both main surfaces along the direction orthogonal to the plating layer. As a result, it is possible to prevent the deterioration of the device and improve it. As a result, it is possible to obtain an effect of significantly improving the reliability.

[Brief description of drawings]

FIG. 1 is a perspective view showing a simplified outer shape of a PTC element according to the present embodiment.

FIG. 2 is a perspective view showing a simplified outer shape of a PTC element according to a conventional example.

FIG. 3 is a perspective view showing the broken state in a simplified manner.

[Explanation of symbols]

 1 semiconductor porcelain 1a its peripheral side surface 2 plating layer

Claims (1)

[Claims] 1. A plating layer (2) is formed on both main surfaces of a semiconductor porcelain (1) in the shape of a circular plate having a predetermined thickness, and the peripheral side surface (1a) of the semiconductor porcelain (1) is formed. The PTC thermistor element is characterized in that the top is ground along a direction orthogonal to the plating layer (2).