JPH0614016A - Timing extract device - Google Patents

Abstract

PURPOSE:To reduce the cost by adopting a digital circuit for each section so as to prevent the effect of external environment and simplifying the configuration. CONSTITUTION:A timing of reception data S is fed to a phase comparator circuit 12, in which the timing signal is compared with a clock pulse QD fed from a 1/16 frequency division counter 16, and the result is fed to a phase adjustment circuit 17. When the reference clock pulse K2, that is, the timing of the clock pulse QD is led, a count stop signal EP is fed to the counter 16, then the phase of the clock pulse QD is delayed by a prescribed quantity. When the timing of the reference clock pulse K2 is lagged, an inverting signal H is fed to a selector 15 and the count of the clock pulse K4 being the reference of the clock pulse QD is quickened. Then the phase of the clock pulse QD is led. Each section consists of a digital circuit and the external effect is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing extraction device suitable for application to a data transmission device.

[0002]

BACKGROUND OF THE INVENTION In a data receiving apparatus, for example, it is possible to accurately process received data by operating each unit at the timing of received data. In other words, if each unit operates regardless of the timing of the received data, the data will be different from the data transmitted on the transmission side.

Therefore, a data receiving device is usually provided with a timing extracting device as shown in FIG. This timing extracting device detects the timing of the received data S, generates a reference clock pulse K2 corresponding to this timing, and supplies this to each unit. The reception data S is accurately processed by operating each unit in synchronization with the reference clock pulse K2. The received data S includes a timing component, and the CMI (Coded Mark Inversio) as described below is used.
n) code or DMI (Differential Mark Inversion) code is used.

Here, the CMI code and the DMI code will be described. Now, as shown in FIG. 5A, the frequency f0
NRZ as shown in FIG.
When there is original data of the method, when this is converted into a CMI code, it becomes data as shown in FIG.
That is, in the CMI code, the clock frequency is 2f0 as shown in FIG. 7C, and when the original data is "0", it is converted to "01", and when the original data is "1", this is converted. It is converted into "00" and "11" alternately.

FIG. 1E shows a DMI code. This DM
The clock frequency of the I code is 2f0 as in the CMI code. When the original data is "0" and it is before and after the data "1", it is "01" or "10".
When the original data is continuously "0", "01" or "10" is continuously converted. Furthermore, if the original data is "1", change it to "00" and "1".
It is converted into 1 "alternately. CMI code and D
The MI code makes it possible to retain timing information even when "0" or "1" continues in the original data.

When the reception data S (FIG. 6A) having a timing component is input to the timing extraction device shown in FIG. 4, this is supplied to the monomulti 1. The mono-multi 1 is triggered by the edges (rising edge and falling edge) of both sides of the received data S, and from there, a clock pulse K1 having a frequency component twice that of the received data S (FIG. 6 (b)).
Is output.

The tank circuit 2 resonates at the timing of the clock pulse K1, and as a result, a sine wave signal (see FIG. 6) is generated.
(C)) occurs. A crystal oscillator, an LC circuit, or the like is used as the tank circuit 2. The output of the tank circuit 2 is supplied to the comparator 3, where it is converted into a reference clock pulse K2 (FIG. 6 (d)) and supplied to each unit.

When the reference clock pulse K2 thus generated does not match the timing of the received data S,
That is, when the received data S is not processed normally, it is usual to adjust the pulse width b of the clock pulse K1 output from the monomulti 1 to match the timings of both.

For example, when the timing of the reference clock pulse K2 is behind the received data S, the pulse width b of the clock pulse K1 output from the monomulti 1 is reduced. As a result, the phase of the output signal of the tank circuit 2 is advanced, which causes the phase of the reference clock pulse K2 to be advanced, so that it is possible to match the timing of the received data S. On the contrary, when the timing of the reference clock pulse K2 is earlier than the received data S, the pulse width b of the output signal of the monomulti 1 may be increased.

[0010]

Since the above-mentioned timing extraction device uses an analog circuit, it is susceptible to noise and temperature, and the circuit scale becomes large. Further, when the crystal oscillator is used for the tank circuit 2, there is a problem that the frequency accuracy is good but it is expensive, and when the LC circuit is used, the frequency accuracy is deteriorated.

Therefore, the present invention solves the above-mentioned problems, and proposes a timing extraction device which can be easily constructed only by a digital circuit and which can prevent the influence of the external environment.

[0012]

In order to solve the above problems, in the present invention, timing detecting means for detecting the timing of input data, means for generating a reference clock pulse corresponding to this timing, input data and a reference. The present invention is characterized by including phase comparison means for comparing the phases of clock pulses and phase adjustment means for adjusting the phase of the reference clock pulse based on the comparison result of the phase comparison means.

[0013]

In FIG. 1, the input received data S (S1, S1,
S2) (FIG. 2) is supplied to the phase comparison circuit 12. On the other hand, the clock pulse K3 generated by the clock generator 13 is supplied to the exclusive OR circuits 14A and 14B, where the master clock pulse MCLK (A) and the inverted master clock pulse MCLK are out of phase with each other by 0.5 clock. (B) occurs, and this is the selector 15
Is supplied to.

The selector 15 first selects the master clock pulse MCLK (A) and supplies it to the 16-frequency division counter 16 as a clock pulse K4. And 0-
Counts up to 15 clocks. Based on this, clock pulses QA to QD whose cycle is sequentially doubled are generated and supplied to the phase comparison circuit 12. The clock pulse QD is used as the reference clock pulse K2.

In the phase comparison circuit 12, the clock pulse Q
Phase shift amount determination sections -D to + D are set based on A to QD, and which section the rising edge of the reception data S (S1, S2) is in is detected. Then, the detected divisions (A to D) and their signs (+ or −) are supplied to the phase adjusting circuit 17, where the adjustment is performed by the adjustment amount set corresponding to the divisions as shown in FIG. To be done. That is, when the sign is "-", the inverted signal H is generated and this is the selector 15
Is supplied to. When the sign is "+", the counter stop signal EP is generated, and this is the 16 frequency division counter 16
Is supplied to.

When the inverted signal H is input to the selector 15 once, the count of the clock pulse K4 is advanced by 0.5 clocks, which causes the reference clock pulse K2.
The phase of is advanced by 0.5 clock. Similarly, when the inverted signal is input twice, the reference clock pulse K2 is advanced by one clock.

When the count stop signal EP is input to the 16-frequency division counter 16 once, the clock pulse K4
Counting is stopped for one clock. As a result, the reference clock pulse K2 is delayed by one clock. By repeating such adjustment processing, it becomes possible to match the timing of the reference clock pulse K2 with the received data S (S1, S2).

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the timing extraction device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the structure of a timing extraction device according to the present invention, and FIG. 2 shows the timing of each signal. In FIG. 1, received data S1 (FIG. 2 (h)) or received data S2 (FIG. 2 (k)) such as a DMI code or CMI code having a timing component is input to a phase comparison circuit 12, where, for example, received data is received. The timing is detected by detecting the rising edges of S1 and S2.

On the other hand, the reference clock pulse K2 (FIG. 2 (f)) corresponding to the timing of the reception data S1 and S2 is generated by the following procedure. That is, the clock pulse K3 is generated in the clock generator 13, and this is input to the exclusive OR circuits 14A and 14B. A "high" signal is input from the power supply VCC to the exclusive-OR circuit 14A, which causes the master clock pulse MCLK (A) having the opposite phase to the clock pulse K3 (see FIG. 2).
(A)) is generated.

A ground or "low" signal is input to the other exclusive-OR circuit 14B, which causes an inverted master clock pulse MCLK (B) having the same phase as the clock pulse K3 (FIG. 2 (b)). Is generated. That is, the master clock pulse MCLK (A) and the inverted master clock pulse MCLK (B) are out of phase with each other by 0.5 clock.

The master clock pulse MCLK (A) and the inverted master clock pulse MCLK (B) are supplied to the selector 15, and the master clock pulse M is initially supplied.
CLK (A) is selected. Then, the selector 15 outputs the clock pulse K4. This clock pulse K4 is supplied to the 16-frequency division counter 16, where 0 to
Counts up to 15 clocks. The 16-frequency division counter 16 sequentially doubles the cycle of the clock pulse K4 to generate clock pulses QA to QD (see FIG. 2).
(C) to (f) are generated. Then, the clock pulse QD at the final stage is used as the reference clock pulse K2.

The clock pulses QA to QD are supplied to the phase comparison circuit 12, and here, in order to determine how much the phase shifts with respect to the received data S1 and S2, a phase shift amount determination section (FIG. 2 (g)). ) Is set. In this example, as the phase shift amount determination category, a total of 7 categories from category -D to category + D are set.

That is, section-D is for clock pulse K4.
0th to 1st clock, section-C is set to 2nd to 4th clocks, section-B is set to 5th to 6th clocks, section A is set to 7th to 8th clocks. Here, when the sign is "-" (minus), the reference clock pulse K2
Indicates that it is behind the received data S, and that the sign is "+" (plus) indicates that the reference clock pulse K2 is ahead of the received data S.

The phase shift amount judgment sections (A to D) and their signs (+ or −) thus detected are supplied to the phase adjusting circuit 17, where the timing of the reference clock pulse K2 is received data. Adjustments are made to match S1 and S2. Here, the phase adjustment as shown in FIG. 3 is performed corresponding to the input sections -D to + D.

That is, when the section A is input, the phase adjustment amount is set to "0" and the state is maintained as it is. When the section B is input, the phase adjustment amount is set to "0.5" clock, when the section C is input, the phase adjustment amount is set to "1.0" clock, and when the section D is input. The amount of phase adjustment is "1.5" clock. These adjustment amounts are adjusted in the delay direction when the sign is "+", and adjusted in the advance direction when the sign is "-".

Therefore, when the sign of the phase shift amount judgment section (-B) is "-" like the received data S1, the phase adjustment circuit 17 sends the inverted signal H, which is the selector 1.
5 is supplied. Then, in the selector 15, the inverted signal H
Input once, master clock pulse MCLK
Inversion master clock pulse MCLK instead of (A)
(B) is selected, and this is output as the clock pulse K4.

At this time, the master clock pulse MCLK
Since (A) and the inverted master clock pulse MCLK (B) have a cycle difference of 0.5 clocks, the count in the 16-division counter 16 at the moment when this is inverted is:
As shown in FIG. 2 (j), it is advanced by 0.5 clocks. When the inverted signal H is input one more time, that is, twice in total, the inverted master clock pulse MCLK (B) is input.
Instead, the master clock pulse MCLK (A) is selected and output.

At this time, it can be seen that the counting by the 16 frequency division counter 16 is advanced by 1.0 clock. Similarly, if the inverted signal H is transmitted three times, the count of the clock pulse K4 is advanced by 1.5 clocks. Therefore, it becomes possible to advance the reference clock pulse K2, which was delayed with respect to the received data S1, by a predetermined amount.

On the contrary, the received data S2 (see FIG.
As shown in (k)), when the sign of the phase shift amount determination category (+ C) is “+”, that is, when the reference clock pulse K2 is ahead of the received data S2, the phase adjustment circuit 17 causes the count stop signal EP ( Enable stop signal,
2 (l)) occurs, and this is supplied to the 16-frequency division counter 16. As a result, as shown in FIG.
The counting operation of the divide-by-6 counter 16 is stopped for one clock. Therefore, the reference clock pulse K2 is 1
It will be delayed by the clock.

Similarly, when the count stop signal EP is input twice, the reference clock pulse K2 is delayed by 2 clocks. When the counting by the 16 frequency division counter 16 is stopped by 0.5 clocks, that is, when the reference clock pulse K2 is delayed by 0.5 clocks, the inverted signal H is sent to the selector 15 in the same manner as described above.
Should be input once, and the count stop signal EP should be input to the 16-frequency division counter 16 once. When the reference clock pulse K2 is delayed by 1.5 clocks, the inversion signal H is input to the selector 15 three times and the count stop signal EP is input to the 16 frequency division counter 16 three times.

In this way, by adjusting the phase of the reference clock pulse K2, that is, the clock pulse QD generated by the 16-frequency division counter 16, the timing of the reference clock pulse K2 is kept close to the reception data S (S1, S2). It becomes possible to kick. In this example, the maximum is 1.5.
Since the adjustment is for clocks, when the timings of the reference clock pulse K2 and the received data S (S1, S2) do not match in one adjustment, the phase is adjusted by the same method. Further, since the timing of the reception data S (S1, S2) may always change, this phase adjustment is continuously performed.

The reference clock pulse K2 thus generated is supplied to the flip-flop circuit 18, where the received data S is received at the timing of the reference clock pulse K2.
(S1, S2) is taken in and supplied to each part. In this example, the phase adjustment circuit 17 is connected to the synchronization protection circuit 1
9 is connected, and the reception data S (S1, S
When 2) moves back and forth between the division −D and the division + D of the phase shift amount determination divisions, the deviation amount between the reference clock pulse K2 and the reception data S (S1, S2) is large and the data is missing. This number is counted when it is determined that there is a possibility.

Then, when the predetermined number of times is counted, the out-of-sync signal is supplied to each section, and it is determined whether the data is adopted or discarded. At this time, for example, the alarm 20 may be sounded to generate an alarm. Further, in this example, the reference clock pulse K
Although the 16-frequency division counter 16 is used as the generation means of 2,
Instead of this, for example, a divide-by-8 counter or a divide-by-32 counter may be used.

[0035]

As described above, according to the present invention, the timing detecting means for detecting the timing of the input data, the generating means of the reference clock pulse corresponding to this timing, and the phase of the input data and the reference clock pulse are compared. Based on the comparison result of the phase comparison means and the phase comparison means,
It is provided with a phase adjusting means for adjusting the phase of the reference clock pulse.

Therefore, according to the present invention, it is possible to digitize each part, and thereby prevent the influence of the external environment. In addition, each part can be easily configured, which has the effect of reducing costs.

[Brief description of drawings]

FIG. 1 is a block diagram of a timing extraction device according to the present invention.

FIG. 2 is an explanatory diagram illustrating the timing of each signal of the timing extraction device according to the present invention.

FIG. 3 is an explanatory diagram illustrating an example of a phase adjustment amount in a phase shift amount determination section.

FIG. 4 is a configuration diagram of a conventional timing extraction device.

FIG. 5 is an explanatory diagram illustrating a CMI code and a DMI code.

FIG. 6 is an explanatory diagram for explaining the timing of each signal in the conventional timing extraction device.

[Explanation of symbols]

 1 Mono-multi 2 Tank circuit 3 Comparator 12 Phase comparison circuit 13 Clock generator 14A, 14B Exclusive OR circuit 15 Selector 16 16 Frequency divider counter 17 Phase adjustment circuit 18 Flip-flop circuit 19 Synchronization protection circuit 20 Alarm

Claims (1)

[Claims] 1. A timing detecting means for detecting the timing of input data, a generating means for generating a reference clock pulse corresponding to the timing, a phase comparing means for comparing the phases of the input data and the reference clock pulse, and the phase. A timing extraction device comprising phase adjustment means for adjusting the phase of the reference clock pulse based on the comparison result of the comparison means.