JPH0613880A - Buffer circuit - Google Patents

Abstract

PURPOSE:To shorten the rise/fall time of output signals by controlling the drivability of an output buffer. CONSTITUTION:When the logical value of a control signal Cont is '1', a data signal Data is outputted to output OUT. the logical value '1' is supplied to a buffer drivability control signal Drive before the output OUT is turned into a driving state. Transistors TR3 and TR4 with high drivability are connected to the Drive. When the logical value of the Count is turned to '1', the output OUT conducts the transistors TR3 and TR4 and the transistors TR1 and TR2 with low drivability and starts driving. The transistors TR3 and TR4 are made non-conducted before the output OUT is turned to a non driving state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit of a semiconductor integrated circuit, and more particularly to improvement of an output buffer of a terminal for transferring data divided by time.

[0002]

2. Description of the Related Art A semiconductor integrated circuit can incorporate a large number of logic circuit functions therein, but a semiconductor chip is extremely small and the number of terminals for inputting / outputting data to / from the logic circuit is limited. With the progress of semiconductor integrated circuit technology, the degree of integration has improved,
A larger number of data inputs / outputs are required, and a method of inputting / outputting one type of data with a single terminal cannot be dealt with. In the semiconductor integrated circuit of this embodiment, data is output to terminals by dividing the data by time. A transfer method (hereinafter referred to as time division transfer) is adopted.

The present invention provides an optimum output buffer circuit for time division transfer. In time division transfer, terminals of a plurality of integrated circuit chips are connected to a common signal line, one of the plurality of chips outputs data to the common signal line and the other chip outputs data of the common signal line by dividing the time. Enter to transfer the data. The time-division transfer requires an output buffer capable of the above control. That is, the logical value "1",
In addition to the output drive state of "0", there is a state of high impedance "Z". In this state "Z", an output buffer that does not affect the output of other chips by disconnecting from the common bus is provided. Needed.

FIG. 1 is a block diagram for explaining the time-division transfer, which is a plurality of integrated circuit chips (Chip A, Chip A).
B, Chip C) output buffer circuit (Buf
The output of A, Buf B, Buf C) is the terminal (PA, P
B, PC) to the common signal line COM.

The output buffer circuit (Buf A, Bu
f B, Buf C) are control signals (Cont A, Cont B, Cont) indicating respective time division timings.
C), and when the control signal is at the logic level "1", output data (Data A, Data B, Data)
a C) is output, and when the control signal has a logic value of “0”, it is in a high impedance state “Z” and does not affect the outputs of other chips.

FIG. 2 is a diagram showing a conventional output buffer circuit, which includes an inverting circuit I and an AND gate circuit. The signal Cont that controls the output state and high impedance state of the output circuit is two The connection point of the transistors becomes the output OUT of the buffer circuit.

When the data signal Data is the logical value "1" and the control signal Cont is the logical value "1", "(Power supply potential) is driven.

When the data signal Data is the logical value "0" and the control signal Cont is the logical value "1", it is inverted. The drive state becomes the value “0” (ground potential).

When the control signal Cont has a logical value "0", the output of the data signal Data inverting circuit I is The output OUT is in a high impedance state.

FIG. 3 is a time chart for explaining the time division transfer. The common signal line COM of FIG. 1 and the control signals (Cont A, Cont B, Cont) of each chip are shown.
C Becomes a logical value "1", and the control signal (Con
t B, Cont C) becomes a logical value “0”, and the data DataA of the chip A is output to the common signal line COM.

[0011] Value "1", control signals of other chips (Cont A, Co
nt C) is a logical value “0 The control signal Cont C of the chip C has a logical value "1", the control signals (Cont A, Cont B) of the other chips have a logical value "0", and the data DataC of the chip C is output. The time-division transfer is performed when one of the chips outputs data to the common signal line and another chip captures the logical value on the signal line.

The portion indicated by the dotted line in the waveform of the common signal line COM is the control signal (Cont A, Cont) of all the chips.
B, Cont C) is a logical value "0", indicating that the common signal line is in a high impedance state.

[0013]

To increase the data transfer amount of time division transfer, there is a method of shortening the time during which each chip outputs data to the common signal line, and a time during which the common signal line is in a high impedance state. There is a way to shorten.

Conventionally, the driving capability of the output buffer circuit of each chip is improved, and when the control signal changes from the logical value "0" to "1", the effective logical value data is output to the common signal line in a short time. Method 1 was taken.

The second method is to reduce dead time not involved in data transfer and is expected to be very effective.
There is a limit in the conventional buffer circuit. High common signal line This is provided for the purpose of preventing the above. As explained in the example of FIG. 3, the control signal Cont A becomes “0” from the logical value “1” when the output time TA of the chip A ends.
The output buffer circuit is composed of a plurality of stages of logic circuits, and there is a delay due to switching of the logic circuits, and it takes some time for its output to change from an output drive state to a high impedance state.

When the output of the chip A is not in a completely high impedance state, the control signal Cont B becomes a logical value "1" and its output buffer is in a driving state, the output buffers of the chip A and the chip B are driven. Compete on the common signal line.

A plurality of chips are connected to the common signal line, the wiring capacitance thereof is large, and the output buffer is driven in order to charge and discharge the charges on the common signal line in a short time to output effective logical value data. When the output buffer drive competes, the power supply grounds are short-circuited via the drive transistor and an abnormal current flows.

As an example, even a buffer circuit using a field effect transistor as a drive transistor may have several tens of mA.
If the phenomenon occurs at multiple terminals, the current value will destroy the integrated circuit. In addition, the data logical value on the common signal line is also undefined, and normal data transfer cannot be performed.

Therefore, in the time-division transfer by the conventional output buffer, a high input is used so that another chip does not start output until the buffer becomes a higher impedance state than the output state.

The field effect transistor, which is an element of the integrated circuit, is a voltage drive element, and the potential showing the logical value on the common signal line is important in the time division transfer. It is necessary that the output buffer have a high drive capability rather than a high impedance state. Since the data logic value is output to the common signal line in a short time when it is in the output state, the driving ability to hold the logic value potential after the common signal line becomes the potential corresponding to the data logic value. Good.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a buffer circuit capable of time-division transfer without providing an invalid high impedance time which is not involved in data transfer.

[0022]

SUMMARY OF THE INVENTION The present invention controls the driving ability of a buffer circuit in an output starting state. When the output impedance is changed from a high impedance state, the buffer circuit is operated with a high driving ability to output the output driving state. It is characterized by operating the buffer circuit by lowering the driving capability before it becomes a high impedance state.

According to the present invention, the output competes on the common signal line for a transient state in which one chip output buffer changes from the output driving state to the high impedance state and another chip output buffer changes from the high impedance state to the output driving state. In this case, the driving capability is prioritized, the potential on the common signal line can be determined by the ratio of the driving capability, and normal data transfer is possible. Further, the current flowing between the output buffers can be limited, and the abnormal current value that would damage the integrated circuit does not occur.

The time division transfer using the buffer circuit according to the present invention does not participate in data transfer. The quantity can be increased and the number of terminals can be reduced.

Further, since the buffer circuit is operated with a high driving ability when the output driving is started, the rise time of the output signal can be shortened and the speed can be increased.

[0026]

The present invention will now be described in detail with reference to the drawings according to the embodiments.

FIG. 4 is a circuit connection diagram showing an output buffer circuit according to an embodiment of the present invention. State control signal Cont, buffer drive capacity control signal Dr
It has an ive input.

The data signal Data is input to the first AND gate circuit G1 and the inverting circuit 1, Are connected in parallel. The output drive transistors have different drive capabilities due to the distribution of element sizes in the integrated circuit. The first and second transistors have a low drive capability and a third drive capability.
And the fourth transistor has high driving capability.

[0029] Although the driving ability is set according to the element size of the transistor, the driving ability can be set by connecting a resistor / constant current source circuit or the like in series with the driving transistor.

FIG. 5 is a time chart for explaining the operation of the embodiment of the present invention. OUT is the output of the buffer circuit, and the solid line portion is the output state of the logical value "1" or "0",
The dotted line indicates the high impedance state, and Co
nt indicates a buffer state control signal, and Drive indicates a drive capacity control signal. Buffer state control signal Cont is a logical value The output OUT is in a high impedance state.

When the buffer state control signal Cont is the logical value "1", the drive capability control signal Drive is set. , The first and third AND gate circuit outputs are logical value "1" inversion circuit I, the second and fourth Thus, the buffer output OUT is in the output state of high driving capability of the logical value “1” (power supply potential). In addition, the data signal Dat
When a is a logical value "0", the first and third AND , Buffer OUT output is logical value "0" (ground potential)
The output state of the high drive capacity of is.

When the buffer state control signal Cont is the logical value "1", the drive capability control signal Drive is set.

At this time, when the data signal Data has the logical value "1", the first AND gate circuit It becomes the output state of the ability.

[0034] It becomes the output state of the dynamic ability.

[0035]

In the time-division transfer using the buffer circuit of the present invention, when the output drive is started from the high impedance state, the buffer circuit operates with high driving ability and the common signal line is switched to the potential of the output logical value in a short time. After that, the driving capability is lowered and the logical value potential of the common signal line is held. When the data transfer is completed, it enters the high impedance state.

At this time, even if the buffer circuit is not completely in the high impedance state, another chip can start output driving, and there is no need to provide an invalid high impedance time that is not involved in data transfer, effectively. The amount of data transfer can be increased and the number of terminals can be reduced, which is very effective for an integrated circuit.

Further, since the buffer circuit operates with a high driving ability when starting the output driving, the rise time of the output signal can be shortened and the speed can be increased.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining time division transfer.

FIG. 2 is a circuit connection diagram showing a conventional output buffer circuit.

FIG. 3 is a time chart for explaining time division transfer.

FIG. 4 is a circuit connection diagram showing an embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of the embodiment of the present invention.

[Explanation of symbols]

Chip A, Chip B, Chip C integrated circuit chip Buf A, Buf B, Buf C output buffer circuit PA, PB, PC terminal COM common signal line Cont A, Cont B, Cont C control signal Data A, Data B, Data C Output data I Inversion circuit Data Data signal Cont State control signal Drive Drive capacity control signal OUT Output signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7341-5K H04L 11/00 320

Claims (1)

[Claims] 1. A first transistor means having a relatively high driving capability for outputting an output signal to an output end according to a signal applied to a gate, and an output to the output end when the input signal is applied to the input end. The second transistor means that outputs a signal and has a relatively low driving capability, and at least the first transistor means are driven at the start of application of the input signal, and the first transistor means is cut off after a predetermined time and the first transistor means is shut off. And a logic control means for maintaining the conduction state of the second transistor means.