JPH0613547A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enlarge the surface area of a bottom electrode and form a capacitor element having a large capacitance without increasing the occupied area. CONSTITUTION:After forming a doped polysilicon on a silicon substrate 21 on which a field oxide film is formed, an anodization is performed in an aqueous solution consisting of mainly hydrofluoric acid, and a porous silicon 23a is formed. Next, a thermal treatment is performed at a temperature of 800 to 900 deg.C and the hole size is enlarged to several 10nm. Then, the porous silicon 23a is etched and a bottom electrode is formed. A capacitor insulating film made of CVD nitride film or thermal oxide film is formed. A top electrode made of doped polysilicon is formed. Therefore, the surface area can be enlarged due to the holes formed inside the bottom electrode and the charge storage amount can be increased to 10 to 100 times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a capacitor as its circuit element.

[0002]

2. Description of the Related Art Conventionally, a stacked capacitor included in a semiconductor device has been formed through the manufacturing steps shown in FIGS. 34 (a) to 36 (b). First, as shown in FIG. 34A, a silicon oxide film 2 for capacitor isolation is grown on a silicon substrate 1. A photoresist film 3 is applied on the silicon oxide film 2, and the photoresist film 3 is patterned.

The silicon oxide film 2 is dry-etched using the patterned photoresist film 3 as a mask,
A hole 2a as shown in FIG. 34 (b) is formed.

After removing the patterned photoresist film 2, polysilicon 4 is deposited as shown in FIG. Next, a photoresist is applied, and the photoresist film 5 is patterned by using the lithography technique and etching.

Using the patterned photoresist 5 as a mask, the polysilicon film 4 is etched, as shown in FIG.
The lower electrode 4a shown in (b) is formed.

The lower electrode 4a is covered with a dielectric film 6 (see FIG. 3).
6 (a)), and finally, as shown in FIG. 36 (b), a polysilicon film 7 is deposited on the dielectric film 6.

A stacked capacitor having such a structure is a dynamic random access memory device (hereinafter, simply referred to as DR).
It is widely used in integrated circuit devices.

However, in recent years, DRAMs have been highly integrated, the geometrical dimensions of elements have been miniaturized, and the area that each element, for example, a capacitor can occupy on a semiconductor substrate has been reduced.

In order to form a large-capacity capacitor in a reduced occupied area, its structure must be made three-dimensional, and up to now, a cylindrical stack electrode, a fin-type stack electrode, and a groove are required. Various bottom electrodes of the mold have been proposed.

FIGS. 37 (a) to 38 (b) show a manufacturing process of a cylindrical stack electrode. First, FIG.
As shown in (a), an interlayer insulating film 12 is grown on a silicon substrate 11, and silicon nitride 13 is deposited. The silicon nitride film 13 and the interlayer insulating film 12 are etched by using a patterned photoresist film (not shown) as a mask, and contact holes are formed to partially expose the silicon substrate.

A polysilicon film and a silicon oxide film are sequentially deposited, and the polysilicon film and the silicon oxide film are etched by using a patterned photoresist film (not shown) as a mask, and the polysilicon support 14 and the oxide film are oxidized. The silicon film 15 is formed. A polysilicon film 16 is deposited on the polysilicon support 14 and the silicon oxide film 15 to obtain the structure shown in FIG.

Next, the polysilicon film 16 is etched back by reactive ion etching without a mask, as shown in FIG.
As shown in (b), the lower electrode 16a is left on the sidewalls of the polysilicon support 14 and the silicon oxide film 15.

Next, the silicon oxide film 15 is etched with an aqueous solution of hydrofluoric acid to obtain the structure shown in FIG.

Finally, a capacitor insulating film 17 composed of a silicon nitride film and a silicon oxide film covers the lower electrode, and an upper electrode 18 of polysilicon is further deposited on the capacitor insulating film 17 to form the capacitor shown in FIG. The structure shown in b) is obtained.

However, as described above, in order to make the capacitor three-dimensional, complicated and accurate control is required, and it is difficult to obtain a capacitor structure with good reproducibility.

Therefore, the inventor of the present application filed Japanese Patent Application No. 3-272.
No. 165 (filed on Mar. 20, 1990) is a stacked capacitor electrode in which a hemispherical silicon grain is densely grown by the LP-CVD method, and a silicon film formed on the surface of the hemispherical silicon grain is processed. Proposed.
By forming unevenness of silicon on the surface, the effective surface area of the capacitor electrode is increased.

However, since the capacitor electrodes that have already been proposed have the stack capacitor electrodes individually separated by dry etching a silicon film composed of hemispherical silicon grains, the side walls of each stack electrode are smooth. However, there was a problem that the unevenness disappeared, and a sufficient increase in surface area could not be obtained.

Therefore, the inventor of the present invention has filed Japanese Patent Application No. 3-53933
No. (filed on February 26, 1991), a method of forming a new hemispherical grain was proposed. According to this method, amorphous silicon having a smooth surface is deposited, and this amorphous silicon film is processed into a desired shape by applying a lithography technique and an etching technique. Thereafter, the silicon oxide and carbon formed during the above processing on the surface of the amorphous silicon are removed, and heat treatment is performed in a vacuum or in a non-oxidizing atmosphere such as an inert gas. As a result, the surface of the amorphous silicon is crystallized and the surface of the silicon film becomes hemispherical grains. The electrodes formed by the proposed method are covered on their side faces with irregularities. This is because the irregularities are formed after separating the amorphous silicon film into individual stack electrodes.

[0019]

However, in the method of forming the stack electrode proposed in Japanese Patent Application No. Hei 3-53933 mentioned above, the amorphous silicon film must be cleaned before the unevenness is formed, and the subsequent heat treatment. Requires an inert and clean atmosphere from the viewpoint of preventing oxidation and contamination of amorphous silicon, and requires a large amount of equipment and precise control to maintain such an atmosphere. As a result, the stack electrode is formed over a long period of time, and there is a problem that the manufacturing efficiency is extremely low. Moreover, even if the unevenness is formed over such a long time, the surface area is at most about twice as large as the flat surface, and 4 Gbit DR which requires ultra-high integration is required.
It could not be applied to AM.

[0020]

The invention described in claim 1 of the present application relates to a semiconductor device including a constituent element of an electric circuit capable of improving electric characteristics by increasing a surface area. That is, it is made of polycrystalline silicon having a surface made of porous silicon.

The invention described in claim 2 of the present application relates to a semiconductor device in which an integrated circuit is formed, which includes a capacitive element having a first electrode and a second electrode facing the first electrode via a dielectric. The gist of the invention is that the first electrode is made of polycrystalline silicon in which at least a part of the surface facing the second electrode is porous silicon.

According to a third aspect of the present invention, a step of forming a lower electrode, a step of forming a dielectric covering the lower electrode, and an upper electrode facing the lower electrode through the dielectric are provided. And a step of forming the lower electrode, wherein the step of forming the lower electrode includes the step of forming the surface of the substrate with porous silicon, and the step of forming the dielectric includes forming the dielectric with the porous layer. Forming in contact with the surface defining the pores of the high quality silicon.

[0024]

The semiconductor device according to the present invention can increase the surface area of the constituent elements of the electric circuit or the surface area of the electrodes of the capacitive element. In fact, porous silicon can increase the surface area by several times to a dozen times, and can improve the electrical characteristics or the capacitance value.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process as a first embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 2 (b).

In the manufacturing process of the first embodiment, first, the field oxide film 2 is formed on the silicon substrate 21 by the LOCOS selective oxidation method.
2 is grown and then polysilicon is deposited by low pressure CVD. After the impurities have been introduced into the polysilicon, anodization is applied to the polysilicon. As a result, at least a part of the surface of the polysilicon becomes the porous silicon film 23a, and the structure shown in FIG. 1A is obtained.

In the anodization method, the polysilicon is used as an anode, and a platinum (Pt) cathode is made to face the polysilicon in an aqueous solution containing 5 to 40% of hydrofluoric acid as a main component. When a direct current of several to hundred milliamps / square centimeter is applied between the anode and the cathode, a large number of micropores are formed in the polysilicon, and the porous silicon film 23 is formed.
a. When visible light to ultraviolet light is irradiated during this porosification, hole carriers are generated and the reaction is accelerated.

The polysilicon is made porous even if it is selectively dry-etched using a mask made of resist.

As described above, the porous silicon film 23a formed by the anodization method has a large number of micropores of 2 to 10 nm, and the volume density of the porous silicon film is 20 to the bulk density. 80 percent. If the micropores are less than 2 nanometers, the capacitive insulating film and the upper electrode described later cannot be sufficiently deposited along the surface of the porous silicon film 23.

In order to enlarge the micropores, the porous silicon film 23a is heat treated at 800 to 900 degrees Celsius. Such heat treatment expands the micropores to about several tens of nanometers as shown in FIG. However, if oxygen is present during the heat treatment, the surface of the porous silicon film 23a is covered with an oxide film, and movement of silicon atoms is hindered. For this reason, the oxygen partial pressure during the heat treatment must be suppressed to 10 −6 Torr or less. The heat treatment is also effective in alleviating strain due to internal stress generated during anodization.

Next, a mask (not shown) is formed on the porous silicon film 23a with a resist, and the porous silicon film 23 is formed.
A is etched to become the lower electrode 23b.

Next, the lower electrode 23b is covered with the capacitive insulating film 24. First, a silicon nitride film is deposited to a thickness of 8 to 15 nanometers by the low pressure CVD method. This low pressure CVD uses a mixed gas of SiH ₂ Cl ₂ gas and NH ₃ gas at a pressure of 0.2.
Adjust to ~ 0.4 Torr and perform at 600-700 degrees Celsius. The reason why the deposition of silicon nitride is carried out at such a low temperature is that the film formation rate is set as a reaction rate-determining and the surface reaction is mainly made. As a result of such surface reaction, the inner walls of the micropores are well covered with silicon nitride. Next, the silicon nitride is oxidized in a steam atmosphere at 850 degrees Celsius for 10 minutes to grow silicon oxide. As a result, the lower electrode 23b is covered with the capacitive insulating film 24 composed of the SiO ₂ film and the Si ₃ N ₄ film.

Oxidation in the steam causes thick silicon oxide to grow on the porous silicon film not covered with silicon oxide, in the pinholes and on the weak spots. It is effective for sure electrical separation.

Next, a polysilicon film 25 is deposited on the entire surface by a low pressure CVD method, and the structure shown in FIG. 2A is obtained.

A resist mask (not shown) is formed on the polysilicon film 25 and is exposed.
5 is selectively removed by etching. As a result,
As shown in (b), the upper electrode 25a is formed.

The manufacturing process according to the second embodiment of the present invention will be described below with reference to FIGS. 3 (a) to 4 (b).

First, as shown in FIG.
A resist mask 32 is formed on the silicon substrate 31. The silicon substrate 31 is anodized, and the silicon substrate 31 exposed from the mask 32 is made porous toward the inside. As a result, the silicon substrate 31 becomes partly porous silicon.

Next, the mask 32 is removed, and the micropores of the porous silicon 33 are expanded by heat treatment as shown in FIG. 1B, as in the first embodiment. As a result, the capacitive insulating film easily adheres to the inner walls of the micro holes.

A silicon nitride film is deposited by a low pressure CVD method so as to be in close contact with the inner walls of the micropores, and a silicon oxide film is grown by steam oxidation. As a result, the SiO ₂ film and S
The capacitive insulating film 34 made of the i ₃ N ₄ film is formed as shown in FIG.

A polysilicon film is grown on the capacitor insulating film 34 by the low pressure CVD method, and impurities are introduced into the polysilicon. A resist mask (not shown) is formed on the polysilicon, and the polysilicon film becomes the upper electrode 35 by etching as shown in FIG. 4B.

In the second embodiment, since the lower electrode is formed in the silicon substrate 31, unevenness is reduced on the main surface of the silicon substrate 31, and the wiring area formed on the main surface of the silicon substrate 31 can be easily flattened. It has the advantage that

In addition to the capacitive elements manufactured in the steps of the first and second embodiments described above, the capacitive elements having the structures shown in FIGS. 5 (a) to 6 (c) characterize the present invention. It is composed of high quality silicon. FIG. 5A shows a simple columnar lower electrode 41, the surface of which is covered with porous silicon 41 a to increase the surface area of the lower electrode 41. FIG. 5B shows a cylindrical lower electrode 42, the outer surface and inner surface of which are covered with porous silicon 42a. FIG. 6 (a) shows a fin-shaped lower electrode 43a, and the lower electrode 43 is covered with porous silicon 43a in both the column portion and the fin portion. Next, FIG.
(B) is the lower electrode 44 of the stacked trench capacitor
And the surface of the lower electrode 44 is porous silicon 4
It is covered with 4a. Further, FIG. 6C shows the lower electrode 45 of the trench capacitor.
Is also covered with porous silicon 45a. Therefore,
The present invention can be applied regardless of the shape of the electrode.

The manufacturing method according to the third embodiment of the present invention will be described below with reference to FIGS. 7 (a) to 9 (b).

According to the manufacturing method of the third embodiment, first, the silicon oxide film 52 for element isolation is grown on the silicon substrate 51, and this silicon oxide film 52 is formed as shown in FIG.
A mask 5 in which a resist is patterned as shown in FIG.
It is exposed selectively in 3.

Contact holes 52a are formed in the silicon oxide film 52 by dry etching, and the structure shown in FIG. 7B is obtained.

Subsequently, the polysilicon film 54a has a temperature of 60 degrees Celsius.
It is deposited by a low pressure CVD (LPCVD) method at 0 ° C., and phosphorus is contained in the polysilicon film 54a from POCl ₃ gas at 800 ° C.
It is introduced for 30 minutes. A resist mask 55 is formed on the polysilicon film 54a, and the structure shown in FIG. 8A is obtained.

The exposed portion of the polysilicon film 54a is removed by reactive ion etching to form a lower electrode 54b as shown in FIG. 8 (b). FIG. 10 is a scanning electron micrograph showing the surface shape of the lower electrode 54b at this time, and the magnification is 60,000 times.

Next, as shown in FIG. 9A, the surface of the lower electrode 54b is made porous to form a porous silicon film 56. In this embodiment, the lower electrode 54b is immersed in a heated phosphoric acid solution (H ₃ PO ₄ ) to make its surface porous.

To explain in more detail the above-mentioned porosification step, the phosphoric acid solution is heated to 140 ° C., and the lower electrode 54b is immersed in this heated phosphoric acid solution for 90 minutes. The heated phosphoric acid selectively etches the impurities segregated on the grain boundaries and transition planes of the polysilicon, and opens a large number of micropores on the surface of the polysilicon. FIG. 11 is a scanning electron micrograph showing the surface shape of the lower electrode 54b after the treatment with the phosphoric acid solution.
The magnification is 60,000 times. 12A to 12C are scanning electron micrographs of the lower electrode 54b taken at different magnifications, which are taken at 100,000 times, 200,000 times, and 450,000 times, respectively. These scanning electron micrographs show that polysilicon is made porous and a large number of micropores of several nanometers to tens of nanometers are formed on the surface thereof.

As described above, since the heated phosphoric acid solution selectively etches the segregated impurities, the polysilicon into which the impurities are not introduced is not made porous. FIG.
(A) to (c) are scanning electron microscope images of the surface shapes of polysilicon containing no impurities when immersed in a phosphoric acid solution for 10 minutes, 30 minutes, and 90 minutes, respectively. I haven't.

FIGS. 14 (a) to 14 (c) show that POCl ₃ gas was used as a diffusion source and phosphorus was thermally diffused for 30 minutes at 800 ° C. in H ₃ PO ₄ at 140 ° C. for 10 minutes, 30 minutes.
2 is a scanning electron microscope photograph of the surface shape after dipping for 90 minutes and 90 minutes respectively, and etching progresses from the surface to a transition surface with a high phosphorus concentration, stacking faults, and grain boundaries, and the polysilicon film is roughened. Represents the state of becoming porous. The size and morphology of the porous structure thus obtained can be controlled by the film formation conditions of the polysilicon film, the method of adding impurities, the subsequent heat treatment conditions, the concentration of the H ₃ PO ₄ solution, the temperature, and the time, It can be reproduced stably. Although an aqueous solution of phosphoric acid is used in this embodiment, the aqueous solution of phosphoric acid may be heated to form vapor and sprayed on the surface of the polysilicon film.

When the phosphoric acid is used to make the polysilicon porous, the thickness of the porous layer can be adjusted by controlling the treatment time with the phosphoric acid aqueous solution. However, in order to accurately control the thickness of the porous layer, an extremely thin silicon oxide film is intervened in the polysilicon film in advance, and this silicon oxide film is used as an etching stopper for controlling the film thickness. . Although this polysilicon film is composed of a plurality of layers, silicon oxide must be interposed so as not to impair the function of the electrode.

For example, while depositing polysilicon to a total thickness of 300 nanometers, two layers of a silicon oxide film of about 2 nanometers are interposed, and phosphorus is added to the polysilicon for 30 minutes in POCl ₃ gas at 800 ° C. After thermal diffusion and subsequent immersion in a phosphoric acid solution at 140 degrees Celsius for 60 minutes, FIG.
As can be seen from the scanning electron micrograph of the above, only the uppermost polysilicon layer was made porous, and the first silicon oxide film stopped the etching. In the polysilicon layer composed of such a plurality of polysilicon films, crystal grains can be divided in the film thickness direction, and the grain size can be controlled. As described above, the etching proceeds along the grain boundaries, so that if the polysilicon layer is composed of a plurality of films, it contributes to an increase in the area of the side wall.

After forming the lower electrode 54b of porous silicon as described above, the dielectric film 56 is formed on the lower electrode 54b.
It is formed so as to contact the surface of b. As the dielectric film 56, a multi-layer structure composed of silicon nitride having a thickness of 5 to 10 nanometers deposited by a low pressure CVD method and silicon oxide obtained by oxidizing the surface of this silicon nitride is used. Also, a high dielectric film such as Ta ₂ O ₅ or a ferroelectric film can be used.

Thereafter, a phosphorus-added polysilicon film is formed so as to be in close contact with the dielectric film 56, and processed into the upper electrode 57 by the lithography technique and reactive ion etching. FIG. 9B shows this stage.

In the third embodiment, the polysilicon is processed into the shape of the lower electrode 54b and then made porous. However, after the polysilicon is made porous, the lower electrode 54b is made.
It may be processed into. Further, the upper electrode 57 is not limited to polysilicon and may be another semiconductor or metal.

In the manufacturing method of the fourth embodiment according to the present invention, impurities are introduced by ion implantation into silicon before being made porous. When phosphorus is used as an impurity for implantation, the acceleration energy is 70 eV and the dose is 1 × 10 ¹⁶ cm ^−2.
And Then, the silicon film is annealed in a nitrogen atmosphere at 900 degrees Celsius for 30 minutes and made porous in a phosphoric acid solution at 140 degrees Celsius. 16A to 16C are scanning electron micrographs when the treatment time in the phosphoric acid solution was 10, 20, and 60 minutes, and fine irregularities of about 5 nm were observed in the silicon particles. To be done.

In the fourth embodiment, phosphorus is used as the impurity implanted into the silicon film, but the impurity need not be phosphorus as long as it is segregated at the grain boundaries and transition planes. Boron, arsenic or antimony may be used.

In the manufacturing method according to the fifth embodiment of the present invention, impurities are introduced into the silicon film during film formation. For example, the gas containing SiH ₄ and PH ₃ is adjusted to 0.6 Torr and 630 ° C. by the low pressure CVD method, and the polysilicon formed in such an atmosphere is made porous in a phosphoric acid solution at 140 ° C. It

In the manufacturing process of the fifth embodiment, the temperature is set to 550 degrees Celsius.
Degree, the silicon film becomes amorphous. When this amorphous silicon is annealed in a high temperature atmosphere of 900 degrees Celsius for 30 minutes, it is crystallized and relatively large crystal grains grow. When this silicon film is treated in a phosphoric acid solution, a high concentration portion where phosphorus is segregated is selectively etched, and a porous structure composed of relatively large pores reflecting the grain size is obtained. FIG. 17
Is a scanning electron microscope photograph taken by immersing a sample having a film thickness of 400 nm in the phosphoric acid solution for 90 minutes by the above method.

The manufacturing method according to the sixth embodiment of the present invention uses an aqueous NH ₃ solution for porosification. In addition to this, any etching agent having a different etching rate due to the difference in impurity concentration can be used. The manufacturing method according to the sixth embodiment uses an NH ₃ aqueous solution at 60 degrees Celsius, and the silicon film is etched at a rate of 5 nanometers per minute. On the surface of the silicon film after etching, minute concaves and convexes of about 5 nm and deep concaves along the grain boundaries are observed. FIG. 18 shows the surface of the silicon film formed by the manufacturing method of the sixth embodiment, which is photographed by a scanning electron microscope. This sample turned black due to fine irregularities on the surface. In addition to the NH ₃ aqueous solution, this may be heated to generate NH ₃ vapor for etching.

As an etchant having a different etching rate depending on the difference in impurity concentration, there are a solution containing HF and HNO ₃ and a solution containing HF and H ₂ O ₂ . The impurities introduced into silicon may be phosphorus, arsenic, boron or antimony, and the method of introducing them is not limited.

The manufacturing method according to the seventh embodiment of the present invention is
The purpose is to increase the area of the side surface of the silicon electrode. That is, when the silicon film is made porous, H ₃ PO _{4 is used.}
The area of the side surface of the electrode is less increased than that of the upper surface of the electrode regardless of whether it is used or NH ₃ . This is because, when the polycrystalline silicon film is formed by a normal low pressure CVD method, it has a columnar structure and therefore the density of grain boundaries appearing on the electrode surface is different. In order to solve this, there is a method of dividing the silicon film into a plurality of layers as described above, but it can also be solved by the method described below.

First, as shown in FIG. 19A, a silicon oxide film 62 is formed on a silicon substrate 61, a resist 63 is applied on the silicon oxide film 62 for patterning, and the silicon oxide film 62 is etched by dry etching. (Fig. 19
(B)).

Thereafter, as shown in FIG. 20A, a polysilicon film 64 is deposited and impurities such as phosphorus and arsenic are added. The polysilicon film 64 was deposited by the low pressure CVD method. The deposition conditions are a temperature of 600 ° C., a mixed gas of SiH ₄ and He used gas (SiH ₄ : 20%, He: 80%), pressure 1T.
orr.

A resist 65 is applied on the polysilicon 64 and patterned (FIG. 20A), and the polysilicon film 64 is dry-etched using this as a mask (FIG. 20B).

After removing the resist 65, a polysilicon film 68 was deposited in a thickness of 150 nanometers by a low pressure CVD method (FIG. 21A). The deposition conditions are the same as for the polysilicon film 64.

Then, the polysilicon film 68 is formed at 800.degree.
Thermal diffusion of phosphorus was performed using POCl ₃ gas for 30 minutes. After that, etching back is performed by reactive ion etching to form an electrode. (FIG.21 (b)).

After that, cleaning is performed with a mixed solution of hydrochloric acid and hydrogen peroxide. The electrode thus formed was immersed in an aqueous solution of H ₃ PO ₄ heated to 140 ° C. for 60 minutes. By this process,
A porous silicon layer 69 is formed on the electrode surface. (Fig. 2
2 (a)).

Thereafter, a dielectric film 66 and an upper electrode (lind polysilicon) 67 are formed (FIG. 22).
(B)).

The surface area increase rate of the capacitor thus formed is about twice as large as that of the silicon film deposited at 600 ° C. Further, the leak current characteristic of this capacitor is almost the same as that of the capacitor in which the porous silicon layer is not formed (see FIGS. 26 and 27), and the breakdown voltage distribution is also good (FIG. 28).

The manufacturing method according to the eighth embodiment of the present invention is
Even when the silicon electrode is exposed to a gas containing halogen, it becomes porous. That is, the polysilicon film is formed into 200 nm.
30 min POCl at 800 ° C after torr deposition
Thermal diffusion of phosphorus was performed using ₃ gases. After this 1To
In a chamfer filled with Cl ₂ gas of rr, etching is performed for 5 minutes with chlorine radicals generated by irradiation with ultraviolet light generated by a low pressure mercury lamp. When this method is used, the etching rate of the portion where phosphorus is segregated at a high concentration such as the grain boundary and the transition surface is 50 to 100 times that of the portion where phosphorus is not segregated. A porous layer and fine irregularities are formed. FIG. 23 shows the result of observation of the surface portion with a scanning electron microscope.

In this embodiment, the formation of the porous layer and the fine irregularities on the surface are formed by using chlorine radicals.
It can also be carried out with r (bromine) or I (iodine) radicals.
Further, although ultraviolet light from a low-pressure mercury lamp is used to generate radicals, photoexcitation using another method may be used,
Even if plasma is generated using microwaves, high frequencies, or an electron gun, radicals can be generated and can be implemented.

The manufacturing method according to the ninth embodiment of the present invention is
The formation of the stack electrode and the porosification are performed at the same time. That is, after depositing a polysilicon film at 200 nanometers, thermal diffusion of phosphorus was performed using POCl ₃ gas at 800 ° C. for 30 minutes. Subsequently, a resist pattern of a stacked capacitor is formed by using a lithography technique. Thereafter, the parallel plate reactive ion etching apparatus is used to etch the polysilicon with Cl ₂ at a pressure of 20 Pa (0.15 Torr). As a result,
The part without the resist mask is anisotropically etched because it is irradiated with chlorine ions, but the part where the phosphorus is segregated at a high density, such as the grain boundary and the transition surface in the polysilicon under the resist pattern, is present. It is selectively etched by chlorine radicals. Therefore, the etching shape becomes anisotropic, while the porous layer isotropically occurs. FIG. 24 shows a photograph of an etched cross section observed with a scanning electron microscope.

By using this method, it is possible to simultaneously form the stack electrode and make it porous. In this embodiment, a parallel plate reactive ion etching (RIE) apparatus is used for etching polysilicon, but ECR, magnetron RIE, or helicon etching apparatus can also be used. Further, in the embodiment, the etching gas is C
Although I ₂ is used, F (fluorine), Br (bromine), I (iodine) and the like can be used.

The manufacturing method according to the tenth embodiment of the present invention is anodization in an aqueous solution of hydrogen fluoride to make it porous. That is, to form porous silicon on the lower electrode, the silicon electrode can be anodized in an aqueous solution containing hydrogen fluoride as a main component. Hereinafter, this example will be described in the order of steps.

A silicon oxide film for element isolation is formed on a silicon substrate 71, and then, in order to protect the silicon oxide film 72 from hydrofluoric acid, the silicon nitride film 73 is subjected to low pressure CVD.
It is formed by the method. Thereafter, in order to make contact with the silicon substrate 71, patterning is performed by the lithography technique and the etching technique. (Fig. 30 (a),
(B)).

Then, SiH ₄ and PH _{3 are formed} by the low pressure CVD method.
An amorphous silicon film is formed from a gas system containing P at a pressure of 0.6 Torr and a temperature of 550 ° C., and is annealed at 800 ° C. for 120 minutes to be crystallized to form a polysilicon film 74a, followed by lithography. -The resist 65 is formed by the technique and patterned by the etching technique to form the lower electrode 64b (FIGS. 31A and 31B).

Using the formed lower electrode 64b as an anode, 5
-40% Pt in an aqueous solution containing HF (hydrofluoric acid) as a main component
(Platinum) is used as a counter electrode, and a direct current of several hundred mA / cm ² is applied to form micropores. At this time, in order to accelerate the reaction, the carrier may be excited by irradiation with visible-ultraviolet rays. The size of the micropores is 2 to several tens of nanometers, and the volume density of the porous layer is controlled to 20-80% of the bulk density. In this method, the side wall of the lower electrode 64b also covers the porous film 79.
It is characterized by being covered with. (FIG. 32 (a)).

At this time, when the size of the formed micropores is several nanometers or less, the dielectric film is not sufficiently covered up to the inside of the pores, which may cause a short circuit or open pores. Is completely filled up, the surface area of the upper electrode does not increase, and it becomes difficult to effectively increase the accumulated charge amount. In order to prevent this, the hole is enlarged by the method already described (FIG. 32 (b)).

Next, a dielectric film 76 is formed (see FIG. 33).
(A)), and impurity-added polysilicon is further deposited as the upper electrode 77 (FIG. 33 (b)).

Although the dielectric film is formed while leaving the silicon nitride film in this embodiment, the dielectric film may be formed after removing the silicon nitride film with the H ₃ PO ₄ solution. .

When the manufacturing method of the ninth embodiment described above is used, the accumulated charge amount can reach up to ten times that of the conventional one. The phenomenon itself that silicon becomes porous by anodization has been known for a long time, and since porous silicon formed by this method is very reactive, formation of element isolation silicon oxide film at low temperature, SOI (Siric
It is used for forming an on-on-insulator structure, forming a silicide for wiring, and the like. Recently, a visible light emission phenomenon, which was hitherto impossible with indirect transition type silicon, has been confirmed, and its application to a light emitting device has been studied. In the method for manufacturing a semiconductor device of the present invention, anodization is applied as a method of forming a porous layer on the surface of a lower electrode, and an effect unique to the present invention of increasing the accumulated charge capacity is obtained.

In the manufacturing method according to the eleventh embodiment of the present invention, when the dielectric film is formed on the surface of the porous layer of the lower electrode,
If the size of the pores (recesses) of the porous layer is less than ten nanometers, the dielectric film may not be able to sufficiently cover the inner surface of the pores or may completely fill the pores. In view of this, the surface area of the upper electrode is increased to increase the storage capacity.

Therefore, if necessary, a step of expanding the size of the hole is added before forming the dielectric film. For example, after forming the porous silicon, the surface of the porous silicon is 700 ° C.,
20-30 nm in a reduced pressure oxygen atmosphere of 1 Torr
After the tolu-oxidation, the formed silicon oxide film is removed with hydrofluoric acid or the like, whereby the hole can be widened.

Alternatively, the silicon oxide film formed on the surface may be removed by performing oxidation for a short time by the rapid thermal oxidation method.

Further, if it is desired to widen the pores with an order of 1-2 nanometers, H ₂ O ₂ (hydrogen peroxide) or HN is used.
This can be carried out by repeating a step of immersing the silicon oxide film in an aqueous solution containing O ₃ (nitric acid) to form a silicon oxide film and removing the silicon oxide film with hydrofluoric acid or the like any number of times.

In the manufacturing method according to the twelfth embodiment of the present invention, the surface of porous silicon is thermally nitrided, and then the silicon nitride film formed on the surface of the porous silicon is removed to expand the pores.

For example, after forming porous silicon, NH
A rapid thermal nitridation at 800 ° C. for 60 seconds in a ₃ (ammonia) atmosphere forms a 1.5-2 nanometer silicon nitride film on the surface of the porous silicon. This can be carried out by repeating the steps of etching and removing with a solution containing H ₃ PO ₄ etc. any number of times.

The manufacturing method according to the thirteenth embodiment of the present invention is the same as that of the tenth embodiment when the width of the silicon-containing portion of the porous silicon is only a few nanometers. In the method of the eleventh embodiment, the entire porous layer may be instantly changed to a silicon oxide film or a silicon nitride film, and in order for the porous layer to function as an electrode, a portion where silicon exists is used. In view of the fact that the width must be thicker than twice the width of the depletion layer, the porous silicon is annealed in a high vacuum, in a non-oxidizing atmosphere, or in a reducing atmosphere to recrystallize the porous silicon. And change to a larger porous structure.

For example, when porous silicon having a structure of several nanometers is heat-treated at 1000 ° C. for 5 minutes in an H ₂ (hydrogen) atmosphere, recrystallization occurs, and porous silicon having a structure of several nanometers is obtained. Change to silicon. This phenomenon itself has been known for a long time. Elect
rochem. Soc. : SOLID-STATESC
IENCE AND TECHNOLOGY Augu
st 1978 Vol. 125, No. 8 P13
39 "Structure of PorousSi
licon Layer and Heat-Trea
“ment effect Effect” Takashi Un
Learn more about agami and MasahiroSeki.

The manufacturing method according to the fourteenth embodiment of the present invention is carried out in combination with the method of forming the hemispherical grain of silicon on the surface of the lower electrode described in the prior art.

For example, the growth temperature is set to 5 by using the low pressure CVD method.
After depositing an amorphous silicon film of 200 nanometers at 00 ° C., a lower electrode shape is formed by using a lithography technique and a dry etching technique. After that, Japanese Patent Application 3-5
Hemispherical silicon grains proposed in No. 3933 (filed on February 26, 1991) are formed on the surface of the lower electrode by annealing in a high vacuum at a substrate temperature of 750 ° C.

Subsequently, PO at 800 ° C. for 30 minutes
Thermal diffusion of phosphorus was performed using Cl ₃ gas. After this,
It was immersed in a H ₃ PO ₄ solution heated to 140 ° C. for 60 minutes.
By performing this treatment, finer irregularities than the porous silicon layer and the hemispherical silicon grains are formed on the electrode surface.

After that, a capacitor insulating film and an upper electrode are formed to form a capacitor. The accumulated charge capacity of this capacitor is about twice as large as that of a capacitor in which hemispherical silicon gray is formed on the lower electrode and about four times as much as that of a normal capacitor to which a hemispherical capacitor is not applied (FIG. 25).

In this embodiment, after the hemispherical grain silicon is formed on the amorphous silicon electrode, the electrode introduced with impurities by phosphorus diffusion is made porous. However, the phosphorus introduction method is not limited to the thermal diffusion method, and the ion diffusion method is not limited to the ion diffusion method. It can be carried out by using the water injection method, by introducing phosphorus, or by using phosphorus-doped amorphous silicon in which phosphorus is introduced during the growth of amorphous silicon. The porous silicon layer is formed by immersing it in a heated H ₃ PO ₄ solution, but the method is not limited to this method as long as the porous silicon layer and fine irregularities are formed on the electrode surface. Further, although phosphorus is used as an impurity, it can be carried out with an impurity such as As (or the like). As described above, by combining the hemispherical silicon gray and the porous silicon, a remarkable effect can be obtained in increasing the accumulated charge capacity.

The manufacturing method according to the fifteenth embodiment of the present invention is carried out even when amorphous silicon doped with a high concentration of H ₃ PO ₄ solution is treated when porous silicon is formed on the lower electrode. .

For example, using the low pressure CVD method, in-si
A tu Lind amorphous silicon film is deposited at 200 nanometers. In this phosphorus-doped amorphous silicon film, phosphorus is introduced in a supersaturated state (1 × 10 ²¹ cm ⁻³ ). Subsequently, the lower electrode shape is formed by using the lithography technique and the dry etching technique. Then, it was immersed in a H ₃ PO ₄ solution heated to 140 ° C. for 60 minutes. By performing this treatment, a porous silicon layer and fine surface irregularities are formed on the electrode surface (FIG. 29).

Then, a capacitor insulating film and an upper electrode are formed to form a capacitor. The stored charge capacity of this capacitor is about twice as large as that of a capacitor in which a lower electrode is made of Lind-doped amorphous silicon. In this embodiment,
Although the in-situ rind amorphous silicon electrode using the low pressure CVD method is made porous, it can be carried out even if phosphorus is not doped. Further, although amorphous silicon is formed by using the low pressure CVD method, amorphous silicon can be formed by implanting silicon into the phosphorus-diffused polysilicon by using the ion implantation method. .
The porous silicon layer is formed by immersing it in a heated H ₃ PO ₄ solution, but the method is not limited to this method as long as the porous layer and fine irregularities are formed on the electrode surface.

The manufacturing method according to the sixteenth embodiment of the present invention is carried out by depositing amorphous silicon by sputtering when forming porous silicon on the lower electrode.

For example, the Ar (argon) pressure during sputtering is 6 × 10 ^-2 Torr, the substrate temperature is 100 ° C., and the thickness is 300.
The silicon film deposited on the nanometer has a columnar porous structure due to the bevel effect, and voids exist between the columns. Then, phosphorus is thermally diffused using POCl ₃ gas at 800 ° C. for 20 minutes, crystallization is performed, and then the silicon oxide film formed by thermal diffusion of phosphorus is removed by hydrofluoric acid to form a porous film. A bottom electrode having a layer can be formed.

Alternatively, silicon containing impurities such as phosphorus or boron may be used as a sputtering target to deposit porous amorphous silicon and then crystallize by annealing.

Further, it is also possible to perform reactive sputtering of silicon on the target in an atmosphere containing a source gas of impurities such as PH ₃ or B ₂ H ₆ and then crystallize by annealing. .

Regarding amorphous silicon by the sputtering method, Kiyoshi Takahashi, Makoto Konagai, Latest Amorphous Si Handbook, Science Forum, Masakuni Suzuki, (198
Detailed in 3).

In the seventeenth embodiment of the present invention, when the porous silicon is formed on the lower electrode, a fine mask of 100 nanometers or less is self-deposited on the silicon film without using the lithography technique. It is formed systematically and anisotropically etched.

For example, polysilicon containing impurities is added to
00 nanometer deposition followed by Ar (argon) and O ₂
Sputtering is performed using silicon oxide as a target in an atmosphere containing (oxygen). The pressure during sputtering is 6 × 10 ^-2 T
orr

The silicon oxide thus deposited on the silicon film to a thickness of 50 nanometers has a width of several tens nanometers.
It has a porous structure on the pillar of the tor. This is treated with dilute hydrofluoric acid of several% to widen the hole to about 20 nanometers, and then polysilicon is etched in a gas containing Cl ₂ at a pressure of 20 Pa using a parallel plate RIE apparatus.

As a result, the portions without silicon oxide are anisotropically etched because they are irradiated with chlorine ions, but the polysilicon under the pillars of silicon oxide is not etched, so that the surface of the polysilicon has a width of several tens. A nanometer columnar porous silicon layer is formed. In addition, an island-shaped or mesh-shaped mask can be formed by changing the sputtering conditions and time, and anisotropic etching can be performed using this mask. Further, the mask material is not limited to silicon oxide, and may be any material as long as it has a sufficient selection ratio in anisotropic etching.

In this embodiment, a parallel plate RIE device is used for etching polysilicon, but ECR, magnetron RIE, or helicon etching device may be used. Furthermore, although Cl ₂ is used as the etching gas in the examples, F (fluorine), Br (bromine), I (iodine) or the like can be used.

Further, not only the sputtering method but also a film forming method such as a CVD method or a vapor deposition method may be used.

[0111]

As described above, according to the present invention, the surface area of an electrode made of porous silicon is 10 to 100 times that of a flat electrode made of polysilicon or the like. The electrical characteristics of the constituent elements of the electric circuit, for example, the charge storage amount of the capacitor can be dramatically increased. As a result, the degree of integration of the semiconductor integrated circuit is significantly improved even when the same semiconductor substrate as that of the conventional example is used, and a sufficient charge storage amount causes a hold failure.
Prevent soft errors. To do. Further, the electrode made porous according to the present invention can increase the accumulated charge capacity to the same extent as the conventional cylindrical stack capacitance electrode, stack trench capacitance electrode, or capacitance electrode using HSG-Si. For example, in the case of the embodiment in which the phosphoric acid aqueous solution is used for the porosity treatment, the charge storage capacity 1.6 times that of the standard stack electrode can be obtained by adding only one step. If it is attempted to realize the same level of charge storage capacity with a cylindrical stack electrode, seven or more steps are required, which makes the manufacturing method extremely complicated. Further, the capacitive element according to the present invention has a macroscopically smooth surface shape, and even if a wiring or the like is laid above the capacitive element, there is little risk of disconnection or the like.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing another step of the manufacturing method according to the first embodiment.

FIG. 3 is a cross-sectional view showing the manufacturing method according to the second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing another step of the manufacturing method according to the second embodiment.

FIG. 5 is a cross-sectional view showing electrode structures of various capacitive elements to which the present invention is applied.

FIG. 6 is a cross-sectional view showing electrode structures of various capacitive elements to which the present invention is applied.

FIG. 7 is a cross-sectional view showing an initial stage of the manufacturing method according to the third embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the middle stage of the manufacturing method according to the third embodiment of the present invention.

FIG. 9 is a sectional view showing a latter stage of the manufacturing method according to the third embodiment of the present invention.

FIG. 10 is a scanning electron micrograph showing the surface texture of the lower electrode formed by the manufacturing method of the third embodiment of the present invention before it is made porous.

FIG. 11 is a scanning electron micrograph showing the surface texture of the lower electrode formed by the manufacturing method of the third embodiment of the present invention after the lower electrode is made porous.

FIG. 12 is a scanning electron showing the surface texture of the lower electrode formed by the manufacturing method according to the third embodiment of the present invention after being made porous at different magnifications (100,000 times, 200,000 times, 450,000 times). It is a micrograph.

FIG. 13 shows different surface treatment times (10 minutes, 3 minutes) for the surface texture of the unintroduced polysilicon after phosphoric acid treatment.
It is a scanning electron microscope photograph taken every 0 minutes, 90 minutes).

FIG. 14 shows different surface treatment times (10 minutes, 30 minutes, 9 minutes) for the surface texture after the impurity-doped polysilicon is treated with phosphoric acid.
It is a scanning electron micrograph taken every 0 minutes.

FIG. 15 is a scanning electron micrograph showing a cross-sectional structure of a lower electrode formed in a modification of the third embodiment of the present invention after the lower electrode is made porous.

FIG. 16 shows different times (10 minutes, 20 minutes,) during phosphoric acid treatment of the lower electrode formed by the manufacturing method of the fourth embodiment of the present invention.
It is a scanning electron micrograph showing the surface texture every 60 minutes.

FIG. 17 is a scanning electron micrograph showing the surface texture of the lower electrode formed by the manufacturing method of the fifth embodiment of the present invention after making it porous.

FIG. 18 is a scanning electron micrograph showing the surface texture of the lower electrode formed by the manufacturing method according to the sixth embodiment of the present invention after the lower electrode is made porous.

FIG. 19 is a sectional view showing an initial stage of the manufacturing method according to the seventh embodiment of the present invention.

FIG. 20 is a first manufacturing method according to a seventh embodiment of the present invention.
It is sectional drawing which shows a middle stage.

FIG. 21 is a second manufacturing method according to the seventh embodiment of the present invention.
It is sectional drawing which shows a middle stage.

FIG. 22 is a sectional view showing a latter stage of the manufacturing method according to the seventh embodiment of the present invention.

FIG. 23 is a scanning electron micrograph showing the surface texture of the lower electrode formed by the manufacturing method of the eighth embodiment of the present invention after making it porous.

FIG. 24 is a scanning electron micrograph showing the surface texture of the lower electrode formed by the manufacturing method of the ninth embodiment of the present invention after making it porous.

FIG. 25 is a graph showing capacitance values when the surface of the stack electrode is made of various crystals.

FIG. 26 is a graph showing current characteristics of a capacitor in which the surface of an electrode is made of porous silicon.

FIG. 27 is a graph showing current characteristics of a capacitor in which an electrode surface is made of polysilicon.

FIG. 28 is a graph showing breakdown voltage distribution characteristics.

FIG. 29 is a scanning electron micrograph showing the surface texture of the lower electrode formed by the manufacturing method according to the fifteenth embodiment of the present invention after making it porous.

FIG. 30 is a sectional view showing an initial stage of the manufacturing method according to the tenth embodiment of the present invention.

FIG. 31 is a sectional view showing a first middle stage of the manufacturing method according to the tenth embodiment of the present invention.

FIG. 32 is a sectional view showing a second middle stage of the manufacturing method according to the tenth embodiment of the present invention.

FIG. 33 is a sectional view showing a latter stage of the manufacturing method according to the tenth embodiment of the present invention.

FIG. 34 is a cross-sectional view showing the initial stage of the manufacturing method according to the conventional example.

FIG. 35 is a cross-sectional view showing the middle stage of the manufacturing method according to the conventional example.

FIG. 36 is a sectional view showing a latter stage of the manufacturing method according to the conventional example.

FIG. 37 is a sectional view showing a manufacturing method according to another conventional example.

FIG. 38 is a cross-sectional view showing another step of the manufacturing method according to another conventional example.

[Explanation of symbols]

21, 31, 51, 61 Silicon substrate 23a, 41a, 42a, 43a, 44a, 45a, 6
9,79 Porous silicon 23b, 41, 42, 43, 44, 45, 54b, 6
4, 74b lower electrode 24, 34, 58, 66,
76 Dielectric 25a, 35, 57, 67, 77 Upper electrode

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 8, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

FIG. 10 is a grain structure of the surface texture before the lower electrode is made porous by the manufacturing method of the third embodiment of the present invention.
It is a scanning electron micrograph showing the structure .

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 11

[Correction method] Change

[Correction content]

FIG. 11 is a grain structure of the surface texture of the lower electrode formed by the manufacturing method of the third embodiment of the present invention after the lower electrode is made porous.
It is a scanning electron micrograph showing the structure .

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 12

[Correction method] Change

[Correction content]

FIG. 12 is a grain structure of the surface texture after the lower electrode is made porous by the manufacturing method of the third embodiment of the present invention.
It is a scanning electron micrograph showing the structure at different magnifications (100,000, 200,000, and 450,000 times).

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 13

[Correction method] Change

[Correction content]

FIG. 13 is a scanning electron microscope photograph taken at different treatment times (10 minutes, 30 minutes, 90 minutes) of the grain structure of the surface texture of the unintroduced polysilicon after phosphoric acid treatment.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 14

[Correction method] Change

[Correction content]

FIG. 14 shows that the grain structure of the surface texture of the impurity-doped polysilicon after phosphoric acid treatment is different for different treatment times (10
Min, 30 min, 90 min) is a scanning electron micrograph.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] Figure 15

[Correction method] Change

[Correction content]

FIG. 15 is a scanning electron micrograph showing a particle structure of a cross-sectional structure of a lower electrode formed in a modification of the third embodiment of the present invention after the lower electrode is made porous.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] Fig. 16

[Correction method] Change

[Correction content]

FIG. 16 shows different times (10 minutes, 20 minutes) during the phosphoric acid treatment of the lower electrode formed by the manufacturing method according to the fourth embodiment of the present invention.
Is a scanning electron micrograph showing the particle structure of the surface texture every 60 minutes).

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 17

[Correction method] Change

[Correction content]

FIG. 17 is a grain structure of the surface texture of the lower electrode formed by the manufacturing method according to the fifth embodiment of the present invention after the lower electrode is made porous.
It is a scanning electron micrograph showing the structure .

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 18

[Correction method] Change

[Correction content]

FIG. 18 is a grain structure of the surface texture after the lower electrode is made porous by the manufacturing method of the sixth embodiment of the present invention.
It is a scanning electron micrograph showing the structure .

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] Fig. 23

[Correction method] Change

[Correction content]

FIG. 23 is a grain structure of the surface texture of the lower electrode formed by the manufacturing method according to the eighth embodiment of the present invention after the lower electrode is made porous.
It is a scanning electron micrograph showing the structure .

[Procedure Amendment 11]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 24

[Correction method] Change

[Correction content]

FIG. 24 is a grain structure of the surface texture after the lower electrode is made porous by the manufacturing method of the ninth embodiment of the present invention.
It is a scanning electron micrograph showing the structure .

[Procedure Amendment 12]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 29

[Correction method] Change

[Correction content]

FIG. 29 is a particle of the surface texture after the lower electrode is made porous by the manufacturing method of the fifteenth embodiment of the present invention.
It is a scanning electron micrograph showing a structure .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masanobu Yoshiya 5-7-1, Shiba, Minato-ku, Tokyo NEC Corporation

Claims (3)

[Claims] 1. A semiconductor device including a constituent element of an electric circuit capable of improving electric characteristics by increasing a surface area, wherein the constituent element is formed of polycrystalline silicon having a surface made of porous silicon. Semiconductor device. 2. A semiconductor device in which an integrated circuit is formed, which includes a capacitive element having a first electrode and a second electrode facing the first electrode via a dielectric, wherein the first electrode is the first electrode. A semiconductor device, wherein at least a part of a surface facing the two electrodes is made of polycrystalline silicon having porous silicon. 3. A semiconductor device comprising: a step of forming a lower electrode; a step of forming a dielectric covering the lower electrode; and a step of forming an upper electrode facing the lower electrode via the dielectric. In the manufacturing method, the step of forming the lower electrode includes the step of making the surface porous silicon, and in the step of forming the dielectric, the dielectric is formed in contact with the surface defining the pores of the porous silicon. A method of manufacturing a semiconductor device, comprising: