[go: up one dir, main page]

JPH06132472A - Ic package - Google Patents

Ic package

Info

Publication number
JPH06132472A
JPH06132472A JP4307808A JP30780892A JPH06132472A JP H06132472 A JPH06132472 A JP H06132472A JP 4307808 A JP4307808 A JP 4307808A JP 30780892 A JP30780892 A JP 30780892A JP H06132472 A JPH06132472 A JP H06132472A
Authority
JP
Japan
Prior art keywords
package
chip capacitor
mounting
mounting board
mold body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4307808A
Other languages
Japanese (ja)
Inventor
Tadashi Ichimasa
忠志 一政
Takao Okidono
貴朗 沖殿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4307808A priority Critical patent/JPH06132472A/en
Publication of JPH06132472A publication Critical patent/JPH06132472A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To realize high density mounting by allowing mounting of other circuit components on the rear side of an IC package body. CONSTITUTION:In a resin molded body (sealing resin) 4 constituting an IC package 101, a chip capacitor 210 is resin sealed together with a semiconductor element such that the metallized electrode 212 thereof is exposed to the mounting board side of package thus mounting the chip capacitor 210 integrally with the IC package 101.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明はICパッケージに関
し、特に特性上ノイズ対策として必要であるチップコン
デンサとICパッケージとを立体的に実装するためのパ
ッケージ構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC package, and more particularly to a package structure for three-dimensionally mounting a chip capacitor and an IC package which are required as a countermeasure against noise.

【0002】[0002]

【従来の技術】図5(a) は実装基板上に実装される従来
の表面実装型のICパッケージの構造を説明するための
断面図であり、200はIC素子(半導体素子)1を搭
載したSOP(Small Outline Package)パッケージ(以
下ICパッケージという。)で、上記IC素子1をダイ
パッド3上に銀ペースト等のロー材6により固着し、上
記IC素子1とICリード2とを金ワイヤ5により接続
し、全体を封止樹脂4により封止してなる構造となって
いる。ここで上記封止樹脂4は外部環境から半導体素子
1を保護するものであり、また上記ICリード2はガル
ウィング形リードで、その高さ方向の寸法が短く、実装
状態でICパッケージの高さができるだけ低くなるよう
工夫されている。
2. Description of the Related Art FIG. 5 (a) is a sectional view for explaining the structure of a conventional surface mount type IC package mounted on a mounting substrate, and 200 is an IC element (semiconductor element) 1 mounted thereon. In a SOP (Small Outline Package) package (hereinafter referred to as an IC package), the IC element 1 is fixed on the die pad 3 by a brazing material 6 such as silver paste, and the IC element 1 and the IC lead 2 are connected by a gold wire 5. The structure is such that they are connected and the whole is sealed with the sealing resin 4. Here, the encapsulating resin 4 protects the semiconductor element 1 from the external environment, and the IC lead 2 is a gull wing type lead, and the dimension in the height direction is short, and the height of the IC package in the mounted state is high. It is designed to be as low as possible.

【0003】また図5(b) は実装基板上に実装されるチ
ップコンデンサを示しており、図中210はノイズ対策
用チップコンデンサで、そのセラミック筺体211内に
対向電極(図示せず)を有し、該セラミック筺体211
の両端部表面上には上記対向電極に接続されたメタライ
ズ電極212が形成されている。
Further, FIG. 5 (b) shows a chip capacitor mounted on a mounting substrate. In the figure, 210 is a noise countermeasure chip capacitor having a counter electrode (not shown) in a ceramic housing 211 thereof. Then, the ceramic housing 211
A metallized electrode 212 connected to the counter electrode is formed on the surfaces of both ends of the.

【0004】図6は上記ICパッケージ及びチップコン
デンサを用いてモジュール化した半導体モジュールの一
例を示しており、図中201は半導体モジュールで、そ
の実装基板10上には上記ICパッケージ200及びチ
ップコンデンサ210が実装されている。ここで12,
13はそれぞれ上記実装基板10の所定位置に形成され
た実装基板側電極で、該電極12は上記ICパッケージ
200のICリード2と、また上記電極13はチップコ
ンデンサ210のメタライズ電極212とはんだにより
固着され、電気的に接続されている。また11は上記実
装基板10上にその一側辺に沿って複数形成されたソケ
ット20との接続用電極である。
FIG. 6 shows an example of a semiconductor module modularized using the IC package and the chip capacitor. In the figure, 201 is a semiconductor module, and the IC package 200 and the chip capacitor 210 are mounted on the mounting substrate 10. Has been implemented. Where 12,
Reference numeral 13 denotes a mounting board side electrode formed at a predetermined position of the mounting board 10. The electrode 12 is fixed to the IC lead 2 of the IC package 200, and the electrode 13 is fixed to the metallized electrode 212 of the chip capacitor 210 by soldering. And are electrically connected. Reference numeral 11 denotes an electrode for connection with a plurality of sockets 20 formed on the mounting board 10 along one side thereof.

【0005】このような構造の半導体モジュール201
では、これをソケット20に装着し、所定の信号を該ソ
ケット20を介して実装基板10の電極11に印加する
と、ICパッケージ200内の半導体素子1により所定
の信号処理が行われると同時に、チップコンデンサ21
0により信号の雑音処理が行われる。
The semiconductor module 201 having such a structure
Then, when this is mounted in the socket 20 and a predetermined signal is applied to the electrode 11 of the mounting substrate 10 via the socket 20, the semiconductor element 1 in the IC package 200 performs predetermined signal processing and, at the same time, the chip. Capacitor 21
When 0, noise processing of the signal is performed.

【0006】[0006]

【発明が解決しようとする課題】ところがノイズ対策用
チップコンデンサは、通常1つのICパッケージに対し
て1つ必要であり、このため複数のICパッケージが実
装基板上に実装された半導体モジュールでは、上記チッ
プコンデンサが実装基板上で占める面積も大きくなって
しまう。また上記ICパッケージは、半導体モジュール
の厚み、つまり実装基板上でのICパッケージの高さを
抑えるため、ICリード2の高さ方向の寸法を短くして
おり、このためパッケージ本体(封止樹脂)4の下面と
実装基板との間にはほとんどスペースがなく、チップコ
ンデンサをICパッケージの下側に配置して高密度実装
を実現することも困難であるという問題があった。
However, it is usually necessary to provide one chip capacitor for noise suppression for one IC package. Therefore, in a semiconductor module in which a plurality of IC packages are mounted on a mounting board, The area occupied by the chip capacitor on the mounting board also becomes large. Further, in the above IC package, in order to suppress the thickness of the semiconductor module, that is, the height of the IC package on the mounting substrate, the dimension of the IC lead 2 in the height direction is shortened. Therefore, the package body (sealing resin) There is almost no space between the lower surface of No. 4 and the mounting board, and it is difficult to realize high-density mounting by disposing the chip capacitor on the lower side of the IC package.

【0007】この発明は上記のような問題点を解消する
ためになされたもので、他の回路部品をICパッケージ
本体の下側に配置して実装することができ、高密度実装
を実現できるICパッケージを得ることを目的とする。
The present invention has been made in order to solve the above problems, and it is possible to arrange and mount other circuit components on the lower side of the IC package body, and to realize high-density mounting. Intended to get the package.

【0008】[0008]

【課題を解決するための手段】この発明に係るICパッ
ケージは、これを構成する樹脂モールド体を、半導体素
子とともにチップコンデンサをその電極が上記パッケー
ジ本体の実装基板側に露出するよう樹脂封止してなる構
造とし、上記樹脂モールド体をこれと一体である上記チ
ップコンデンサと同時に上記実装基板上に実装可能に構
成したものである。
In an IC package according to the present invention, a resin mold body constituting the IC package is resin-sealed together with a semiconductor element so that electrodes of the chip capacitor are exposed to the mounting substrate side of the package body. The resin mold body can be mounted on the mounting board at the same time as the chip capacitor integrated with the resin mold body.

【0009】この発明に係るICパッケージは、これを
構成する樹脂モールド体を、実装基板上に配置されたチ
ップコンデンサの上部が入り込むようその実装基板側に
形成された部品逃がし穴を有する構造とし、上記樹脂モ
ールド体を、上記実装基板上に実装されたチップコンデ
ンサをその部品逃がし穴に挿入して上記実装基板上に実
装可能に構成したものである。
In the IC package according to the present invention, the resin mold body constituting the IC package has a component escape hole formed on the mounting board side so that the upper portion of the chip capacitor arranged on the mounting board can be inserted thereinto, The resin mold body is configured to be mountable on the mounting board by inserting the chip capacitor mounted on the mounting board into the component escape hole.

【0010】[0010]

【作用】この発明においては、ICパッケージを構成す
る樹脂モールド体を、チップコンデンサをその電極がパ
ッケージ本体の実装基板側に露出するよう半導体素子と
ともに樹脂封止してなる構造とし、上記樹脂モールド体
をこれと一体である上記チップコンデンサと同時に上記
実装基板上に実装できるようにしたから、ICパッケー
ジを実装基板上に搭載した状態では、該ICパッケージ
の下側にチップコンデンサが位置することとなり、この
ような立体的な素子の実装により高密度実装を実現でき
る。
According to the present invention, the resin molded body constituting the IC package is structured such that the chip capacitor is resin-sealed together with the semiconductor element so that the electrodes of the chip capacitor are exposed to the mounting substrate side of the package body. Since it can be mounted on the mounting substrate at the same time as the chip capacitor integrated with the chip capacitor, the chip capacitor is located below the IC package when the IC package is mounted on the mounting substrate. High-density mounting can be realized by mounting such three-dimensional elements.

【0011】また、チップコンデンサの実装はICパッ
ケージと同時に行われることとなり、回路部品の実装作
業に要する時間を短縮することができる。
Since the chip capacitors are mounted at the same time as the IC package, the time required for mounting the circuit parts can be shortened.

【0012】この発明においては、ICパッケージを構
成する樹脂モールド体を、実装基板上に配置されたチッ
プコンデンサの上部が入り込むようその実装基板側に形
成された部品逃がし穴を有する構造とし、上記樹脂モー
ルド体を、上記実装基板上に実装されたチップコンデン
サをその部品逃がし穴に挿入して上記実装基板上に実装
できるようにしたので、上記と同様ICパッケージとチ
ップコンデンサとの立体的な実装により高密度実装を実
現できる。
According to the present invention, the resin molded body constituting the IC package has a structure having a component escape hole formed on the side of the mounting substrate so that the upper portion of the chip capacitor arranged on the mounting substrate can enter the resin molded body. Since the mold body can be mounted on the mounting board by inserting the chip capacitor mounted on the mounting board into the component escape hole, the three-dimensional mounting of the IC package and the chip capacitor can be performed in the same manner as above. High-density mounting can be realized.

【0013】[0013]

【実施例】実施例1.図1は本発明の第1の実施例によ
るICパッケージの構造を説明するための図、図2は該
ICパッケージの実装方法を説明するための図であり、
図において、101は本実施例のICパッケージで、こ
れはチップコンデンサ210をICパッケージと一体の
ものとして実装できるようになっている。つまり上記I
Cパッケージ101では、これを構成する樹脂モールド
体(封止樹脂)4は、上記半導体素子1とともに上記チ
ップコンデンサ210をその電極212が上記パッケー
ジ本体の実装基板側に露出するよう樹脂封止してなる構
造をしており、上記チップコンデンサ210は、そのメ
タライズ電極212の実装基板との接触面が上記ICリ
ード2の実装基板との接触面と面一となるよう位置決め
されている。
EXAMPLES Example 1. 1 is a diagram for explaining a structure of an IC package according to a first embodiment of the present invention, and FIG. 2 is a diagram for explaining a mounting method of the IC package.
In the figure, 101 is the IC package of this embodiment, which is capable of mounting the chip capacitor 210 as an integral part of the IC package. That is, the above I
In the C package 101, the resin mold body (sealing resin) 4 constituting the C package 101 is resin-sealed together with the semiconductor element 1 so that the electrode 212 of the chip capacitor 210 is exposed to the mounting substrate side of the package body. The chip capacitor 210 is positioned so that the contact surface of the metallized electrode 212 with the mounting substrate is flush with the contact surface of the IC lead 2 with the mounting substrate.

【0014】また実装基板10上の所定位置には、IC
リード2との接続用電極12及びチップコンデンサ21
0のメタライズ電極212との接続用電極13とがそれ
ぞれ形成されており、これらの電極表面にはハンダペー
ストが塗布されている。その他の構成は従来のICパッ
ケージ200と同一である。
At a predetermined position on the mounting board 10, an IC is placed.
Electrode 12 for connection with lead 2 and chip capacitor 21
No. 0 metallization electrode 212 and connection electrode 13 are formed, and solder paste is applied to the surfaces of these electrodes. Other configurations are the same as those of the conventional IC package 200.

【0015】次に実装方法について説明する。まず図2
(a) に示すようにチップコンデンサ210を搭載したI
Cパッケージ101を、上記実装基板10上の各電極1
2,13に対し平面的に位置決めし(図2(a) )、該I
Cパッケージ101を実装基板10の表面上に載せる。
この状態ではICリード2及びチップコンデンサのメタ
ライズ電極212はそれぞれ上記電極12,13に接触
している。その後熱処理を行って上記ハンダペーストを
溶融させて、上記ICリード2及びチップコンデンサの
メタライズ電極212をそれぞれ上記電極12,13に
固着する。これにより上記ICパッケージ101がチッ
プコンデンサ210とともに実装基板10上に固定され
る。
Next, a mounting method will be described. First, Figure 2
As shown in (a), I
The C package 101 is attached to each electrode 1 on the mounting substrate 10.
2 and 13 are positioned in a plane (Fig. 2 (a)) and the I
The C package 101 is placed on the surface of the mounting substrate 10.
In this state, the IC lead 2 and the metallized electrode 212 of the chip capacitor are in contact with the electrodes 12 and 13, respectively. After that, heat treatment is performed to melt the solder paste and fix the metallized electrodes 212 of the IC lead 2 and the chip capacitor to the electrodes 12 and 13, respectively. As a result, the IC package 101 is fixed on the mounting substrate 10 together with the chip capacitor 210.

【0016】このような構成のICパッケージ101で
は、チップコンデンサ210をその電極212がパッケ
ージ本体の実装基板側に露出するよう半導体素子1とと
もに樹脂封止し、上記チップコンデンサ210を上記I
Cパッケージ101と一体のものとして実装できるよう
にしたので、ICパッケージ101を実装基板10上に
載置した状態では、該ICパッケージ101の下側にチ
ップコンデンサ210が位置することとなり、このよう
な立体的な素子の実装により高密度実装を実現すること
ができる。
In the IC package 101 having such a structure, the chip capacitor 210 is resin-sealed together with the semiconductor element 1 so that the electrode 212 of the chip capacitor 210 is exposed to the mounting substrate side of the package body, and the chip capacitor 210 is replaced with the I capacitor.
Since it can be mounted integrally with the C package 101, when the IC package 101 is mounted on the mounting substrate 10, the chip capacitor 210 is located below the IC package 101. High-density mounting can be realized by mounting three-dimensional elements.

【0017】また、チップコンデンサ210の実装はI
Cパッケージ101と同時に行われることとなり、部品
の実装作業に要する時間を短縮することができる。
The chip capacitor 210 is mounted by I
Since it is performed at the same time as the C package 101, the time required for the component mounting work can be shortened.

【0018】実施例2.図3は本発明の第2の実施例に
よるICパッケージを説明するための図、図4は該IC
パッケージの実装方法を説明するための図である。図に
おいて、102は本実施例のICパッケージで、このI
Cパッケージ120はチップコンデンサ210上に覆い
被さるよう重ねて実装できるようになっている。つまり
上記ICパッケージ102は、これを構成する樹脂モー
ルド体(封止樹脂)4が、実装基板10上に配置された
チップコンデンサ210の上部が入り込むようその実装
基板側に形成された部品逃がし穴4aを有する構造とし
たものである。その他の構成は上記従来のICパッケー
ジ200と同一であり、実装基板10の構成は第1の実
施例のものと同一である。
Example 2. FIG. 3 is a diagram for explaining an IC package according to the second embodiment of the present invention, and FIG. 4 is the IC package.
It is a figure for demonstrating the mounting method of a package. In the figure, 102 is the IC package of this embodiment,
The C package 120 can be mounted so as to be overlaid on the chip capacitor 210 so as to cover it. That is, in the IC package 102, the resin mold body (sealing resin) 4 constituting the IC package 102 is formed in the component escape hole 4a formed on the side of the mounting substrate 10 so that the upper portion of the chip capacitor 210 arranged on the mounting substrate 10 enters. The structure has The other structure is the same as that of the conventional IC package 200, and the structure of the mounting substrate 10 is the same as that of the first embodiment.

【0019】次に実装方法について説明する。まず図4
(a) に示すようにチップコンデンサ210をそのメタラ
イズ電極212が上記電極13と対向するよう上記実装
基板10上で位置決めし(図4(a) )、該チップコンデ
ンサ210を実装基板10の表面上に載せる。続いてI
Cパッケージ102を上記チップコンデンサ210に対
してその上部が上記ICパッケージ102の部品逃がし
穴4aに入り込むよう、かつICリード2が電極12に
対向するよう位置決めし(図4(b) )、実装基板10上
に載置する(図4(c) )。この状態では、上記チップコ
ンデンサ210のメタライズ電極212は実装基板上の
電極13と接触し、またICパッケージ102の部品逃
がし穴4aには上記チップコンデンサ210の上部が入
り込んでパッケージ102のICリード2は実装基板1
0上の電極12と接触している。
Next, a mounting method will be described. Figure 4
As shown in (a), the chip capacitor 210 is positioned on the mounting substrate 10 so that its metallized electrode 212 faces the electrode 13 (FIG. 4 (a)), and the chip capacitor 210 is placed on the surface of the mounting substrate 10. Put on. Then I
The C package 102 is positioned with respect to the chip capacitor 210 such that the upper part thereof enters the component escape hole 4a of the IC package 102 and the IC lead 2 faces the electrode 12 (FIG. 4 (b)). Place on top of 10 (Fig. 4 (c)). In this state, the metallized electrode 212 of the chip capacitor 210 is in contact with the electrode 13 on the mounting board, and the upper part of the chip capacitor 210 is inserted into the component escape hole 4a of the IC package 102 so that the IC lead 2 of the package 102 is Mounting board 1
0 is in contact with the upper electrode 12.

【0020】そしてこの状態で熱処理を行って、上記各
電極12,13表面に塗布されたハンダペーストを溶融
させ、上記ICリード2及びチップコンデンサ210の
メタライズ電極212をそれぞれ上記電極12,13に
固着する。これにより上記ICパッケージ102及びチ
ップコンデンサ210が実装基板10上に固定される。
Then, heat treatment is performed in this state to melt the solder paste applied to the surfaces of the electrodes 12 and 13 and fix the metallized electrodes 212 of the IC lead 2 and the chip capacitor 210 to the electrodes 12 and 13, respectively. To do. As a result, the IC package 102 and the chip capacitor 210 are fixed on the mounting substrate 10.

【0021】このような構成のICパッケージ102で
は、これを構成する樹脂モールド体4を、実装基板10
上に配置されたチップコンデンサ210の上部が入り込
むようその実装基板側に部品逃がし穴4aを形成した構
造とし、上記ICパッケージ102を上記チップコンデ
ンサ10上に覆い被さるよう重ねて実装できるようにし
たので、上記第1の実施例と同様ICパッケージ102
とチップコンデンサ201との立体的な実装により高密
度実装を実現できる。
In the IC package 102 having such a structure, the resin mold body 4 constituting the IC package 102 is mounted on the mounting substrate 10.
Since the component escape hole 4a is formed on the side of the mounting substrate so that the upper portion of the chip capacitor 210 arranged above can be inserted, the IC package 102 can be mounted over the chip capacitor 10 so as to cover it. , The IC package 102 as in the first embodiment.
High-density mounting can be realized by three-dimensional mounting of the chip capacitor 201 and the chip capacitor 201.

【0022】なお上記各実施例では、パッケージのリー
ドがSOPパッケージ(small outline package)に採用
されているガルウィング形リードである場合について示
したが、リードの形状はこれに限るものではない。
In each of the embodiments described above, the lead of the package is the gull wing type lead adopted in the SOP package (small outline package), but the lead shape is not limited to this.

【0023】[0023]

【発明の効果】以上のようにこの発明に係るICパッケ
ージによれば、該ICパッケージを構成する樹脂モール
ド体を、チップコンデンサをその電極がパッケージ本体
の実装基板側に露出するよう半導体素子とともに樹脂封
止してなる構造とし、上記樹脂モールド体をこれと一体
である上記チップコンデンサと同時に上記実装基板上に
実装可能に構成したので、ICパッケージを実装基板上
に搭載した状態では、樹脂モールド体の下側にチップコ
ンデンサが位置することとなり、このような立体的な素
子の実装により高密度実装を実現できるという効果があ
る。
As described above, according to the IC package of the present invention, the resin molded body forming the IC package is molded together with the semiconductor element so that the electrodes of the chip capacitor are exposed to the mounting substrate side of the package body. Since the structure is such that it is sealed, and the resin mold body can be mounted on the mounting board at the same time as the chip capacitor integrated with the resin mold body, when the IC package is mounted on the mounting board, the resin molding body is mounted. Since the chip capacitor is located on the lower side, there is an effect that high-density mounting can be realized by mounting such a three-dimensional element.

【0024】また、チップコンデンサの実装はICパッ
ケージと同時に行われることとなり、部品の実装作業に
要する時間を短縮することができるという効果もある。
Since the chip capacitors are mounted at the same time as the IC package, there is an effect that the time required for mounting the parts can be shortened.

【0025】またこの発明に係るICパッケージによれ
ば、該ICパッケージを構成する樹脂モールド体を、実
装基板上に配置されたチップコンデンサの上部が入り込
むようその実装基板側に形成された部品逃がし穴を有す
る構造とし、上記樹脂モールド体を、上記実装基板上に
実装されたチップコンデンサをその部品逃がし穴に挿入
して実装可能に構成したので、上記と同様ICパッケー
ジとチップコンデンサとの立体的な実装により高密度実
装を実現できる効果がある。
Further, according to the IC package of the present invention, the resin relief forming the IC package is formed on the side of the mounting board so that the upper portion of the chip capacitor arranged on the mounting board is inserted into the resin molding body. Since the resin mold body is configured to be mountable by inserting the chip capacitor mounted on the mounting board into the component escape hole, the three-dimensional structure of the IC package and the chip capacitor can be achieved in the same manner as above. There is an effect that high density mounting can be realized by mounting.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1の実施例によるICパッケージ
の構造を説明するための断面図である。
FIG. 1 is a sectional view for explaining a structure of an IC package according to a first embodiment of the present invention.

【図2】上記ICパッケージの実装方法を説明するため
の図である。
FIG. 2 is a diagram for explaining a mounting method of the IC package.

【図3】この発明の第2の実施例によるICパッケージ
の構造を説明するための断面図である。
FIG. 3 is a sectional view for explaining the structure of an IC package according to a second embodiment of the present invention.

【図4】上記第2実施例のICパッケージを実装する方
法を説明するための図である。
FIG. 4 is a diagram for explaining a method of mounting the IC package of the second embodiment.

【図5】従来のICパッケージの構造を説明するための
断面図である。
FIG. 5 is a cross-sectional view for explaining the structure of a conventional IC package.

【図6】従来のICパッケージ及びチップコンデンサを
実装基板上に実装してなる半導体モジュールを説明する
ための平面図である。
FIG. 6 is a plan view for explaining a semiconductor module in which a conventional IC package and a chip capacitor are mounted on a mounting board.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 ICリード 3 ダイパッド 4 封止樹脂(樹脂モールド体) 4a 部品逃がし穴 5 金ワイヤ 6 ロー材 10 実装基板 11 ソケットとの接続用電極 12 ICリードとの接続用電極 13 チップコンデンサとの接続用電極 101,102 ICパッケージ 210 チップコンデンサ 211 セラミック筺体 212 メタライズ電極 1 Semiconductor Element 2 IC Lead 3 Die Pad 4 Sealing Resin (Resin Molded Body) 4a Component Escape Hole 5 Gold Wire 6 Brazing Material 10 Mounting Board 11 Socket Connecting Electrode 12 IC Lead Connecting Electrode 13 Chip Capacitor Connection electrodes 101, 102 IC package 210 Chip capacitor 211 Ceramic housing 212 Metallized electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 内部に半導体素子が封入された樹脂モー
ルド体からなり、実装基板上に実装されるICパッケー
ジにおいて、 上記樹脂モールド体は、上記半導体素子とともに、チッ
プコンデンサをその電極が上記パッケージ本体の実装基
板側に露出するよう一体的に樹脂封止してなるものであ
り、 上記樹脂モールド体は、これと一体である上記チップコ
ンデンサと同時に上記実装基板上に実装可能であること
を特徴とするICパッケージ。
1. An IC package, which comprises a resin mold body having a semiconductor element enclosed therein and is mounted on a mounting substrate, wherein the resin mold body, together with the semiconductor element, has a chip capacitor and electrodes of the package body. The resin mold body is integrally sealed so as to be exposed to the mounting board side, and the resin mold body can be mounted on the mounting board at the same time as the chip capacitor integrated with the resin molding body. IC package to do.
【請求項2】 内部に半導体素子が封入された樹脂モー
ルド体からなり、実装基板上に実装されるICパッケー
ジにおいて、 上記樹脂モールド体は、実装基板上に配置されたチップ
コンデンサの上部が入り込むようその実装基板側に形成
された部品逃がし穴を有し、 上記樹脂モールド体は、上記実装基板に実装されたチッ
プコンデンサを、その部品逃がし穴に挿入して上記実装
基板上に実装可能であることを特徴とするICパッケー
ジ。
2. An IC package, comprising a resin mold body having a semiconductor element encapsulated therein, which is mounted on a mounting board, wherein the resin mold body is such that an upper portion of a chip capacitor arranged on the mounting board is inserted thereinto. It has a component escape hole formed on the mounting board side, and the resin mold body can be mounted on the mounting board by inserting the chip capacitor mounted on the mounting board into the component escape hole. IC package characterized by.
JP4307808A 1992-10-20 1992-10-20 Ic package Pending JPH06132472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4307808A JPH06132472A (en) 1992-10-20 1992-10-20 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4307808A JPH06132472A (en) 1992-10-20 1992-10-20 Ic package

Publications (1)

Publication Number Publication Date
JPH06132472A true JPH06132472A (en) 1994-05-13

Family

ID=17973472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4307808A Pending JPH06132472A (en) 1992-10-20 1992-10-20 Ic package

Country Status (1)

Country Link
JP (1) JPH06132472A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834832A (en) * 1994-06-09 1998-11-10 Samsung Electronics Co., Ltd. Packing structure of semiconductor packages
US6995448B2 (en) * 2001-04-02 2006-02-07 Amkor Technology, Inc. Semiconductor package including passive elements and method of manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834832A (en) * 1994-06-09 1998-11-10 Samsung Electronics Co., Ltd. Packing structure of semiconductor packages
US6995448B2 (en) * 2001-04-02 2006-02-07 Amkor Technology, Inc. Semiconductor package including passive elements and method of manufacture

Similar Documents

Publication Publication Date Title
US5800958A (en) Electrically enhanced power quad flat pack arrangement
JP2000133767A (en) Laminated semiconductor package and its manufacture
KR0177395B1 (en) Chip mounted circuit board and method for manufacturing the same
JP2885414B2 (en) Semiconductor device, mounting method thereof, and electronic device
US5349235A (en) High density vertically mounted semiconductor package
US5031025A (en) Hermetic single chip integrated circuit package
EP0221496A2 (en) Integrated circuit package
JPH0730059A (en) Multichip module
US5719748A (en) Semiconductor package with a bridge for chip area connection
JPH06132472A (en) Ic package
JPH0582582A (en) Semiconductor device
JP2524482B2 (en) QFP structure semiconductor device
JP2541532B2 (en) Semiconductor module
CN104037096B (en) The method of packaging system and manufacture packaging system
KR0163214B1 (en) Integrated circuit package using ceramic substrate and manufacturing method thereof
JPH08279593A (en) Semiconductor device for high-density mounting
JP2822990B2 (en) CSP type semiconductor device
JPH0222886A (en) Hybrid integrated circuit
KR950013049B1 (en) Multi chip loc package
JP2000260931A (en) Semiconductor device and its manufacture
JPS62219531A (en) Semiconductor integrated circuit device
JPH04216653A (en) Package for semiconductor integrated circuit and its packaging method
KR100342811B1 (en) Area array bumped semiconductor package with chips
KR950008240B1 (en) Semiconductor package
KR200313831Y1 (en) Bottom Lead Package