JPH06132292A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH06132292A JPH06132292A JP27863192A JP27863192A JPH06132292A JP H06132292 A JPH06132292 A JP H06132292A JP 27863192 A JP27863192 A JP 27863192A JP 27863192 A JP27863192 A JP 27863192A JP H06132292 A JPH06132292 A JP H06132292A
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- gettering
- silicon single
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置及びその
製造方法に関し、更に詳しくは、ＳＯＩ（Ｓilicｏn Ｏ
n Ｉnsulator）素子のゲッタリング構造及びその形成方
法に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, more specifically, an SOI (Silicon O
n Insulator) element gettering structure and method for forming the gettering structure.
【０００２】[0002]
【従来の技術】一般に、単結晶シリコン上に素子を作成
する場合には、素子製造工程中に混入するＦｅ，Ｃｒ，
Ｎｉ等の重金属原子による汚染が生じる。このような重
金属汚染を捕獲するゲッタリング技術としては、エクス
トリンシックゲッタリング法（ＥＧ法）とイントリンシ
ックゲッタリング法が知られている。2. Description of the Related Art Generally, when an element is formed on single crystal silicon, Fe, Cr, and
Contamination by heavy metal atoms such as Ni occurs. As a gettering technique for capturing such heavy metal contamination, an extrinsic gettering method (EG method) and an intrinsic gettering method are known.
【０００３】ＥＧ法は、基板裏面に、サンドブラスト，
レーザ照射を施したり、多結晶シリコン等を裏面に形成
することにより、歪領域を形成し、ゲッタリング源とす
る手法である。The EG method involves sandblasting,
This is a method in which a strained region is formed by applying laser irradiation or by forming polycrystalline silicon or the like on the back surface and using it as a gettering source.
【０００４】また、ＩＧ法は、基板内部に、過飽和格子
間酸素を析出させ、形成された酸素析出物と二次欠陥を
ゲッタリング源とする手法である。The IG method is a method in which supersaturated interstitial oxygen is precipitated inside the substrate and the formed oxygen precipitates and secondary defects are used as gettering sources.
【０００５】しかし、シリコンウエハ上に絶縁膜を形成
し、この絶縁膜上に、多結晶シリコンを堆積させレーザ
照射等の熱線により溶融再結晶化させてシリコン単結晶
膜を形成及びＳＯＩ構造においては、上記したＥＧ法及
びＩＧ法は適用することができない。即ち、上記シリコ
ン単結晶膜は、溶融再結晶化させる前の多結晶シリコン
をＣＶＤ法等で形成するため、酸素含有量は少なく、Ｉ
Ｇ法を用いることができない。また、このように絶縁膜
上に薄いシリコン単結晶膜を形成したＳＯＩ基板におい
ては、裏面や基板内部にゲッタリング源を形成しても、
絶縁膜が障壁となってゲッタリング作用を得ることがで
きない。However, an insulating film is formed on a silicon wafer, and polycrystalline silicon is deposited on the insulating film and melted and recrystallized by a heat ray such as laser irradiation to form a silicon single crystal film. The above-mentioned EG method and IG method cannot be applied. That is, since the above-mentioned silicon single crystal film is formed of polycrystalline silicon before being melted and recrystallized by a CVD method or the like, it has a low oxygen content and I
The G method cannot be used. Further, in the SOI substrate in which the thin silicon single crystal film is formed on the insulating film as described above, even if the gettering source is formed on the back surface or inside the substrate,
The gettering effect cannot be obtained because the insulating film serves as a barrier.
【０００６】そこで、このような問題の対策として、特
開平１−１８１４７３号公報記載に係るＳＯＩ素子の形
成技術が提案されている。この従来技術は、図１６に示
すように、絶縁膜１上にシリコン単結晶膜２を形成し、
このシリコン単結晶膜２内にソース・ドレイン領域３，
４及びチャネル領域５を形成すると共に、ゲッタリング
源の酸素析出物である欠陥層６，７を形成している。こ
の欠陥層６，７は、窒素（Ｎ）を、シリコン単結晶膜２
の絶縁膜１との界面付近で、ソース・ドレイン領域３，
４の下の領域にイオン注入し、熱処理によってＮを核と
する析出物の核形成を行った後、更に高温の熱処理で酸
素析出を行って形成されている。Therefore, as a countermeasure against such a problem, a technique for forming an SOI element, which is disclosed in Japanese Patent Application Laid-Open No. 1-181473, has been proposed. In this conventional technique, as shown in FIG. 16, a silicon single crystal film 2 is formed on an insulating film 1,
In the silicon single crystal film 2, the source / drain regions 3,
4 and the channel region 5, the defect layers 6 and 7 which are oxygen precipitates of the gettering source are formed. The defect layers 6 and 7 contain nitrogen (N) for the silicon single crystal film 2
Near the interface with the insulating film 1 of the source / drain region 3,
4 is ion-implanted in the region under 4 and nucleation of precipitates having N as a nucleus is performed by heat treatment, and then oxygen precipitation is performed by further heat treatment at high temperature.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上記従
来技術にあっては、ゲッタリング源が酸素析出物で成る
欠陥層６，７がソース・ドレイン領域３，４の下にある
ため、ソース・ドレイン領域３，４と欠陥６，７を両方
形成するとなると、シリコン単結晶膜２を厚く形成しな
ければならないという問題が生じる。特に、欠陥層６，
７をシリコン単結晶膜２の下部のみに形成するには、イ
オン注入の打込み深さの制御及び温度制御が困難である
ため、歩留りを低下させる問題点を有している。However, in the above-mentioned prior art, the defect layers 6 and 7 whose gettering sources are oxygen precipitates are located under the source / drain regions 3 and 4, and therefore the source / drain regions are not formed. If both the regions 3 and 4 and the defects 6 and 7 are formed, there arises a problem that the silicon single crystal film 2 must be formed thick. In particular, the defect layer 6,
When 7 is formed only in the lower part of the silicon single crystal film 2, it is difficult to control the implantation depth of ion implantation and the temperature, and thus there is a problem that the yield is reduced.
【０００８】また、酸素析出物で成る欠陥層をソース・
ドレイン領域の下でなくて、外側に位置させて形成した
場合、今度はシリコン単結晶膜の幅寸法を長くする必要
が有り、素子の微細化傾向に逆行するものとなる。In addition, a defect layer composed of oxygen precipitates is
If it is formed not outside the drain region but outside the drain region, it is necessary to increase the width dimension of the silicon single crystal film, which goes against the trend toward miniaturization of the device.
【０００９】本発明は、このような従来の問題点に着目
して創案されたものであって、有効なゲッタリング構造
を有するＳＯＩ構造の半導体装置及び歩留りを向上する
その半導体装置の製造方法を得んとするものである。The present invention was devised in view of the above conventional problems, and provides a semiconductor device having an SOI structure having an effective gettering structure and a method of manufacturing the semiconductor device for improving the yield. It is what you get.
【００１０】[0010]
【課題を解決するための手段】請求項１記載の発明は、
絶縁基板上のシリコン単結晶膜に形成した半導体装置に
おいて、前記シリコン単結晶膜外側面にゲッタリング用
欠陥膜を設けたことを、その解決手段としている。The invention according to claim 1 is
In a semiconductor device formed on a silicon single crystal film on an insulating substrate, a gettering defect film is provided on the outer surface of the silicon single crystal film as a solution.
【００１１】請求項２記載の発明は、上記ゲッタリング
用欠陥膜をソース・ドレイン電極の一部としたことを特
徴としている。The invention according to claim 2 is characterized in that the gettering defect film is part of a source / drain electrode.
【００１２】請求項３記載の発明は、上記ゲッタリング
用欠陥膜を、シリコン単結晶膜側面に形成した平坦化用
サイドウォ−ルとしたことを特徴とする。According to a third aspect of the present invention, the gettering defect film is a flattening side wall formed on the side surface of the silicon single crystal film.
【００１３】請求項４記載の発明は、絶縁基板上にシリ
コン単結晶でなる素子形成領域層を形成する工程と、全
面に多結晶シリコン膜を堆積させた後、パターニングを
行い前記素子形成領域層のソース・ドレイン領域表面に
多結晶シリコン膜を残す工程と、前記ソース・ドレイン
領域上の夫々の多結晶シリコン膜に電極配線を接続させ
る工程を備えることを、その解決方法としている。According to a fourth aspect of the present invention, there is provided a step of forming an element formation region layer made of a silicon single crystal on an insulating substrate, and after depositing a polycrystalline silicon film on the entire surface, patterning is performed. The solution is to include the step of leaving the polycrystalline silicon film on the surface of the source / drain region and the step of connecting the electrode wiring to each polycrystalline silicon film on the source / drain region.
【００１４】[0014]
【作用】請求項１記載の発明においては、ＳＯＩ構造を
構成するシリコン単結晶膜の外側面にゲッタリング用欠
陥膜を設けるため、シリコン単結晶膜の膜厚及び幅寸法
を拡大することがなく、また、シリコン単結晶膜内に損
傷を得えることが回避できる。According to the first aspect of the invention, since the gettering defect film is provided on the outer surface of the silicon single crystal film forming the SOI structure, the thickness and width of the silicon single crystal film are not increased. Moreover, it is possible to avoid obtaining damage in the silicon single crystal film.
【００１５】請求項２記載の発明は、ソース・ドレイン
電極の一部がゲッタリング用欠陥膜であるため、ソース
・ドレイン領域への確実な接合を有し、ゲッタリング作
用を確実とする。According to the second aspect of the present invention, since a part of the source / drain electrode is a gettering defect film, the source / drain region has a reliable junction to ensure the gettering action.
【００１６】請求項３記載の発明は、絶縁膜表面から突
出しているシリコン単結晶膜の周側壁の平坦化用サイド
ウォールをゲッタリング用欠陥とすることにより、工程
を増やすことなく、ゲッタリング層を形成できる作用が
ある。According to a third aspect of the present invention, the gettering layer is formed without increasing the number of steps by using the flattening side wall of the silicon single crystal film protruding from the surface of the insulating film as a gettering defect. Can be formed.
【００１７】請求項４記載の発明は、多結晶シリコン膜
の堆積及びエッチングでゲッタリング欠陥膜が形成で
き、シリコン単結晶膜を損傷を与えずに半導体装置が製
造できる。このため、工程数の増加を抑制することが可
能となる。In a fourth aspect of the present invention, a gettering defect film can be formed by depositing and etching a polycrystalline silicon film, and a semiconductor device can be manufactured without damaging the silicon single crystal film. Therefore, it is possible to suppress an increase in the number of steps.
【００１８】[0018]
【実施例】以下、本発明に係る半導体装置及びその製造
方法の詳細を図面に示す実施例に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the embodiments shown in the drawings.
【００１９】（実施例１）本実施例は、ＳＯＩ構造を構
成するシリコン単結晶膜に電界効果トランジスタを製造
する場合に、本発明を適用したものである。(Embodiment 1) In this embodiment, the present invention is applied in the case of manufacturing a field effect transistor in a silicon single crystal film forming an SOI structure.
【００２０】先ず、ＳｉＯ2で成る絶縁膜１１上に、周
知の技術を用いて、図１に示すように、シリコン単結晶
膜１２を素子形成領域分だけパターニングして島状に形
成する。そして、全面に多結晶シリコン膜１３をＣＶＤ
法にて堆積させる。[0020] First, on the insulating film 11 made of SiO 2, using known techniques, as shown in FIG. 1, by patterning the silicon single crystal film 12 only element formation region component is formed in an island shape. Then, a polycrystalline silicon film 13 is formed on the entire surface by CVD.
It is deposited by the method.
【００２１】次に、多結晶シリコン膜１３をシリコン単
結晶膜１２上及び側壁を覆う範囲を残すように、リソグ
ラフィー技術及びエッチング技術を用いてパターニング
した後、全面にシリコンナイトライド（Ｓｉ3Ｎ4）膜１
４を堆積させる。そして、図２に示すように、レジスト
層１５をパターニングした後、シリコンナイトライド膜
１４及び多結晶シリコン膜１３をドライエッチングす
る。Next, the polycrystalline silicon film 13 is patterned by a lithography technique and an etching technique so as to leave a region covering the silicon single crystal film 12 and the side wall, and then silicon nitride (Si 3 N 4) is formed on the entire surface. ) Membrane 1
4 is deposited. Then, as shown in FIG. 2, after patterning the resist layer 15, the silicon nitride film 14 and the polycrystalline silicon film 13 are dry-etched.
【００２２】この後、レジスト層１５を除去し、熱酸化
（９５０℃程度）を行いゲート酸化膜１８を形成する。
次に、図３に示すように、全面に多結晶シリコンで成る
ゲート材料膜１５をＣＶＤ法にて堆積する。さらに、リ
ソグラフィー技術及びエッチング技術により、図４に示
すように、ゲート材料膜１５を加工してゲート電極１５
Ａを形成する。After that, the resist layer 15 is removed, and thermal oxidation (about 950 ° C.) is performed to form a gate oxide film 18.
Next, as shown in FIG. 3, a gate material film 15 made of polycrystalline silicon is deposited on the entire surface by a CVD method. Further, as shown in FIG. 4, the gate material film 15 is processed by the lithography technique and the etching technique to form the gate electrode 15.
Form A.
【００２３】次に、図５に示すように、全面にＳｉＯ2
膜１６を堆積させた後、ソース・ドレインへの接続孔を
多結晶シリコン膜１３の表面まで開口した後、周知の技
術を用いて、図６に示すように、ソース電極１７Ａ及び
ドレイン電極１７Ｂを形成して完成する。Next, as shown in FIG. 5, SiO 2 is formed on the entire surface.
After depositing the film 16, a source / drain connection hole is opened up to the surface of the polycrystalline silicon film 13, and then a source electrode 17A and a drain electrode 17B are formed using a well-known technique as shown in FIG. Form and complete.
【００２４】本実施例では、多結晶シリコン膜１３が、
シリコン単結晶膜１２に形成したソース領域１２Ａ及び
ドレイン領域１２Ｂを夫々覆うため、両領域の汚染源等
をゲッタリングする効果を奏する。In this embodiment, the polycrystalline silicon film 13 is
Since the source region 12A and the drain region 12B formed in the silicon single crystal film 12 are covered respectively, the effect of gettering the contamination source and the like in both regions is exerted.
【００２５】なお、上記実施例においては、ソース・ド
レイン領域の形成工程を省略して説明した。In the above embodiments, the process of forming the source / drain regions is omitted.
【００２６】（実施例２）図７〜図１１は、本発明の実
施例２の工程を示す断面図である。(Embodiment 2) FIGS. 7 to 11 are sectional views showing steps of Embodiment 2 of the present invention.
【００２７】本実施例は、図７に示すように、シリコン
基板２１上に、ＳｉＯ2で成る絶縁膜２２を形成し、周
知の技術（例えば多結晶シリコン膜のレーザ照射による
溶融再結晶化）を用いてシリコン単結晶膜２３を形成す
る。In this embodiment, as shown in FIG. 7, an insulating film 22 made of SiO 2 is formed on a silicon substrate 21, and a well-known technique (for example, melting and recrystallization of a polycrystalline silicon film by laser irradiation). Is used to form a silicon single crystal film 23.
【００２８】次に、図８に示すように、シリコン単結晶
膜２３の表面にシリコン酸化膜２４を熱酸化により形成
した後、レジストパターン２５を形成する。そして、こ
のレジストパターン２５をマスクとして、シリコン酸化
膜２４及びシリコン単結晶膜２３を異方性エッチング
（ＲＩＥ）した後、図７に示すように、全面に多結晶シ
リコン膜２６をＣＶＤ法にて堆積させる。Next, as shown in FIG. 8, a silicon oxide film 24 is formed on the surface of the silicon single crystal film 23 by thermal oxidation, and then a resist pattern 25 is formed. Then, using the resist pattern 25 as a mask, the silicon oxide film 24 and the silicon single crystal film 23 are anisotropically etched (RIE), and then a polycrystalline silicon film 26 is formed on the entire surface by a CVD method as shown in FIG. Deposit.
【００２９】次に、反応性イオンエッチング（ＲＩＥ）
により全面エッチバックを行いシリコン単結晶膜２３の
周側壁に、多結晶シリコン膜２６で成るサイドウォール
２６Ａを残す。なお、このサイドウォール２６Ａの高さ
は、後続の素子形成の加工性を考慮すると、シリコン単
結晶膜２３の膜厚と同じか、又は若干低い方が望まし
い。Next, reactive ion etching (RIE)
Then, the entire surface is etched back by means of which the side wall 26A made of the polycrystalline silicon film 26 is left on the peripheral side wall of the silicon single crystal film 23. The height of the side wall 26A is preferably equal to or slightly lower than the film thickness of the silicon single crystal film 23 in consideration of the workability of subsequent element formation.
【００３０】次に、シリコン酸化膜２４を除去した後、
通常の電界効果トランジスタ製造技術を用いれば、図１
１に示すようなトランジスタとなる。なお、図中２７は
ゲート酸化膜、２８はゲート電極、２９Ａはソース領
域、２９Ｂはドレイン領域を示している。Next, after removing the silicon oxide film 24,
Using conventional field effect transistor manufacturing technology,
The transistor shown in FIG. In the figure, 27 is a gate oxide film, 28 is a gate electrode, 29A is a source region, and 29B is a drain region.
【００３１】本実施例は、ゲッタリング用欠陥膜として
サイドウォール２６Ａを形成したことにより、ソース・
ドレイン領域を形成したシリコン単結晶膜２３のゲッタ
リングを側壁部で行うことができ、このサイドウォール
２６Ａはシリコン単結晶膜２３の絶縁膜２２に対する段
差を緩和し平坦化に寄与する。In this embodiment, since the sidewall 26A is formed as a gettering defect film, the source / source
Gettering of the silicon single crystal film 23 in which the drain region is formed can be performed on the side wall portion, and the side wall 26A contributes to flattening by reducing the step difference between the silicon single crystal film 23 and the insulating film 22.
【００３２】なお、本実施例では、ＭＯＳ型トランジス
タであるため、ソースとドレインが異電位となりサイド
ウォール２６Ａに漏れ電流が流れる可能性がある。この
ため、図１３に示すように形成したサイドウォール２６
Ａを、図１４に示すように、ソース・ドレイン領域２９
Ａ，２９Ｂの両脇のサイドウォール２６Ａを除去するこ
とが必要である。Since the MOS transistor is used in this embodiment, there is a possibility that the source and drain have different potentials and a leak current flows through the sidewall 26A. Therefore, the sidewall 26 formed as shown in FIG.
A is a source / drain region 29 as shown in FIG.
It is necessary to remove the sidewalls 26A on both sides of A and 29B.
【００３３】（実施例３）図１２は、実施例３を示す断
面図である。本実施例は、電界効果トランジスタではな
くバイポーラトランジスタを作成した例である。シリコ
ン単結晶膜の周縁部では、バイポーラトランジスタであ
るため、同電位となり、全周に亘ってサイドウォールを
設けることができる。(Third Embodiment) FIG. 12 is a sectional view showing a third embodiment. This embodiment is an example in which a bipolar transistor is formed instead of a field effect transistor. Since the periphery of the silicon single crystal film is a bipolar transistor, it has the same potential, and the sidewall can be provided over the entire circumference.
【００３４】（実施例４）図１５は、本発明の実施例４
を示す断面である。(Fourth Embodiment) FIG. 15 shows a fourth embodiment of the present invention.
Is a cross section showing.
【００３５】本実施例は、シリコン単結晶膜２３の側壁
及び上面を覆うゲッタリング用欠陥膜２６Ｂとゲート電
極２６Ｃを多結晶シリコン膜で同時に形成した例であ
り、製造工程が簡便となる。The present embodiment is an example in which the gettering defect film 26B covering the side wall and the upper surface of the silicon single crystal film 23 and the gate electrode 26C are simultaneously formed of a polycrystalline silicon film, and the manufacturing process is simplified.
【００３６】以上、各実施例について説明したが、本発
明はこれらに限定されるものではなく、構成の要旨に不
随する各種の材料変更及び構造変更等の設計変更が可能
である。Although the respective embodiments have been described above, the present invention is not limited to these, and various design changes such as a material change and a structure change can be made according to the gist of the configuration.
【００３７】[0037]
【発明の効果】以上の説明から明らかなように、本発明
によれば、ＳＯＩ素子の安定したゲッタリングを確実に
する効果を奏する。As is apparent from the above description, according to the present invention, the effect of ensuring stable gettering of the SOI element is exhibited.
【００３８】また、シリコン単結晶膜に負担をかけない
構造であるため、素子特性の劣化を抑制する効果があ
る。Further, since the structure is such that the silicon single crystal film is not burdened, it is effective in suppressing deterioration of device characteristics.
【００３９】さらに、請求項３記載の発明にあっては、
通常の平坦化工程と、ゲッタリング用欠陥膜の形成工程
が同一であるため、製造工程を簡便にする効果がある。Further, in the invention according to claim 3,
Since the normal planarization process and the gettering defect film formation process are the same, there is an effect that the manufacturing process is simplified.
【００４０】請求項２及び４記載の発明においては、ゲ
ッタリング欠陥膜がソース・ドレインの表面と確実に接
合するため、ゲッタリング効果を高めることができる。According to the second and fourth aspects of the invention, the gettering defect film is surely bonded to the surface of the source / drain, so that the gettering effect can be enhanced.
【図１】本発明の実施例１の製造工程を示す断面図。FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment of the present invention.
【図２】本発明の実施例１の製造工程を示す断面図。FIG. 2 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
【図３】本発明の実施例１の製造工程を示す断面図。FIG. 3 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
【図４】本発明の実施例１の製造工程を示す断面図。FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
【図５】本発明の実施例１の製造工程を示す断面図。FIG. 5 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
【図６】本発明の実施例１製造工程を示す断面図。FIG. 6 is a sectional view showing a manufacturing process according to the first embodiment of the present invention.
【図７】本発明の実施例２の製造工程を示す断面図。FIG. 7 is a cross-sectional view showing a manufacturing process of a second embodiment of the present invention.
【図８】本発明の実施例２の製造工程を示す断面図。FIG. 8 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.
【図９】本発明の実施例２の製造工程を示す断面図。FIG. 9 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.
【図１０】本発明の実施例２の製造工程を示す断面図。FIG. 10 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.
【図１１】本発明の実施例２の製造工程を示す断面図。FIG. 11 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.
【図１２】本発明の実施例３の断面図。FIG. 12 is a sectional view of a third embodiment of the present invention.
【図１３】ゲッタリング用欠陥膜のパターニング工程の
平面図。FIG. 13 is a plan view of a patterning process of a gettering defect film.
【図１４】ゲッタリング用欠陥膜のパターニング工程の
平面図。FIG. 14 is a plan view of a step of patterning a gettering defect film.
【図１５】本発明の実施例４の断面図。FIG. 15 is a sectional view of Embodiment 4 of the present invention.
【図１６】従来例の断面図。FIG. 16 is a sectional view of a conventional example.
１１…絶縁膜 １２…シリコン単結晶膜 １３…多結晶シリコン膜 １７Ａ…ソース電極 １７Ｂ…ドレイン電極 ２６Ａ…サイドウォール ２６Ｂ…ゲッタリング用欠陥膜 11 ... Insulating film 12 ... Silicon single crystal film 13 ... Polycrystalline silicon film 17A ... Source electrode 17B ... Drain electrode 26A ... Sidewall 26B ... Gettering defect film
Claims (4)
た半導体装置において、 前記シリコン単結晶膜外側面にゲッタリング用欠陥膜を
設けたことを特徴とする半導体装置。1. A semiconductor device formed on a silicon single crystal film on an insulating substrate, wherein a gettering defect film is provided on an outer surface of the silicon single crystal film.
ドレイン電極の一部を構成する請求項１記載の半導体装
置。2. The gettering defect film is a source film.
The semiconductor device according to claim 1, which constitutes a part of the drain electrode.
コン単結晶膜側面に形成された平坦化用サイドウォール
である請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the gettering defect film is a planarization sidewall formed on a side surface of the silicon single crystal film.
形成領域層を形成する工程と、 全面に多結晶シリコン膜を堆積させた後、パターニング
を行い前記素子形成領域層のソース・ドレイン領域表面
に多結晶シリコン膜を残す工程と、 前記ソース・ドレイン領域上の夫々の多結晶シリコン膜
に電極配線を接続させる工程を備えることを特徴とする
半導体装置の製造方法。4. A step of forming an element formation region layer made of silicon single crystal on an insulating substrate, and a step of depositing a polycrystalline silicon film over the entire surface and then patterning the source / drain region surface of the element formation region layer. 2. A method of manufacturing a semiconductor device, comprising: a step of leaving a polycrystalline silicon film on the substrate; and a step of connecting an electrode wiring to each of the polycrystalline silicon films on the source / drain regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27863192A JP3297937B2 (en) | 1992-10-16 | 1992-10-16 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27863192A JP3297937B2 (en) | 1992-10-16 | 1992-10-16 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06132292A true JPH06132292A (en) | 1994-05-13 |
| JP3297937B2 JP3297937B2 (en) | 2002-07-02 |
Family
ID=17599971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27863192A Expired - Fee Related JP3297937B2 (en) | 1992-10-16 | 1992-10-16 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3297937B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001326364A (en) * | 2000-03-10 | 2001-11-22 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of manufacturing the same |
| US6551866B1 (en) | 1998-11-27 | 2003-04-22 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor memory device |
| JP2006324688A (en) * | 1994-06-03 | 2006-11-30 | At & T Corp | Getter for multi-layer wafer and method for making the same |
| CN106165071A (en) * | 2014-04-18 | 2016-11-23 | 索尼公司 | Semiconductor devices for high-frequency switches, high-frequency switches, and high-frequency modules |
-
1992
- 1992-10-16 JP JP27863192A patent/JP3297937B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006324688A (en) * | 1994-06-03 | 2006-11-30 | At & T Corp | Getter for multi-layer wafer and method for making the same |
| US6551866B1 (en) | 1998-11-27 | 2003-04-22 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor memory device |
| JP2001326364A (en) * | 2000-03-10 | 2001-11-22 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of manufacturing the same |
| CN106165071A (en) * | 2014-04-18 | 2016-11-23 | 索尼公司 | Semiconductor devices for high-frequency switches, high-frequency switches, and high-frequency modules |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3297937B2 (en) | 2002-07-02 |
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