JPH06131159A - Zero flag detection circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a zero flag detection circuit which has a small amount of hardware and can operate at high speed. [Structure] Binary number A = a _n a _n-1 ...
_k ... a ₂ a ₁ (k is an arbitrary natural number satisfying 1 ≦ k ≦ n) and B
= B _n b _n-1 ... b _k ... b ₂ b ₁ When detecting the zero flag ZR indicating whether or not the addition result is zero, the detection of the zero flag from k bits to k + 1 bits that occurs during the detection of the zero flag The carry signal c _{k + 1} is generated by the logical sum of a _k and b _k .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zero flag detecting circuit for calculating a zero flag indicating whether or not the result of calculation by an adder / subtractor is zero.

[0002]

2. Description of the Related Art FIG. 7 shows a concept of a zero flag detection circuit in which carry propagation is parallelized by a conventional carry selection method. Each of the input data A and B consisting of n (= n _h + n _l ) bits of the zero flag detection circuit is divided into an upper n _h bit and a lower n _l bit to form an upper block and a lower block, respectively. In the figure, the lower zero flag detecting circuit 3 the carry signal c _l to zero flag z _l and the upper block of the lower block, zero flag when the carry signal from the lower block by a higher zero flag detecting circuit 2 is 0 z _ho and the carry c _ho to the higher order, and the zero flag z _hl when the carry signal from the lower block is 1 by the higher zero flag detection circuit 1 and the carry c _h l to the higher order Ask for.

Then, the zero flag z _h of the upper block is
According to the value of c _{l, one} of z _ho and z _hl is selected and obtained by the upper zero flag selector 5, and the logical product of z _h and z _l is ANDed.
Obtained by the gate 6 and output as the entire zero flag ZR. In addition, the carry c _h to the higher level from the upper n _h c _l
In accordance with the value of, the higher carry selector of 4 selects from c _ho and c _hl .

FIG. 8 is a truth table of a zero flag detection circuit for 1-bit addition at the k-th bit. z _k is a zero flag of the kth bit, and ZR = ∧ (i = 1 to n) z _k . Here, ∧ (i = 1 to n) _represents the logical product of all z _k whose subscript k is 1, ..., N.

When c _k = 0, z _k = NOT (XOR (a
_k , b _k )), and z _k = 1 when a _k = b _k = 0 or a _k = b _k = 1 and at that time, carry from the k-th bit to the k + 1-th bit c _{k + 1} output is a _k (or b
_k ). Here, XOR (a _k , b _k ) _represents an exclusive OR of a _k and b _k . Further, NOT (XOR (a _k ,
b _k )) is the negation of XOR (a _k , b _k ), and a _k , b _k
Is called the exclusive logical product of. The same meaning is used in the following description.

[0006] In addition, z _k = Given the time of 0, if z _k = 0 for some k, k <i ≦ n made any natural number i
The overall zero flag ZR is 0, whatever the value of z _i for. Therefore, when z _k = 0, the carry c _{k + 1} from the k-th bit to the k + 1-th bit may be a logical value of 0 or 1. For the above reason, the c _{k + 1} output in the case of a _k ≠ b _k where z _k = 0 is also set to a _k (or b _k ) as in the case where z _k = 1.

On the other hand, if c _k = 1 then z _k = XOR (a
_k , b _k ), and if a _k ≠ b _k, then z _k = 1 and c _{k + 1}
The output is 1. For the same reason in the case of c _k = 1 as in the case of c _k = 0, c _{k + 1} in the input condition a _k = b _{k where} z _k = 0
The output is 1.

According to the above idea, c _k input causes c
A circuit for determining the _{k + 1,} c _k = 0 if c _{k + 1} = a _k
(Or b _k ), if c _k = 1 then a 1-bit addition / zero flag detection circuit including a carry generation circuit that sets c _{k + 1} = 1 is configured.

By the conventional method for constructing the zero flag detection circuit described above, it is possible to construct a zero flag detection circuit which carries out carry propagation in parallel and carries the carry propagation with delay of the selector <logn> stages. Here, <x> represents the smallest integer of x or more, and is used in the same meaning in the following description.

[0010]

In the above-described conventional zero flag detection circuit, carry propagation of up to n bits occurs due to c _{K + 1} being determined depending on the value of c _k . Therefore, in the conventional zero flag detection circuit, carry propagation is parallelized by the carry selection method.
A carry propagation delay of gn> stage is required. In addition, since carry propagation is parallelized by carry selection, a zero flag detection circuit when the carry is 0 and a carry is required, and a selector for those outputs is required. It costs.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a zero flag detection circuit which is a circuit with a small amount of hardware and which can operate at high speed.

[0012]

Means for Solving the Problems The present invention, c _{k + 1} in the case of z _k = 0 with respect to the detection of the zero flag, regardless of the value of c _k inputs, take a 0,1 either logic value Paying attention to the fact that it does not matter, the zero flag detection circuit is characterized in that c _{k +} 1 is given by the logical sum of a _k and b _{k and} the carry propagation in the process of zero flag detection is at most 1 bit.

[0013]

In the present invention, the carry c _{k + 1} generated during the detection of the zero flag z _K in the zero flag detection circuit is given by the logical sum of a _K and b _k , and the delay required for carry propagation is independent of n. With a delay of one stage of the OR gate, the zero flag for 1-bit addition of all bits can be simultaneously obtained with a small delay time. In addition, it is possible to significantly reduce the amount of hardware compared to the conventional method.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on embodiments of concrete circuits. Needless to say, the embodiment is merely an example, and various modifications and improvements can be made without departing from the spirit of the present invention.

<Embodiment 1> FIG. 1 is a truth table of 1-bit addition of the k-th bit in the present invention. k is 1 ≦ k ≦
It is an arbitrary natural number of n. In the addition of the binary numbers A and B by the n-bit two's complement representation, the zero flag of the 1-bit addition of each digit is z ₁ = ... z _k-1 = 1 and z _k is 0 at the k-th bit. By taking the case as follows as an example, the validity of the zero flag detection in the present invention will be described.

The carry signal c _{k +} 1 in the case of z _k = 1 in FIG. 1 is the high-order signal when ak and b _K as the augends and addends and c _k as the carry are input to the full adder. It is the same as the carry signal to the bit. Therefore, from the first bit
The 1-bit addition zero flag detection circuit up to the ( _{k-1) th} bit outputs a zero flag (here, 1) having a correct logical value.

[0017] c in the k-th bit _k is the output of the zero flag detection circuit 1 bit addition of k-1 th bit, carry the same logic to the k-th bit from k-1 th bit in the adder It is a value. Therefore, the k-th bit 1-bit addition zero flag detection circuit outputs the correct logical value (0 in this case) of the k-th bit 1-bit addition zero flag as z _k .

The overall zero flag ZR is because zero flag all logical product of 1-bit addition of the bits, z _k = 0 if z _{k + 1,} ..., regardless of the transfer of the logical value of z _n ZR = 0
Becomes Therefore, if z _k = 0, the logical value of c _{K + 1} is 0,
Either value of 1 does not affect the value of ZR.

In the present invention, when _{k k} = 0 and z _k = 0, a
_In the case of _k ≠ b _k , c _{k + 1} = 1 and c _k = 1 and z
In the case of the _{k = 0 a k = b k} , and 1 c _{k + 1} in a _k = b _k = 0. According to the above method, c k _{+ 1} is given by a logical expression comprising a _{c k + 1 = a k ∨b} k, does not depend on the value of c _k. Here, the operator ∨ represents a logical sum.

Originally, the number of input bits of the arithmetic unit is arbitrary n bits, but in order to simplify the description, the zero flag detection circuit for 4-bit addition will be described below as an example. Figure 2
Shows the configuration of the zero flag detection circuit in the present invention. The zero flag detection circuit according to the present invention is a zero flag detection circuit 7 for 1-bit half addition of the first bit, a zero flag detection circuit 8 for 1-bit full addition from the second bit to the fourth bit, and the logic of its output. It consists of an AND gate 9 that takes the product.

FIG. 3 shows an example of the 1-bit half addition zero flag detection circuit 7 in FIG. 2 according to the present invention. The exclusive-AND gate 10 in the figure calculates the value of z ₁ . OR gate 11 in FIG, by taking the logical sum of a ₁ and b _1, and calculates a carry c2 to the second bit.

FIG. 4 shows a zero flag detection circuit for the 1-bit full addition of the k-th (natural number 2 ≦ k ≦ 4) bit in the present invention. The gate 10 of the exclusive logical product in the figure is c
The value of z _k when _k = 0 is calculated. In the figure, the gate 12 of the exclusive-OR gates the output of the exclusive-OR gate as z _k when c _k = 0, and the inversion of the output of the exclusive-AND gate when c _k = 1. Is output as z _k . In the figure, the OR gate 11 calculates the carry c _{k + 1} to the k + 1 th bit by taking the logical sum of a _k and b _k .

With the configuration of the zero flag detection circuit described above, the zero flag detection circuit is composed of four exclusive OR gates, three exclusive OR gates, an OR gate, and one 4-input AND gate. Can be configured, t _exnor is a delay of one stage of an input exclusionary AND gate, t _exnor is a delay of one stage of an input exclusive OR gate, t _or is a delay of an OR gate used for calculating _{ck + 1} , _and If the AND gate delay is t
_{When exnor} > t _or , the delay is t _exnor + t _exor + t _and ,
_{When exor} ≤t _or , the entire zero flag is detected with the delay of t _or + t _and .

<Embodiment 2> The number of input bits of the arithmetic unit is originally arbitrary n bits, but in order to simplify the description, a zero flag detection circuit for 4-bit addition will be described below as an example. FIG. 5 shows the configuration of the zero flag detection circuit in the 4-bit adder / subtractor. In the figure, the complement generator 13 is
When b _k and the control signal input S are input, b _k is outputted as an output signal bb _k when S = 0, and a value _obtained by logically inverting b _k is outputted as bb _k when S = 1. S is input to the carry input c ₁ of the zero flag detection circuit for the 1-bit full addition of the first bit.

An example of the 1-bit full addition zero flag detection circuit in FIG. 5 is the same as the 1-bit full addition zero flag detection circuit in FIG. FIG. 6 is a circuit example of the complement generator. b
By taking the exclusive OR of _k and the control circuit, bb _k is output and used as the input of the zero flag detection circuit for 1-bit addition.
Since the complement generator of each bit operates in parallel, the zero flag of the adder / subtractor is detected with a delay obtained by adding the delay of the complement zero generator to the delay of the addition zero flag generator.

[0026]

As described above, the logical product of all the zero flags of each bit obtained by the one-bit addition zero flag detection circuit is used to obtain the n-bit two's complement binary addition. In the zero flag detection circuit for detecting the zero flag, the conventional technique requires a huge amount of hardware because the carry signal propagates through the m-stage selector and adopts the carry selection method. On the other hand, according to the present invention, under the same conditions described above, the propagation of the carry signal is at most 1 bit, and the zero flags for all 1-bit addition of n bits are obtained in parallel, so that the zero flag can be detected at high speed. Moreover, the amount of hardware required for detecting the zero flag is significantly reduced. In a pipeline computer or the like, the operation of the pipeline in the next stage may be controlled by the value of the zero flag of the adder, and the present invention can determine the zero flag earlier than the conventional zero flag detection circuit. Therefore, the operating condition of the pipeline of the next stage can be set early, and the pipeline cycle can be shortened. Further, since the zero flag detection circuit is installed in parallel with the adder, a circuit configuration with a small amount of hardware is essential. According to the present invention, the zero flag detection circuit can be configured with a significantly small amount of hardware as compared with the conventional technique.

[Brief description of drawings]

FIG. 1 shows a truth table of a 1-bit addition zero flag detection circuit according to the present invention.

FIG. 2 shows a configuration of a zero flag detection circuit of an adder according to the present invention.

FIG. 3 illustrates a 1-bit half addition zero flag detection circuit according to the present invention.

FIG. 4 shows a zero flag detection circuit for 1-bit full addition according to the present invention.

FIG. 5 shows a configuration of a zero flag detection circuit of an adder / subtractor according to the present invention.

FIG. 6 shows a circuit example of a complement generator according to the present invention.

FIG. 7 shows the concept of a zero flag detection circuit according to a conventional carry selection method.

FIG. 8 shows a truth table of a conventional one-bit addition zero flag detection circuit.

[Explanation of symbols]

 1 Upper Zero Flag Detection Circuit 2 Upper Zero Flag Detection Circuit 3 Lower Zero Flag Detection Circuit 4 Upper Carry Selector 5 Upper Zero Flag Selector 6 AND Gate 7 1 Bit Half Addition Zero Flag Detection Circuit 8 1 Bit Full Addition Zero Flag detection circuit 9 AND gate 10 Exclusive logical product gate 11 OR gate 12 Exclusive logical sum gate 13 Complement generator

Claims (2)

[Claims] 1. A binary number represented by a two's complement representation of n (n is an arbitrary natural number) A = a _n a _n-1 ... A _k ... A ₂ a ₁ (k is an arbitrary natural number satisfying 1 ≦ k ≦ n). ) And B = b _n b _n-1 ... b _k
When inputting b ₂ b ₁ and adding the two numbers, 1 is output as the zero flag ZR when the operation result is zero, and 0 is output as the zero flag ZR when the operation result is non-zero. Zero flag detection In the circuit, a zero flag detection circuit is characterized in that a carry signal c _{k + 1} for detecting a zero flag from k bits to k + 1 bits generated during the detection of a zero flag is generated by a logical sum of a _k and b _k . 2. A binary number A = a _n a _n-1 ... a _k ... a ₂ a ₁ (k is an arbitrary natural number satisfying 1 ≦ k ≦ n) in which n (n is an arbitrary natural number) bit is represented by two's complement. ) And B = b _n b _n-1 ... b _k
... B in which each bit of A and B is inverted in b ₂ b ₁ .
When B is an input and the carry c _k to the least significant bit is 1, and AB is subtracted, a carry signal c _{k +} for detecting a zero flag from k bits to k + 1 generated during the zero flag detection. A zero flag detection circuit, wherein 1 is generated by a logical sum of a _k and b _k .