JPH061306B2 - Liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix type liquid crystal display device having an inversion refresh function suitable for using a liquid crystal cell as a memory element. BACKGROUND OF THE INVENTION In recent years, an active matrix type liquid crystal display device has been attracting attention as a large capacity display device in terms of low power consumption, flatness and miniaturization, and a display data reading function and a display data refresh function are added to it. However, some even use the display device itself as a RAM. An example of such an apparatus is disclosed in Japanese Patent Laid-Open No. 59-24892. However, in this device, a DC voltage is applied to the liquid crystal substance. As is well known, the liquid crystal substance is electrolyzed by a direct current electric field, which significantly shortens the life of the liquid crystal. Therefore, the above device has a practical problem in terms of life. [Object of the Invention] An object of the present invention is to prolong the life of an active matrix type liquid crystal display device having a data reading and refreshing function. SUMMARY OF THE INVENTION The present invention, in an active matrix type liquid crystal device having a data reading and refresh function, reads the voltage currently applied to the liquid crystal display pixel at the time of the refresh operation, and after inverting and amplifying the voltage, the pixel is read again. It is characterized in that the voltage applied to the liquid crystal pixels is made alternating by applying the voltage. [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIG. The novelty of the present invention lies in the refresh operation of the liquid crystal pixel, and the normal data writing and displaying operations are the same as those of the known liquid crystal display device, and therefore the description thereof is omitted. In FIG. 1, reference numeral 1 denotes a display pixel defined by a display electrode, which is arranged in a matrix and constitutes a display section (not shown). Each display pixel 1 is composed of a MOS transistor 2 as a selection switch forming a transistor / capacitor array, a capacitor 3, and a liquid crystal element 4 connected to each capacitor 3, and each is a memory cell. A scan electrode 1 for commonly connecting the gates of the MOS transistors 2 in each row and a MOS in each column
The signal electrodes m commonly connecting the drains of the transistors are insulated and orthogonally arranged at each intersection. Each signal electrode m is connected to the refresh circuit 5. The refresh circuit 5 has two inputs, first and second comparators 6 and 7, first and second dummy cells 8 and 9, first and second precharge voltage generation circuits 10 and 11, and comparator outputs. A three-value conversion output circuit 12 that is controlled to generate a predetermined voltage and M that selectively controls the flow of each signal.
It consists of an OS transistor. The first input of the first comparator 6 connects the dummy line n _a, connects the first Damiseru 8 by MOS transistor 13 and the capacitor 14 to the dummy line n _a. Similarly, the dummy line n _b is connected to the 1 input of the second comparator 7, and the second dummy cell 9 including the MOS transistor 15 and the capacitor 16 is connected to the dummy line n _b . The gates of the MOS transistors of the dummy cells in each column are commonly connected to the control line b. Reference numeral 10 is a first precharge voltage generator for writing the first reference voltage in the first dummy cell 8, and 11 is a second precharge voltage generation for writing the second reference voltage in the second dummy cell 9. It is a vessel. Stray capacitance C _A of the stray capacitance C _'A1 dummy line n _a scanning signal line m
Set to be almost equal to. Similarly, the stray capacitance C ′ _A2 of the dummy line n _b is set to be substantially equal to the stray capacitance C _A. For the refresh operation, it is sufficient to newly write the read information, but even if the charge is stored in the capacitor 3 at the "1" level, the voltage decreases with time due to leakage of the MOS transistor 2 or the like. Therefore, even if the read voltage is lower than the first written voltage,
When newly writing, unless the initial voltage is written, the display operation or the information storage operation cannot be performed sufficiently. Further, the liquid crystal element 4 has a defect that the life is shortened by continuously applying a DC electric field. The present invention provides three types of voltage applied to the capacitor 3 during the refresh operation, that is, "1",
The level is set to "0" or "-1". As a result, if the electric field applied to the liquid crystal element 4 is set to a certain potential in the common electrode of the liquid crystal element 4, an alternating AC electric field can be applied every refresh operation, and the life of the liquid crystal element 4 can be extended. Next, the refresh operation of the embodiment shown in FIG. 1 will be described according to the timing chart shown in FIG. First, the first precharge voltage generator 10 charges the capacitor 14 of the first dummy cell 8 to an intermediate potential of level "1". Similarly, the second precharge voltage generator 11 causes the capacitor 16 of the second dummy cell 9 to change to the level "-".
It is charged to an intermediate potential of 1 ". At the first time t ₁ of the refresh operation, the control line a becomes H level, and the switching elements 17, 18, 19 are closed together with the control line c which was previously at H level. And the dummy line n _a connected to the scanning signal line m and the dummy cells 8 and 9,
n _b is electrically connected to each other, and the scanning signal line m and the two dummy lines n _a and n _b have the same potential. At time t ₂ , the switching elements 17 and 18 are opened, and the scanning signal line m and the two dummy lines n _a and n _b are electrically disconnected. In still a time t _3, the scanning electrodes l ₁ and b connected to the gate of the MOS transistor 2 and switching-element 13, 15 in the dummy cell 8,9 of the display pixel 1 becomes H level, respectively M
The OS transistor 2 and the switching elements 13 and 15 are closed, and the potentials precharged by the capacitors 14 and 16 are dummy lines n _a and n _b , the stray capacitance C ′ _A1 and the capacitor 14, the stray capacitance C ′ _A2 and the capacitor 16 respectively. Is divided by and. Similarly, also for the scanning signal line m, the potential charged in the capacitor 3 is divided by the capacitor 3 and the stray capacitance C _A. Next, the outputs of the first and second comparators 6 and 7 are classified into the following three cases depending on the value of the voltage appearing on the scanning signal line m. It is shown in FIG. That is, in the first case, if the capacitor 3 is charged to the potential of the logic level "1", a positive potential appears on the scanning signal line m, and the input signal lines e and f in the first and comparator 6 are shown.
The voltage magnitude relationship is e> f, the output g is at H level,
The magnitude relation between the voltages of the input signal lines h and i in the second comparator 7 is h ≦ i, and the output j becomes L level. Similarly, in the second case, the capacitor 3 has the logical level "0".
If it is at the potential of, the output g of the first comparator 6 is L,
The output j of the second comparator 7 becomes L. Furthermore the third
In this case, if the capacitor 3 is at the potential of the logic level "-1", the output g of the first comparator 6 is the L level, the second
The output j of the comparator 7 becomes H level. Next, the ternary conversion output circuit 12 that receives the outputs of these first and second comparators has a logic level "-1" in the first and second cases and a logic level "1" in the second case. 0 ", in the third case, logic level" 1 "
The output of the three-value conversion output circuit 12 is the timing chart of FIG. 2 and the switching element 19 opens and the switching element 20 closes at the time t ₅ , so that the scanning signal electrode m is output. Therefore, until the time t ₆ after the MOS transistor 2 is closed, the capacitor 3 is charged with the output potential of the ternary conversion output circuit 12, and rewriting, that is, refresh operation is performed. As described above, one refresh operation is completed, but in the next cycle, the refresh operation is performed for the pixels selected by the scan electrode l _{2. In} this way, pixels are selected one after another and the refresh operation is performed. When one refresh operation described above is completed,
The potential charged in the capacitor 3 is positive and negative, except for the case of the logic level "0". Therefore, in this embodiment, since the electric field applied to the liquid crystal pixel is reversed during the refresh operation, the storage capacity in the display pixel can be maintained and the life of the display pixel can be extended. [Effects of the Invention] According to the present invention, the electric field applied to the liquid crystal pixels can be alternated by the refreshing operation, so that the life of the device can be extended.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a timing chart, and FIG. 3 is an explanatory diagram showing the input / output relation of the ternary conversion output circuit in FIG. 5 ... Refresh circuit 6, 7 ... Comparator 8, 9 ... Dummy cell 10, 11 ... Precharge circuit 12 ... Tri-level conversion output circuit 13, 15, 17, 18, 19, 20 ... Switching element 3, 14, 16 ... Capacitor C _A , _C'A1 , _C'A2 ... stray capacitance

Claims (1)

Claim: What is claimed is: 1. A liquid crystal display device comprising memory cells each comprising a liquid crystal element and a transistor / capacitor array arranged in a matrix corresponding to pixels, wherein a transistor and a capacitor are provided for each column of the transistor / capacitor array. Each of the first and second dummy cells, the capacitor in each dummy cell and the transistor /
First and second comparators for reading out and comparing the charge amounts of the capacitors of the selected row in the capacitor array, and charges of the selected capacitors according to the output values of the first and second comparators. A three-value conversion output circuit for inverting or reversing the polarity of the three-value conversion output circuit, and a plurality of switching elements for performing rewriting for applying the output voltage of the three-value conversion output circuit to the capacitors of the selected row, A liquid crystal display device having a refreshable memory display function.