JPH0612529B2 - Address translator test method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an address translation device that translates a logical address into a real address, and more particularly to a test system for the address translation buffer.

(Prior Art) A system that supports virtual memory for converting a logical address to a real address includes an address conversion device. The address translation device normally performs the address translation based on the address translation table prepared by the operating system, and stores the translation information so that the address translation can be executed at high speed. It has a buffer. Since address translation is usually accompanied by paging, such translation is conversion from a logical page to a real page.

There is a method in which the test of the address translation device, especially the address translation buffer is performed by a test program. The test program system prepares a test address translation table group and registers and confirms data in the address translation buffer based on the table group.

The address translation buffer consists of multiple entries and is often indexed by the set associative method. In this case, the address translation buffer is indexed by a part of the logical address, and the rest of the logical address is registered in the address translation buffer. Usually, the former is called a set address and the latter is called a key address. That is, the address translation buffer is indexed by the set address and compared with the key address. As a result of the comparison, when there is the matching entry, the conversion information from the indexed logical address to the real address is registered and the real address is obtained. As a result of the comparison, in the case of the above disagreement, the conversion information is not registered.

A registration address conversion table is prepared for the above address conversion buffers. In order to register the translation information in all the entries of the address translation buffer, a table that uses all the set addresses in all cases is required. It must be unique for each buffer entry.

Assuming that the key address occupies the upper part of the logical address, the registration address conversion table that satisfies the above condition becomes huge.

Further, the converted real address also exists in the same page to reduce the memory area.

(Problems to be solved by the invention) Therefore, the key address is almost a fixed value, and it is impossible to detect these when the address translation buffer is mistakenly indexed or the entries interfere. is there.

The object of the present invention is to register the translation information in the address translation buffer using the test address translation table, confirm the registered contents using the test address translation table, and circulate the real page group in the logical address space. The above problem is eliminated by providing the address translation device test method configured so that the translation information can be provided even when the address translation buffer is erroneously indexed or the entries interfere. .

(Means for Solving Problems) The address translator testing method according to the present invention comprises an address translation table, an address translation means, an address translation buffer, and an address reading means, and includes the address translation table The test address translation table is used to register to the address translation buffer, the second test address translation table included in the address translation table is used for confirmation, and the test address translation table is a logical address. It is configured so that a real page group can be patrolled in the space and made to correspond.

The address conversion table is 2 ⁿ -1 (n2: positive integer)
It includes a first test address translation table for associating the real page group with the above, and a second test address translation table created by rewriting the contents of the first test address translation table.

The address conversion means is based on the address conversion table,
This is for converting a logical page address in the logical address space into a page address in the real address space.

The address translation buffer is for registering address translation information including the real page address.

The address reading means is for indexing the address conversion buffer to check whether it is registered or not, and for reading the real page address.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the outline of an embodiment of the address translator testing method according to the present invention. FIG. 2 is an explanatory diagram showing the format of the logical address. FIG. 3 is an explanatory diagram showing formats of the segment table and the page table. FIG. 4 is a block diagram showing the address conversion process. FIG. 5 is an explanatory diagram showing the registration format of the address translation buffer. FIG. 6 is an explanatory diagram showing an access area. FIG. 7 is a flow chart showing registration in the address translation buffer. FIG. 8 is a flow chart showing the registration and confirmation of the address translation buffer.

FIG. 9 is a flow chart showing an analysis at the time of abnormal termination in registration and confirmation.

In FIG. 1, 1 is a logical address register, 2 is a real address register, 3 is an address conversion buffer, 4 is a comparator, 5 is a segment table area, 6 is a registration page table, and 7 is a confirmation page table. In FIG. 4, 41 is a control register, 42 is a segment table area, 43 is a page table, and 44 and 45 are adders. In FIG. 6, 61 to 63 are access pages of the registration page table area 6 and 64 is an access page of the confirmation page table area 7.

In FIG. 1, both logical addresses and execution addresses are described in 4-byte width.
Up to are valid bits, and the lowest bit is a byte boundary. The format of the logical address is divided into a segment S, a page P, and an in-page address L as shown in FIG. 2. The segment S is bits 8 to 11 and the page P is bit 12.
.About.19, in-page address L is set to bits 20 to 31, and bits 0 to 7 are fixed to 0. Therefore, one page is 4 kilobytes.

Next, the formats of the entries in the segment table and the page table are shown in FIGS. 3 (a) and 3 (b), respectively. Fig. 3
The entry of the segment table of (a) is 4 bytes wide, and bit 0 is a V bit indicating validity and is valid when the logical value is 1. Bits 8 to 31 indicate the start address of the page table, and bits 1 to 7 are fixed at 0.
The entry of the page table in FIG. 3 (b) has a width of 4 bytes, and bit 0 is a V bit indicating validity, and is valid when the logical value is 1. Bits 8 to 19 indicate the real page address, and Bits 1 to 7 are fixed at 0, but Bit 20
~ 31 is optional. The real page addresses of bits 8 to 19 are the registration information of the address conversion buffer 3 shown in FIG.

When registering in the address conversion buffer 3, the registration information is registered through the address conversion process shown in FIG. Referring to FIG. 4, the contents of the control register 41 storing the start address of the segment table and four times the segment field S are added by the adder 44, and the index entry is read from the segment table area 42. . Therefore, it is confirmed that the V bit is 1, and the top address of the page table is obtained. The start address of the page table and four times the page field P are added by the adder 45, the index entry is read from the page table area 43, it is confirmed that the V bit is 1, and the actual page address is obtained.

Returning to FIG. 1, the logical address is set in the logical address register 1. Next, the address translation buffer 3 is indexed and the presence or absence of registration is checked by the comparator 4. Bits 14 to 19 of the logical address are index addresses of the address conversion buffer 3, that is, set addresses, and are sent out on the signal line 8. Bits 8 to 13 are key addresses, which are sent out on the signal line 9 and serve as comparison addresses at the time of indexing and registration addresses at the time of registration.

If the registration is confirmed, it is called a hit, and if the registration is not confirmed, it is called a miss. In the case of mishisto, the real page address is obtained by the address conversion process and the signal line 10
The real address is set in the real address register 2 together with the above-mentioned in-page address, and the real page address is sent from the address translation buffer 3 and used for registration.

In this embodiment, the capacity of the address translation buffer is 64 entries, and the entries have the format shown in FIG. As is clear from FIG. 5, each entry has a V bit indicating that the registered contents are valid, a logical address bit (bit 8 to 13) which is a key address, and a real page address bit (bit 8 to 19). It consists of and.

Next, the segment table area, page table area, and access area for testing the address translation buffer 3 and the comparator 4 will be described. First, the test segment value is set to S _1, and the entry S ₁ is secured in the segment table 5. Next, a registration page table area 6 for storing the first test address conversion table defined in the claims and a confirmation page table area 7 for storing the second test address conversion table 2. And prepare four real pages as shown in FIG. That is, registration page table area 6
Pages 61 to 63 are circulated and allocated, and all entry pages 64 are allocated to the confirmation page table area 7. Page 61 is P for the four real pages shown in FIG.
₀ , page 62 is P ₁ , page 63 is P ₂ , page 64 is m ₀
Is the real page address. Page 61 to Page 64 of 4
At least 64 units of 4-byte data are prepared for one page from the beginning of the page. The logical address at the time of registration / confirmation in 64 entries of the address translation buffer 3 is a
_{From 0} to a ₆₃ , the first 1 byte of ai (i = 0 to 63) is “00” in hexadecimal notation. xi, yi, zi, b
i is 4-byte data, and the first 1 byte is hexadecimal notation "OF", "OE", "OD", "FO".
", And the remaining 3 bytes are the same as ai.

First, registration of translation information in the address translation buffer 3 will be described with reference to FIG. The _first address of the registration page table area 6 is stored in the entry S ₁ of the segment table area 5, the tables are linked, and the contents of the address conversion buffer 3 are all cleared. Next, the logical address is initialized and the initial value is set to a ₀ . At a ₀ , the segment field S ₁ and the page field are 0 and the in-page address is 0, and the memory access is performed by the logical address ai (i = 0 to 63). In response to this memory access, the address translation buffer 3 becomes a mishit, and it is confirmed that the registration is performed and the read data matches with ai. If they do not match, an error message is output and the processing ends abnormally due to a defective clearing of the address translation buffer 3 or a defective address translation process. If a match is confirmed, the logical address is updated, incrementing the page field by one and the in-page address by four. After that, if the above operation is repeated 64 times, the registration of all entries is completed.

Next, registration and confirmation of the address translation information in the address translation buffer 3 will be described with reference to FIGS. 8 and 9. The start address of the confirmation page table area 7 is stored in the entry S ₁ of the segment table area 5, the tables are linked, the logical address is initialized, and the initial value is set to a.
_Set to ₀ .

Confirmation can be done in the same order as registration or in reverse order, but for the sake of simplicity, use the same order. In a ₀ , the segment field S _{1 is set} , the page field is set to 0, and the in-page address is set to 0, and memory access is performed at the logical address ai (i = 0 to 63). Next, it is checked whether the read data matches the expected value ai. If it is correctly registered in the address translation buffer 3 and is hit by the index, the read data is ai. After confirming the match, the logical address is updated, the page field is incremented by 1, and the in-page address is incremented by 4. After that, when the above operation is repeated 64 times, the registration / confirmation of all entries is completed. If a discrepancy is found, the process proceeds to the analysis routine of FIG.

If the registration information is not registered in the address translation buffer 3, the segment table area 5 and the confirmation page table area 7 are referred to, and bi is read from page 64 in FIG. Therefore, by reading out bi, it becomes clear that the coincidence output cannot be obtained because of the unregistered state or the failure of the comparator 4. Display this as an unregistered error message.

Next, even if the contents of the entry are disturbed or misindexed due to interference from other entries of the address translation buffer 3, the key address is fixed in the registered information and is reflected in the hit / miss hit. Without it, the truth cannot be discriminated by whether or not a hit has occurred. For example, with respect to the erroneous index, a certain address may be registered twice due to a failure of the set address on the signal line 8.
However, since the real page address of the registration page table 6 is walted as P ₀ , P ₁ , P ₂ at the time of registration, xi, y is read when the page other than the expected page is read.
It is possible to distinguish by i or zi. If none of these apply, it is processed as an erroneous access.

Finally, the false index of entries or the interference of entries will be described. As the contents registered in the address translation buffer 3, a waltz pattern having a cycle of 3 or 2 ⁿ -1 (n3: a positive integer) is given in order of entry. The address translation buffer 3 is usually a hardware configuration including a memory device. It is supposed that the entry α is to be indexed, but the entry β is indexed or the entry β is affected.

It is assumed that a memory element normally has a power of 2 and employs a cell arrangement in a matrix configuration. in this case,
Depending on the method of address decoding, the distance between the entry α and the entry β is 3 or 2 ⁿ −1 (n
It is rare that the period is 3) or a multiple thereof. Therefore, walting of 3 or 2 ⁿ -1 (n3) is not perfect, but is sufficiently strong. It is considered that the larger the waltz cycle is, the stronger the waltz cycle is, but in this embodiment, 3 is adopted.

(Effect of the Invention) As described above, according to the present invention, the translation information is registered in the address translation buffer using the test address translation table, the registered contents are confirmed using the test address translation table, and the logical address space is stored. It is possible to easily detect an erroneous index in the address translation buffer and interference of entries by circulating the real page groups and making them correspond.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the address translator testing method according to the present invention. FIG. 2 is an explanatory diagram showing the format of the logical address. FIG. 3 is an explanatory diagram showing formats of the segment table and the page table. FIG. 4 is a block diagram showing the address conversion process. FIG. 5 is an explanatory diagram showing the registration format of the address translation buffer. FIG. 6 is an explanatory diagram showing an access area. FIG. 7 is a flow chart showing registration of the address translation buffer. FIG. 8 is a flow chart showing the registration and confirmation of the address translation buffer. FIG. 9 is a flow chart showing an analysis at the time of abnormal termination in registration and confirmation. 1 ... Logical address register 2 ... Real address register 3 ... Address conversion buffer, 4 ... Comparator 5, 42 ... Segment table area 6, 7, 43 ... Page table area 41 ... Control register, 44, 45 …… Adder 61 ～ 64 …… Access page, 8 ～ 10 …… Signal line

Claims (1)

[Claims] 1. A first test address conversion table for associating 2 ⁿ -1 (n2: positive integer) real page groups, and a first test address conversion table created by rewriting the contents of the first test address conversion table. 2, an address conversion table including a test address conversion table, address conversion means for converting a logical page address of a logical address space into a real page address of a real address space based on the address conversion table, and the real page address. An address translation buffer for registering address translation information including the address translation information, and address reading means for indexing the address translation buffer to check whether the address is registered and reading the real page address. Using the test address translation table No. 1 for registration to the address translation buffer, the second address Confirmation is performed by using a test address conversion table, and the test address conversion table is configured so that the actual page group can be circulated and corresponded to the logical address space. method.