JPH06124070A - Liquid crystal drive - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to improvement of a liquid crystal driving device,
Type, while maintaining the writing function to the liquid crystal display panel,
It is an object of the present invention to devise the output timing control of the added voltage value related to the image data of the lower bit group to reduce the sampling capacitance and the amplification element, and to reduce the circuit size. [Configuration] A switching control signal based on the image data DIN of the upper bit group and the image data DIN of the lower bit group
Switching control means 11 that outputs SWn [n = 1, 2, 3 ... N] and a plurality of reference voltages VM [M = 1, 2, 3 ... M] are selected and combined in time division based on the switching control signal SWn. Drive output means 1 for outputting the liquid crystal drive voltage VX
2 and at least a control means 13 for controlling the input / output of the switching control means 11 and the drive output means 12, and the control means 13 is in the upper bit group during the transfer or holding period of the image data DIN of the lower bit group. Of the first voltage VUi relating to the image data DIN of
The output voltage of the combined voltage VUi + VLi with the second voltage VLi is included in the configuration.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Conventional Technology (FIGS. 11 to 13) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 2) Operation Embodiment (1) First Description of Embodiment (FIGS. 3 to 7) (2) Description of Second Embodiment (FIGS. 8 to 10)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device and a control method, more specifically, a TFT.
The present invention relates to circuit miniaturization of a device for driving a (Thin Film Transistor) type liquid crystal display device.

In recent years, a liquid crystal display has been used as an image display device which is thin and lightweight and operates with low power consumption. In addition, with the improvement of the display quality of liquid crystal displays, it has reached the point of replacing conventional CRT (cathode-ray tube) devices with active matrix type LCD (Liquid Crystal Display) among flat panel type liquid crystal displays. ) Equipment is the mainstream.

According to this, the sample hold output circuit for outputting the liquid crystal drive voltage has three data lines per data line.
Each of the sampling capacitors, two operational amplifiers, and four analog switches are used to charge the sampling voltage with the reference voltage related to the image data of the upper bit group, and the sampling voltage of the reference voltage related to the image data of the lower bit group. The added voltage value is sent to the data line based on the charging process.

Therefore, multi-gradation can be realized without significantly increasing the number of reference voltages and the number of analog switches. However, the sampling capacity for charging the added voltage value and the sampling capacity are sent to the data line. The operational amplifier prevents the circuit of the liquid crystal drive device from becoming smaller.
While maintaining the writing function to the T-type liquid crystal display panel,
There is a demand for an apparatus capable of reducing the sampling capacity and the amplification element by devising the output timing control of the added voltage value related to the image data of the upper and lower bit groups, and reducing the circuit thereof.

[0006]

11 to 13 are explanatory views of a conventional example, and FIG. 11 (a) is a configuration diagram of a multi-tone liquid crystal driving device according to the conventional example. Further, FIG. 11B is an equivalent circuit diagram of the liquid crystal capacitance of the unit pixel of the liquid crystal display panel, and FIG. 11C is a waveform diagram of the write voltage.

For example, a multi-tone liquid crystal drive device as shown in the "multi-tone active matrix liquid crystal drive circuit" previously filed by the present inventors (Japanese Patent Application No. 4-111000) is shown in FIG. In a), it comprises a switching controller 1, a reference voltage generator 2, a voltage selector 3, a sample hold output circuit 4 and a control circuit 5.

In the multi-gradation active matrix liquid crystal drive circuit, the digital circuit scale increases as the number of gradations increases.
The digital image data from the video signal source is divided into a plurality of pieces in order to solve the increase in the chip area due to the increase in the number of analog switches, the increase in the number of reference voltage signal lines supplied from outside the data driver, and the increase in the number of data signal lines. Then, the image data is transferred to a data driver, digital / analog conversion is performed to convert each image data into an analog voltage, the result is stored in a sampling capacitor, and the respective voltages are combined at the final stage.

That is, the function of the device is converted into a plurality of switching control signals SW by the switching control section 1 based on the image data of the upper bit group and the image data of the lower bit group from the image signal source, which are converted into a plurality of switching control signals SW. It is output to the voltage selection unit 3. In the voltage selection unit 3, the reference voltage generated by the reference voltage generation unit 2 based on the plurality of switching control signals SW is the sample hold output circuit 4.
Is output selectively.

As a result, the sample hold output circuit 4
Then, the reference voltage is charged and discharged based on the output control of the control circuit 5, and the reference voltage is written in the data line as the liquid crystal drive voltage VXi in the TFT type liquid crystal display panel.

In FIG. 11B, the resistance value RD of the equivalent circuit of the data line of the liquid crystal display panel is O of the TFT.
It is sufficiently smaller than the on-resistance r during N operation. Also, FIG.
In the waveform diagram of the write voltage in (c), the voltage waveform VD on the data line has a steep (period TA) waveform with respect to the rectangular liquid crystal drive voltage VXi due to the low resistance value of the data line and the wiring capacitance CD. stand up. Also, the liquid crystal capacitance C
The liquid crystal drive voltage VXi applied to L reaches a specified value during the period TA + TB. Here, the period TB depends on the charging characteristics of the on-resistance r of the TFT and the liquid crystal capacitance CL.

[0012]

By the way, the sample-hold output circuit 4 for outputting the liquid crystal drive voltage VXi of the conventional example.
According to FIG. 12, as shown in FIG. 12, three sampling capacitors CA1, CB1, CC1, and
Composed of four operational amplifiers OP11, OP12 and four analog switches SA1, SB1, SC1, SD1 for charging the sampling capacitor CA1 with the reference voltage relating to the image data DIN of the upper bit group and the image data DIN of the lower bit group. The added voltage value is sent to the data line based on the process of charging the sampling capacitor CB1 with the reference voltage according to the above.

For this reason, there is a problem that the sampling capacitor CC1 for charging the added voltage value and the operational amplifier OP21 as an amplifying element for sending the added voltage value to the data line hinder the downsizing of the circuit of the liquid crystal driving device.

For example, FIG. 12 is a configuration diagram of a main part of a liquid crystal drive device according to a conventional example, which is a configuration example of a data driver in which digital image data DIN is divided into upper bits and lower bits. The case of 4 [bits] is shown.

In FIG. 12, the switching control unit 1 has a memory MU1 for holding image data D3 and D2 of upper bits.
1 to MU14, memories MU11 to MU14 for holding lower bit image data D1 and D0, switching circuit MPX, memory 61
A to 64A and decoding circuits 81A to 84A.

Further, the reference voltage generator 2 has the reference voltages V1 to V1.
DC power source for generating V4, voltage selector 3 is selector 91A
It consists of ~ 94A. The sample hold output circuit 4 has three sampling capacitors CA1 and C1 for each data line.
B1, CC1, two operational amplifiers OP11, OP12 and 4
Analog switches SA1, SB1, SC1, SD1
Consists of.

Therefore, in the case of 4 × 4 pixels and N = 4 [bits], the four sampling capacitors CC1 to CC4 and the four operational amplifiers OP21 to OP24 impede the circuit reduction of the liquid crystal drive device. .

Further, in the operation timing chart of the liquid crystal drive device according to the conventional example shown in FIG. 13, first, the upper bit data in the memories MU11 and MU12 are transferred and output in series via the switching circuit MPX and written. Signal TW1 ~
The data is sequentially written in the memories 61A to 64A based on TW4.

Further, switching control signals (not shown) are sequentially output from the decoding circuits 81A to 84A to the selectors 91A to 94A corresponding to the write data value, and the analog switches in the selectors 91A to 94A corresponding to the data value are output. Is selected, one of the reference voltages V1 to V3 or V4 is selected from the reference voltages V1 to V4, and the standby state is entered so that the sampling capacitors CA1 to CB1 are charged.

After waiting for the reference voltage corresponding to the upper bit data in the memories MU13 and MU14 to be selected, the analog switches SA1 to SA4 are turned on by the activation of the output control signal T4 and selected. The reference voltage is charged in the sampling capacitors CA1 to CA4.

Similarly, the lower bit data in the memories ML11 and ML12 are serially transferred and output via the switching circuit MPX, and the memories 61A to 61A to TW1 to TW4 based on the write signals TW1 to TW4.
It is sequentially written in 64A.

Further, switching control signals (not shown) are sequentially output from the decoding circuits 81A to 84A to the selectors 91A to 94A corresponding to the write data value, and the analog switches in the selectors 91A to 94A corresponding to the data value are output. Is selected, one reference voltage V1 to V4 is selected from the reference voltages V1 to V4, and the sampling capacitance C
It is in a standby state so as to be charged in B1 to CB4.

After waiting for the reference voltage corresponding to the lower bit data in the memories ML13 and ML14 to be selected, the analog switches SB1 to SB4 are turned on by the activation of the output control signal T5 and selected. The reference voltage is charged in the sampling capacitors CA1 to CB4.

After that, before the voltage for the data of the next line is generated, the analog switches SC1 to SC4 are turned on based on the output control signal T6 generated by the control circuit 5.
The sampling capacitors CA1 and CB1, CA2 and CB2, CA3 and CB3, and CA4 and CB4 are connected in parallel to perform analog addition. Next, the summed value is based on the output control signal T7 which rises in synchronization with the output control signal T6, and the third sampling capacitors CC1 to CC1.
Each is transferred to CC4.

This value is (CAN × VA + CBN × VB)
/ (CAN + CBN). However, N = 1 to 4, VA is a voltage accumulated in the sampling capacitor CAN, and VB is a voltage accumulated in the sampling capacitor CBN. The video signal stored in the third sampling capacitor CCN is sent to the data lines X1 to X4 as the liquid crystal drive voltages VX1 to VX4 via the third operational amplifier OP2N.

As a result, the image data D of the upper bit group
According to the method of transmitting the added voltage value of the reference voltage related to IN and the reference voltage related to the image data DIN of the lower bit group to the data line, the number of reference voltages and the number of analog switches are not significantly increased, and Key can be realized.

However, even in the case of 4 × 4 pixels and N = 4 [bits], eight sampling capacitors CA1 to CA4 and CB1 to CB4 constituting the sample hold output circuit,
In addition to four operational amplifiers OP11 to OP14, four sampling capacitors CC1 to CC4 and four operational amplifiers OP21 to OP21.
OPm is required, and in m × L pixels, the m sampling capacitors CCm that temporarily charge the added voltage value and the m operational amplifiers OP2m that send it to the data line are the chip area of the liquid crystal drive device. Occupies a large amount, hindering the reduction in size, which is a major obstacle to downsizing and cost reduction of the liquid crystal drive device.

The present invention was created in view of the problems of the conventional example, and the added voltage value relating to the image data of the upper and lower bit groups while maintaining the writing function to the TFT type liquid crystal display panel. It is an object of the present invention to provide a liquid crystal drive device capable of reducing the sampling capacitance and the amplification element and reducing the circuit thereof by devising the output timing control of the above.

[0029]

[Means for Solving the Problems] FIGS.
FIG. 1 is a principle diagram (1) of a liquid crystal drive device according to the present invention,
2 (a) to 2 (c) respectively show a principle diagram (part 2) of the liquid crystal drive device according to the present invention.

The first liquid crystal driving device of the present invention is shown in FIG.
As shown in, switching control means 11 for outputting a switching control signal SWn [n = 1, 2, 3 ... N] based on the image data DIN of the upper bit group and the image data DIN of the lower bit group, and the switching. Drive output means 12 for selectively combining a plurality of reference voltages VM [M = 1, 2, 3 ... M] based on a control signal SWn and outputting a liquid crystal drive voltage VX, and at least the switching control means 11 And a control means 13 for controlling the input / output of the drive output means 12, the control means 13 relating to the image data DIN of the upper bit group during the transfer or holding period of the image data DIN of the lower bit group. The output control of the combined voltage VUi + VLi of the voltage VUi of 1 and the second voltage VLi related to the image data DIN of the lower bit group is performed.

In the first liquid crystal drive device of the present invention, the drive output means 12 is, as shown in FIG.
The voltage selecting means 12A for selectively outputting the first voltage VUi relating to the image data DIN of the upper bit group and the second voltage VLi relating to the image data DIN of the lower bit group based on the switching control signal SWn, and the first voltage , And second and second voltages VUi and VLi are charged and discharged by sample hold output means 12B.

Further, in the first liquid crystal drive device of the present invention, the control means 13 continues to control the output of the first voltage VUi relating to the image data DIN of the higher-order bit group every horizontal synchronization period, Composite voltage VUi + VLi related to the image data DIN of the lower bit group and the image data DIN of the upper bit group
Is controlled.

Further, in the first liquid crystal driving device of the present invention, the sample-hold output means 12B has first to third switching elements S1 to S3 as shown in FIG. 2B.
It is composed of first and second sampling capacitors C1 and C2 and an amplifying element OP, at least one end of the first switching element S1 is connected to the voltage selecting means 12A, and the other end is the first sampling capacitor C1. One end of the third switching element S3 and the amplifier element OP are connected, and
One end of the switching element S2 is connected to the voltage selection means 12A, and the other end is connected to the second sampling capacitor C2 and the other end of the third switching element S3, and the other end of the third switching element S3. Is connected to the amplification element OP, and the third switching element S3 is controlled based on the output control signal T generated during the transfer or holding period of the image data DIN of the lower bit group.

Further, the second liquid crystal driving device of the present invention is the same as the first liquid crystal driving device, wherein the sample-hold output means 12B has first to fourth switching elements S1 to S4 as shown in FIG. 2C. , The first and second sampling capacitors C1 and C2, and the amplifier element OP, and at least one end of the first switching element S1 has a voltage selecting means 12
Is connected to A and has the other end of the first sampling capacitor C
Connected to one ends of the first and third switching elements S3,
One end of the second switching element S2 has a voltage selecting means.
12A, the other end is connected to one end of the second sampling capacitor C2 and the fourth switching element S4, the other end of the third switching element S3 is the other end of the fourth switching element S4, and An image of the lower bit group is connected to the amplifying element OP, the third switching element S3 is controlled based on the first output control signal T1 generated during the transfer or holding period of the image data DIN of the lower bit group. The fourth switching element S4 is controlled based on the second output control signal T2 generated during the transfer or holding period of the data DIN, and the above object is achieved.

[0035]

[Operation] According to the first liquid crystal drive device of the present invention, as shown in FIG.
As shown in (a), switching control means 11, drive output means 12 and control means 13 are provided, and the sample hold output means 12B of the drive output means 12 is the first to third
Switching elements S1 to S3, first and second sampling capacitors C1 and C2, and an amplifier element OP, and
During the transfer or holding period of the image data DIN of the lower bit group, the control means 13 causes the first voltage VUi relating to the image data DIN of the upper bit group and the image data DIN of the lower bit group.
Output control of the combined voltage VUi + VLi with the second voltage VLi relating to

For example, the switching control signal SWn [n = 1, 1] in the switching control means 11 based on the image data DIN of the upper bit group and the image data DIN of the lower bit group.
2, 3, ... N] are generated, a plurality of reference voltages VM [M = 1, 2, 3] are generated based on the switching control signal SWn.
... M] is selectively combined in a time division manner by the drive output means 12, and the first voltage VUi and the combined voltage relating to the image data DIN of the upper bit group are output as the liquid crystal drive voltage VX by the output control of the control means 13. To be done.

At this time, the voltage selection means 12A of the drive output means 12 as shown in FIG. 2 (a) causes the first voltage VUi or the lower voltage relating to the image data DIN of the high-order bit group based on the switching control signal SWn. The second voltage VLi relating to the image data DIN of the bit group is selectively output to the sample hold output means 12B, and the sample hold output means 12B charges and discharges the first and second voltages VUi, VLi.

Here, for example, the control means 13 continues to send the first voltage VUi relating to the image data DIN of the upper bit group every horizontal synchronization period, and then continues to send the image data DIN and the upper bit of the lower bit group. The composite voltage VUi + VLi relating to the group image data DIN is sent to the data line of the liquid crystal display device.

That is, the first and second switching elements S1 and S2 of the sample hold output means 12B as shown in FIG. 2B are turned on and turned on during the holding period of the image data DIN of the upper bit group. As a result, the first and second sampling capacitors C1 and C2 are charged with the reference voltage VM,
The third switching element S3 is turned on based on the output control signal T generated by the control means 13 during the transfer or holding period of the image data DIN of the lower bit group in the next horizontal synchronization period.

As a result, the image data D of the lower bit group
During the transfer or holding period of IN, the control means 13 generates a combined voltage VUi + VLi of the first voltage VUi relating to the image data DIN of the upper bit group and the second voltage VLi relating to the image data DIN of the lower bit group. By controlling the output in the first half of one horizontal synchronization period, the first voltage VUi relating to the image data DIN of the higher-order bit group is continuously transmitted, and then the combined voltage VUi concerned.
It is possible to send + VLi to the data line.

In the equivalent circuit diagram of the data line and the liquid crystal capacitance of the liquid crystal display device of FIG. 1B, the resistance value RD of the data line is O of the thin film transistor (TFT).
Considering that it is sufficiently smaller than the ON resistance r during N operation, the voltage value of the initial period TA of the voltage waveform VD on the data line is VA, and the charging voltage of the liquid crystal capacitance CL at the end of the period TA. VC is given by the equation (1), that is, VC = VA [1-EXP (-TA / T)] ... (1). The time constant T is the product r × CL of the on-resistance r of the TFT and the liquid crystal capacitance CL.

Next, the combined voltage VUi + VLi is the liquid crystal capacitance CL.
Then, the liquid crystal drive voltage VX becomes V
Assuming that A + ΔV, the charging voltage VC of the liquid crystal capacitance CL at the end of the period TB is expressed by equation (2), that is, VC = (VA + ΔV) −VA · EXP [(− TA + TB) / T] −ΔV · EXP ( -TB / T) ... given by (2).

Here, in the equation (2), the first term (VA +
ΔV) is the true value to be finally charged, and the second and third terms are error terms. By transforming the second and third terms, the following expression (3) is obtained.

Error = − (VA + ΔV) · EXP [(− TA + TB) / T] + ΔV · EXP [(− TA + TB) / T] −ΔV · EXP (−TB / T) (3) where (3) ), The first term is an error term when the liquid crystal drive voltage VX is VA + ΔV throughout the TA + TB period. In the conventional example, the liquid crystal panel and the drive circuit are designed so that this error can be ignored. , This term is small and we ignore it. Then the remaining error is the second
The first and second terms are ignored as the second and third terms are small.
Since it is smaller than the term, it can be ignored. Therefore, the remaining error is the third term, but in this term, ΔV is VA
If it is smaller than 1 and EXP (-TB / T) is sufficiently smaller than 1, it can be ignored.

Whether or not ΔV is smaller than VA is determined by the capacitance C in the calculation for obtaining the combined voltage VUi + VLi.
Related to the capacitance ratio of C1 and C2, the larger this ratio, the smaller ΔV. For example, in the case of 256 gradations called full color, 8-bit information is divided into high-order bit groups and low-order bit groups of 4 bits, so that if the voltages VUi and VLi are weighted the same, the capacitances C1 and C2 The ratio is 16, and ΔV is 1/16 of VA.

Next, regarding the value of EXP (-TB / T),
As described above, the error is (VA + ΔV) · E in the conventional example.
It suffices to design the liquid crystal panel and the drive circuit so that XP [(-TA + TB) / T] has a sufficiently small value. Here, assuming that the error is within 0.1 [%] of the final value,
In order to set EXP [(-TA + TB) / T] = 1/1000, the charging time constant becomes 6.9 / 9 of the period TA + TB. Then, since the periods TA and TB are almost the same time, EXP (-TB / T) is a square root of 1/1000, which is about 1
It becomes / 32.

From the above calculation, the error of this method −ΔV
・ The value of EXP (-TB / T) is (1/16) × the final value.
(1/32) = 1/512, which is a sufficiently small value that causes no practical problem.

As shown in FIG. 1C, this charging curve is a curve in which the voltage value during the TA period is larger and the combined value is smaller. This is because the voltage value becomes smaller due to the combination calculation. Therefore, ΔV calculated by the above equation is actually a negative value.

Therefore, the combined voltage V as in the conventional example.
A sampling capacitor for temporarily charging Ui + VLi and an operational amplifier as an amplifying element for sending the Ui + VLi to the data line are not required, and the ratio of the sample and hold output means 12B occupying the chip area is reduced, and the size can be reduced. It will be possible.

As a result, by devising the output timing control of the added voltage value related to the image data of the upper and lower bit groups while maintaining the writing function to the TFT type liquid crystal display panel, Reduction can be realized, and the circuit can be downsized and the cost can be reduced.

Further, according to the second liquid crystal drive device of the present invention, as shown in FIG. 2C, the sample hold output means 12B has the first to fourth switching elements S1 to S4, the first and second switching elements. Sampling capacitors C1 and C2 and an amplifying element O
P, the third switching element S3 is controlled based on the first output control signal T1 generated during the transfer or holding period of the image data DIN of the lower bit group, and the fourth switching element S4 is controlled by the lower bit group. The image data DIN is controlled based on the second output control signal T2 generated during the transfer or holding period.

Therefore, like the first liquid crystal drive device,
The liquid crystal driving voltage can be sent to the data line of the liquid crystal display device. For example, in the first half of one horizontal synchronization period, the first and third switching elements S1 and S3 are turned on and the other switching elements S2 and S4 are turned off, so that the first sampling capacitor C1 is charged. In the initial state of one horizontal synchronization period in which the first voltage VU11 is sent to the data line, first, the image data DIN of the upper bit group is
When a reference voltage VUi for the voltage selection means 12B is obtained at the output of the voltage selection means 12B, the first switch element S1 is turned on by another output control signal T4, and the reference voltage reference voltage VUi
Are stored in the first sampling capacitor C1. At this time,
By maintaining the OFF operation of the fourth switch element S4,
Reference voltage VUi charged in the first sampling capacitor C1
Is sent out on the data line. This voltage has a value close to the final value of the liquid crystal drive voltage VX, and the liquid crystal capacitance is charged toward this voltage value.

Further, in the middle of one horizontal synchronizing period, the reference voltage V for the image data DIN of the lower bit group is
When Li is obtained at the output of the voltage selection means 12B, the second switch element S2 is turned on by another output control signal T5, and the reference voltage VLi is set to the second sampling capacitance C2.
Accumulate to 2. Then, the second switch element S2 is turned off.
The fourth switch element S4 is turned on by the second output control signal T2 by the operation, and by the action of the third switch element S3 which continues the ON operation,
The combined voltage VUi + VLi charged in the second sampling capacitors C1 and C2 is sent to the data line. That is,
According to the law of conservation of charge, (VUi × C1 + VLi × C2) / (C1
The combined voltage of + C2) becomes the new next voltage.

The image data DIN finally required by this
The liquid crystal drive voltage VX according to the above is sent to the data line, and the liquid crystal capacitance charged toward the reference voltage VUi is charged toward the new voltage.

It is the first and second that holds this final voltage value.
Sampling capacitors C1 and C2 of the third switching element S3 in response to the first output control signal T1 in preparation for the arrival of the image data of the next line (second data line). Stand by by turning off. Further, by continuing the ON operation of the fourth switch element S4, the final voltage on the second sampling capacitor C2 can be continuously sent to the data line.

As a result, similarly to the first liquid crystal driving device, the sampling capacity for temporarily charging the combined voltage VUi + VLi and the operational amplifier for sending the combined voltage to the data line are unnecessary, and the function of writing to the TFT type liquid crystal display panel is eliminated. It is possible to reduce the circuit size and reduce the cost while maintaining the above.

[0057]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, each embodiment of the present invention will be described with reference to the drawings. 3 to 10 are views for explaining a liquid crystal driving device according to each embodiment of the present invention.

(1) Description of First Embodiment FIG. 3 is a block diagram of a multi-tone liquid crystal driving device according to the first embodiment of the present invention, and FIG. 4 is a block diagram of its main circuit. . 5 is a block diagram of the sample hold output circuit, and FIG. 6 is a block diagram of the liquid crystal panel. Further, FIG. 7 shows respective operation timing charts thereof.

For convenience of explanation, a case where 4 × 4 pixels and the image data DIN is N = 4 [bits] will be described. For example, a multi-gradation liquid crystal driving device for driving the TFT type liquid crystal panel 26 is shown in FIG.
1, a voltage selection output system 22, a control circuit 23, a gate driver 24, and a reference voltage generator 25.

That is, the switching control system 21 is an embodiment of the switching control means 11 and outputs the switching control signal SWN [N = 4] based on the image data DIN of the upper 2 bits and the image data DIN of the lower bit group. It is output to the voltage selection output system 22. Note that N represents the number of bits for gradation display.

For example, the switching control system 21 includes the memories MU1, MU2, ML1 and ML2, the switching circuit MPX, the shift register SR, the memories 61A to 64A and the decoders 81A to 84A.
Consists of. The memories MU1 and MU2 are the upper 2 of the image data DIN
The bits D3 and D2 are held and the memories ML1 and
ML2 holds the lower 2 bits D1 and D0 of the image data DIN. The switching circuit MPX is a switching control signal SS
The upper / lower data DU and DL are switched based on the above, and the read data is transferred to the memories 61A to 64A. The shift register SR writes the write signals TW1 to TW4 for each line based on the start signal generated by the control circuit 23.
Is output to the memories 61A to 64A to control writing / reading.

The memories 61A to 64A temporarily latch read data relating to the image data DIN of the upper 2 bits and the image data DIN of the lower bit group, and have a capacity of N bits. The decoders 81A to 84A decode the display data given in binary and output the switching control signals SW1 to SW4 to the voltage selection output system 22.

The voltage selection output system 22 is one embodiment of the drive output means 12, and, for example, four reference voltages V1 to V4 are selected and combined in a time division manner based on the switching control signals SW1 to SW4 to drive the liquid crystal. The voltage VX is output.
For example, the voltage selection output system 22 includes four sets of analog switches 91A to 94A and four sets of sample hold output circuits SH1.
A to SH4A.

Each of the analog switches 91A to 94A is an example of the voltage selecting means 12A, and the switching control signals SW1 to SW are provided.
4 is a digital / analog conversion circuit for selectively outputting the reference voltage VUi relating to the image data DIN of the higher-order bit group and the reference voltage VLi relating to the image data DIN of the lower-order bit group. For example, the analog switches 91A to 94A are
As shown in FIG. 4, analog switches S11-S14, S21-
It is composed of S24, S31 to S34, and S41 to S44.

Further, each sample hold output circuit SH1A
˜SH4A is an example of the sample hold output means 12B, which charges and discharges the reference voltages VUi and VLi. For example, one sample hold output circuit SH1A has three switching elements SA1 to SA1 as shown in FIGS.
It comprises SC1, two sampling capacitors CA1, CB1 and one operational amplifier OP11.

For example, one end of the first switching element SA1 is connected to the analog switch 91A, and the other end is connected to the first sampling capacitor CA1, one end of the third switching element SC1 and the operational amplifier OP11. Further, one end of the second switching element SB1 is connected to the analog switch 91A, and the other end is connected to the second sampling capacitor CB1 and the other end of the third switching element SC1.

The other end of the third switching element SC1 is connected to the operational amplifier OP11, and the third switching element SC1 is operated based on the output control signal T6A generated during the transfer or holding period of the image data DIN of the lower bit group. Is controlled.

Further, each other sample hold output circuit S
The internal configuration of H2A to SH4A is the same as that of the sample hold output circuit SH1A, and therefore its description is omitted. The control circuit 23 is an example of the control means 13, and controls the input / output of the switching control system 21 and the voltage selection output system 22 based on the horizontal synchronizing signal HS, the vertical synchronizing signal VS, and the reference clock signal CLK. . Here, the reference clock signal CLK is not essentially required as an interface, and may be generated inside the driving device by measuring the cycle of the horizontal synchronizing signal HS.

Further, the control circuit 23 outputs the output control signals T4A to T6A to the sample hold output circuits SH1A to SH4A and outputs the switching control signal SS to the switching circuit MPX to output the image data DIN of the lower bit group. During the transfer or the holding period, the output control of the combined voltage VUi + VLi of the reference voltage VUi relating to the image data DIN of the upper bit group and the reference voltage VLi relating to the image data DIN of the lower bit group is performed.

The gate driver 24 controls the gate of the TFT of the liquid crystal panel, and is composed of, for example, four buffers DV1 to DV4 connected to the gate lines Y1 to Y4 as shown in FIG.

The reference voltage generator 25 supplies the M = 4 reference voltages V1 to V4 via the analog switches 91A to 94A, for example, the reference voltage V related to the image data DIN of the upper bit group.
Reference voltage VLi related to Ui and image data DIN of lower bit group
Is supplied to each sample hold output circuit SH1A to SH4A.

As a result, the control circuit 23 continues the output control of the reference voltage VUi related to the image data DIN of the upper bit group every horizontal synchronization period, and then the image data DIN of the lower bit group and the image of the upper bit group. The combined voltage VUi + VLi related to the data DIN can be output controlled.

FIG. 6 is a block diagram of a liquid crystal panel according to each embodiment of the present invention. In FIG. 6, for example, 4 × 4
The liquid crystal panel 26 of the pixel includes 16 thin film transistors (T
FT) Q11 to Q44, and the liquid crystal capacitance C11 to C of each pixel
When writing a signal voltage for display (hereinafter also referred to as a liquid crystal drive voltage) to 44, a switching operation is performed. Also, from P11
P44 indicates a pixel which is the minimum unit of pixel display, and an array of pixels in the horizontal direction is hereinafter referred to as one line. Further, the display data of the liquid crystal panel 26 is written line by line,
By repeating this 60 times per second at zero times, an image without flicker to the human eye is shown.

The actual number of pixels of the liquid crystal panel 26 is about 640 pixels in the horizontal direction and about 480 pixels in the vertical direction. For color display, R (RED, red), G (GREEN, green), B
It has a pixel separately for (BLUE, blue).

In this way, according to the multi-tone liquid crystal drive device of the first embodiment of the present invention, as shown in FIG.
A switching control system 21, a voltage selection output system 22, and a control circuit 23 are provided, and one sample hold output circuit SH1A of the voltage selection output system 22 includes three switching elements SA1 to SC1 and two sampling capacitors CA1. C
B1 and one operational amplifier OP11, and during the transfer or holding period of the image data DIN of the lower bit group, the control circuit 23 controls the reference voltage VUi related to the image data DIN of the upper bit group and the lower bit group. The output of the combined voltage VUi + VLi with the reference voltage VLi related to the image data DIN is controlled.

For example, switching is performed by the switching control system 21 based on the image data of the upper bit group (hereinafter referred to as upper data 1, 2, ...) And the image data of the lower bit group (hereinafter referred to as lower data 1, 2, ...). Control signal SW1
When SW4 is generated, its switching control signal SW1 ~
Based on SW4, four reference voltages V1 to V4 are time-divisionally selected and combined by the voltage selection output system 22, and the reference voltage VU11 related to the upper data 1 and the combined voltage VU11 + VL11 related to the upper and lower data are controlled. The liquid crystal drive voltage VX11 is output by the output control of the circuit 23.

At this time, by the analog switches 91A to 94A of the voltage selection output system 22 as shown in FIG. 4A, the upper data 1 based on the switching control signals SW1 to SW4.
Reference voltage VU11 related to
L11 is selectively output to the sample hold output circuits SH1A to SH4A, and the sample hold output circuits SH1A to SH4A are output.
Then, the reference voltages VU11 and VL11 are charged and discharged.

That is, in the operation time chart of the liquid crystal driving device shown in FIG. 7, for example, the control circuit 23 is used.
Thus, every horizontal synchronization period, the reference voltage VU11 related to the upper data 1 is continuously output, and the combined voltage VU11 + VL11 related to the lower data 1 and the upper data 1 is output to the data line of the liquid crystal display device. The control signal T6A is output to the third analog switches SC1 to SC4 of the sample hold output circuits SH1A to SH4A.

As a result, the first and second switching elements SA1 to SA4 and SB1 to SB4 of the sample and hold output circuits SH1A to SH4A as shown in FIG. 5 are turned on and turned on during the holding period of the upper data. As a result, the first and second sampling capacitors CA1 and CB1 are charged with the reference voltages V1 to V3 or V4, and the output generated by the control circuit 23 during the transfer or holding period of the lower data 2 of the next horizontal synchronization period. The third switching elements SC1 to SC4 are turned on based on the control signal T6A.

As a result, during the transfer or holding period of the lower data 2, the control circuit 23 controls the reference voltage VU11 of the upper data 1 with respect to the reference voltage VU 11 of the lower data 1.
The output voltage of the combined voltage VU11 + VL11 with L11 is controlled in the first half of one horizontal synchronization period, so that the combined voltage VU11 + continues to be transmitted to the reference voltage VU11 related to the upper data 1.
VL11 can be sent to the data line as the liquid crystal drive voltage VX1.

Therefore, as in the conventional example, the combined voltage V
There is no need for a sampling capacitor that charges U11 + VL11 once and an operational amplifier that sends it to the data line.
The ratio of the sample hold output circuits SH1A to SH4A occupying the chip area is relaxed, and the circuit can be downsized (see comparison in FIG. 12).

As a result, the sampling capacity and the operational amplifier are reduced by devising the output timing control of the added voltage value relating to the image data of the upper and lower bit groups while maintaining the writing function to the TFT type liquid crystal display panel. Can be realized, and the circuit can be downsized and the cost can be reduced.

(2) Description of Second Embodiment FIG. 8 is a block diagram of a multi-tone liquid crystal driving device according to a second embodiment of the present invention, and FIG. 9 is a configuration of a sample hold output circuit thereof. FIG. 10 is a diagram showing the operation time charts thereof.

The difference from the first embodiment is that in the second embodiment, the fourth switching element SDN is connected,
The output control is performed based on the second output control signal T7A generated during the transfer or holding period of the image data DIN of the lower bit group.

That is, the multi-gradation liquid crystal driving device for driving the TFT type liquid crystal panel 36 includes a switching control system 31, a voltage selection output system 32, a control circuit 33, a gate driver 34 and a reference voltage generator 35 in FIG. Become.

That is, the switching control system 31 is another embodiment of the switching control means 11, and the upper 2-bit image data DIN and the lower 2-bit image data DIN are set.
The switching control signals SW1 to SW4 are output to the voltage selection output system 32 based on For example, the switching control system 31 includes the memories MU1, MU2, ML1 and ML2, the switching circuit MPX, the shift register SR, and the memories 61A to 64A.
And decoders 81A to 84A.

The memories MU1 and MU2 hold the upper 2 bits D3 and D2 of the image data DIN, and the memory ML
Reference numerals 1 and ML2 hold the lower 2 bits D1 and D0 of the image data DIN. The switching circuit MPX switches the upper / lower data DU and DL based on the switching control signal SS and transfers the read data to the memories 61A to 64A. The shift register SR outputs write signals TW1 to TW4 to the memories 61A to 64A based on the clock signal CK1A from the control circuit 33, and controls the writing / reading.

The memories 61A to 64A temporarily latch the read data relating to the image data DIN of the upper 2 bits and the image data DIN of the lower bit group. Decoder 81A-84
A is for decoding the read data and outputting the switching control signals SW1 to SW4 to the voltage selection output system 33.

The voltage selection output system 32 is another embodiment of the drive output means 13 and includes switching control signals SW1 to SW4.
Based on the above, for example, the four reference voltages V1 to V4 are selected and combined in a time division manner and the liquid crystal drive voltage VX is output. For example, the voltage selection output system 32 includes four sets of analog switches 91A to 94A and four sets of sample hold output circuits SH1B to SH4B.

Each of the analog switches 91A to 94A selectively outputs the reference voltage VUi relating to the image data DIN of the upper bit group or the reference voltage VLi relating to the image data DIN of the lower bit group based on the switching control signals SW1 to SW4. Is.

Further, each sample hold output circuit SH1B
˜SH4B is an example of the sample hold output means 12B, which charges and discharges the reference voltages VUi and VLi. For example, one sample hold output circuit SH1B has four analog switches SAN to SDN, 2 as shown in FIG.
It is composed of sampling capacitors CAN and CBN and one operational amplifier OP2N. One end of the analog switch SAN is connected to the analog switch 91A, and the other end is connected to one end of the sampling capacitor CAN and the analog switch SBN.

Further, one end of the analog switch SBN is connected to the analog switch 91A, and the other end is connected to the sampling capacitor CBN and one end of the analog switch SDN. Further, the other end of the analog switch SCN is the fourth
Is connected to the other end of the analog switch SDN, which serves as a switching element of, and the operational amplifier OP2N.

The analog switch SCN is controlled based on the output control signal T6B generated during the transfer or holding period of the image data DIN of the lower bit group, and the analog switch SDN transfers or holds the image data DIN of the lower bit group. It is controlled based on T7A generated during the period. The other structure is similar to that of the first embodiment, and the description thereof is omitted.

In this way, according to the multi-tone liquid crystal driving device of the second embodiment of the present invention, as shown in FIG.
One sample hold output circuit SH1B has four switching elements SAN to SDN, and two sampling capacitors C.
An output control signal T consisting of AN, CBN and one operational amplifier OP21, which is generated by the third analog switch SCN during the transfer or holding period of the image data DIN of the lower bit group.
Controlled based on 6B, fourth analog switch SD1
Are controlled based on the output control signal T7A generated during the transfer or holding period of the image data DIN of the lower bit group.

Therefore, similar to the first embodiment, the liquid crystal drive voltage VX1 is applied to the data lines X1 to X4 of the liquid crystal panel 36.
Can be sent. For example, in the operation time chart of FIG. 10, the case of the first data line (N = 1) will be described. In the initial state of one horizontal synchronization period, first, the analog voltage (reference voltage) for the image data DIN of the upper bit group is set. When the voltage) VU11 is obtained at the output of the analog switch 91A, the output control signal T4B turns on the first analog switch SA1 to store the reference voltage VU11 in the first sampling capacitor CA1. At this time, the third analog switch SC1 maintains the ON operation and the second and fourth analog switches SB1 and SD1 maintain the OFF operation, so that the reference voltage VU11 charged in the first sampling capacitor CA1 changes to the operational amplifier OP21. To the data line. This voltage is the liquid crystal drive voltage VXN
Is close to the final value of, and the liquid crystal capacitance is charged toward this voltage value.

Further, in the middle of one horizontal synchronizing period, when the analog voltage (reference voltage) VL11 for the image data DIN of the lower bit group is obtained at the output of the analog switch 91A, the output control signal T5B causes the second voltage. The analog switch SB1 is turned on, and its reference voltage VL11
Are stored in the second sampling capacitor CB1. And
The second analog switch SB1 performs the OFF operation, and the third
By continuing the ON operation of the analog switch SC1 of, the fourth analog switch S is driven by the output control signal T7A.
When D1 turns on, the combined voltage VU11 + V charged in the first and second sampling capacitors CA1 and CB1
L11 is sent out on the data line. That is, according to the law of conservation of charge, (VU11 × CA1 + VL11 × CB1) / (CA
The combined voltage VC1 of 1 + CB1) becomes a new next voltage.

Image data DIN finally required by this
Is the liquid crystal drive voltage VXN related to the data line X
1, the liquid crystal capacitance previously charged to the analog voltage VU11 is charged to the new voltage.

It is the first and the first that hold this final voltage value.
The second sampling capacitors CA1 and CB1 are provided, and the first sampling capacitor CA1 prepares for the output control signal T6B in preparation for the arrival of the image data of the next line (second data line).
Thus, the third analog switch SC1 is turned off to stand by. In addition, the fourth analog switch SD1
By continuing the ON operation of, the final voltage on the second sampling capacitor CB1 can be continuously sent to the data line.

In FIG. 10, the reference voltage VU11 is the image data voltage for the upper bit of the first line with respect to the first data line, and the reference voltage VL11 is the lower voltage of the first line for the first data line. Image data voltage for bits. Similarly, the reference voltage V
U21 is the image data voltage for the upper bits of the second line with respect to the first data line, and is the reference voltage V
L21 is the image data voltage for the lower bit of the second line with respect to the first data line.

Further, the reference voltage VU31 is the image data voltage for the upper bit of the third line with respect to the first data line, and the reference voltage VL31 is the image data for the lower bit of the third line for the first data line. Voltage. The combined voltage VC2 is the first sampling capacitance CA of the reference voltage VU21 and the reference voltage VL21.
1 and the sampling capacitor CB1 are combined, that is, (VU21 × CA1 + VL21 × CB1) / (CA1 +
This is the voltage obtained by CB1).

As a result, similarly to the first embodiment, the sampling capacitor for temporarily charging the combined voltage VU11 + VL11 and the operational amplifier for sending it to the data line are not required. In addition, the number of operational amplifiers required in the conventional sample hold output circuit can be reduced to one,
It is possible to significantly reduce the number of operational amplifiers installed while maintaining the function of writing to a 480 x 640 pixel TFT type liquid crystal display panel, and to reduce the circuit size and cost.

[0102]

As described above, according to the first liquid crystal drive device of the present invention, the switching control means, the drive output means and the control means are provided, and the sample hold output means of the drive output means is the first. ~ Third switching element,
The first and second sampling capacitors and the amplification element,
Further, during the transfer or holding period of the image data of the lower bit group, the control means generates a combined voltage of the first voltage relating to the image data of the upper bit group and the second voltage relating to the image data of the lower bit group. Output controlled.

Therefore, the sampling capacitor for temporarily charging the combined voltage and the operational amplifier as an amplifying element for sending the combined voltage to the data line as in the conventional example are unnecessary, and the sample and hold output means occupies the chip area. The ratio will be relaxed and it will be possible to reduce the ratio. From this, it is possible to reduce the sampling capacitance and the amplification element while maintaining the writing function to the TFT type liquid crystal display panel.

Further, according to the second liquid crystal drive device of the present invention, in the first liquid crystal drive device, the sample hold output means includes the first to fourth switching elements, the first and second switching devices.
And a third switching element is controlled based on a first output control signal generated during a transfer or holding period of image data of a lower bit group, and a fourth switching element is a lower bit. It is controlled based on the second output control signal generated during the transfer or holding period of the image data of the group.

Therefore, like the first liquid crystal drive device,
Even when the sampling capacitor for temporarily charging the combined voltage and the operational amplifier as an amplifying element for sending it to the data line are removed as in the conventional example, the liquid crystal drive voltage is sent to the data line of the liquid crystal display device. It becomes possible to do.

As a result, the circuit scale can be reduced and the cost can be reduced, which contributes to the provision of a liquid crystal driving device capable of displaying multi-gradation images on an active matrix type liquid crystal display panel and its industrial value improvement. However, it is big.

[Brief description of drawings]

FIG. 1 is a principle diagram (1) of a liquid crystal drive device according to the present invention.
Is.

FIG. 2 is a principle diagram of a liquid crystal drive device according to the present invention (No. 2)
Is.

FIG. 3 is a configuration diagram of a multi-tone liquid crystal driving device according to a first embodiment of the present invention.

FIG. 4 is a configuration diagram of a main circuit of the liquid crystal driving device according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a sample hold output circuit according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram of a liquid crystal panel according to each embodiment of the present invention.

FIG. 7 is an operation time chart of the liquid crystal drive device according to the first embodiment of the present invention.

FIG. 8 is a configuration diagram of a multi-tone liquid crystal driving device according to a second embodiment of the present invention.

FIG. 9 is a configuration diagram of a sample hold output circuit according to a second embodiment of the present invention.

FIG. 10 is an operation time chart of the liquid crystal drive device according to the second embodiment of the present invention.

FIG. 11 is an explanatory diagram of a multi-tone liquid crystal driving device according to a conventional example.

FIG. 12 is a configuration diagram of a main part of a liquid crystal drive device according to a conventional example.

FIG. 13 is an operation time chart of the liquid crystal driving device according to the conventional example.

[Explanation of symbols]

11 ... Switch control means, 12 ... Drive output means, 13 ... Control means, 12A ... Voltage selection means, 12B ... Sample hold output means, C1, C2 ... First and second sampling capacitors, S1 to S4 ... First to first Fourth switch element, OP ... Amplifying element, DIN ... Image data, SWi [i = 1, 2, ... i] ... Switch control signal, VM [M = 1, 2, ... M] ... Reference voltage, VX ... Liquid crystal Drive voltage, VUi ... 1st voltage, VLi ... 2nd voltage, T (T1, T2) ... Output control signal (1st, 2nd output control signal).

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Yuichi Miwa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Hiroyuki Isogai 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takahiro Nakano 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (5)

[Claims] 1. A switching control for outputting a switching control signal (SWn [n = 1,2,3 ... n]) based on the image data (DIN) of the upper bit group and the image data (DIN) of the lower bit group. Means (11) and a plurality of reference voltages (VM [M [M] based on the switching control signal (SWn).
, 1, 2, 3 ... M]) in a time-sharing manner and outputs the liquid crystal drive voltage (VX), and at least the switching control means (11) and the drive output means (12). ) Input / output control means (13) for controlling the input / output of the upper bit group (DIN) while the control means (13) transfers or holds the image data (DIN) of the lower bit group. ) Related first voltage (VUi)
And the second data relating to the image data (DIN) of the lower bit group
A liquid crystal driving device characterized by controlling output of a combined voltage (VUi + VLi) with a voltage (VLi) of the above. 2. The liquid crystal drive device according to claim 1,
The drive output means (12) is a switching control signal (SW
n), the first voltage (VUi) relating to the image data (DIN) of the upper bit group and the image data (D) of the lower bit group.
Voltage selection means (12A) for selectively outputting the second voltage (VLi) related to IN), and the first and second voltages (VUi, VL)
Sample hold output means (12B) for charging and discharging i)
A liquid crystal driving device comprising: 3. The liquid crystal driving device according to claim 1,
The control means (13) continues to control the output of the first voltage (VUi) relating to the image data (DIN) of the higher-order bit group every horizontal synchronization period, and then the image data (DIN) of the lower-order bit group. And a liquid crystal driving device which controls output of a combined voltage (VUi + VLi) relating to image data (DIN) of the upper bit group. 4. The liquid crystal drive device according to claim 3,
The sample hold output means (12B) comprises first to third switching elements (S1 to S3), first and second sampling capacitors (C1 and C2) and an amplifier element (OP), and at least the first One end of the switching element (S1) is connected to the voltage selection means (12A), and the other end is connected to the first sampling capacitor (C1), one end of the third switching element (S3) and the amplification element (OP). One end of the second switching element (S2) is connected to the voltage selecting means (12A), and the other end is connected to the second sampling capacitor (C2) and the third switching element (S3).
Is connected to the other end of the third switching element (S3), and the other end of the third switching element (S3) is connected to an amplifying element (OP).
3) is controlled on the basis of an output control signal (T) generated during the transfer or holding period of the image data (DIN) of the lower bit group. 5. The liquid crystal drive device according to claim 3,
The sample-hold output means (12B) includes first to fourth switching elements (S1 to S4), first and second sampling capacitors (C1 and C2) and an amplification element (OP), and at least the first One end of the switching element (S1) is connected to the voltage selection means (12A), and the other end is connected to one end of the first sampling capacitor (C1) and the third switching element (S3), One end of the switching element (S2) is connected to the voltage selecting means (12A), and the other end is connected to the second sampling capacitor (C2) and the fourth switching element (S4).
Is connected to one end of the third switching element (S3), the other end of the third switching element (S3) is connected to the other end of the fourth switching element (S4) and an amplification element (OP), and the third switching element (S3) is The fourth switching element (S4) is controlled based on the first output control signal (T1) generated during the transfer or holding period of the lower bit group image data (DIN), and the fourth switching element (S4) controls the lower bit group image data ( The liquid crystal drive device is controlled based on a second output control signal (T2) generated during the transfer or holding period of (DIN).