JPH06120939A - Pointer processing circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object to provide a pointer processing circuit that can easily and quickly recover from a memory slip state. [Structure] A write counter (2) and a read counter (3) that generate a write clock (RCK) and a read clock (SCK) that are obtained by dividing the period of each bit of input data by N, respectively.
And each bit of input data is N of write clock (RCK)
Memory part that divides into multiple areas by clock and stores (1)
And a control signal (INCREQ, DEC) for synchronizing the read clock (SCK) to read the substantially central area of each bit stored in the memory section (1) divided into a plurality of areas.
REQ) is provided based on the phase difference between both clocks (RCK, SCK) and a phase comparator (4), and when the control signal (INCREQ, DECREQ) is output from the phase comparator (4), Reset signal that initializes both counters (2, 3) and phase comparator (4)
It is equipped with a memory slip monitor (5) that generates (PTRRESET).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to, for example, SONET (Synchr
in new synchronous multiplex communication such as onous Optical NETwork)
The present invention relates to pointer processing when transferring from a clock on the reception side to a clock on the transmission side in a relay device, a multiplex conversion device, or the like on the transmission path, and particularly to a pointer processing technique whose main purpose is to avoid memory slip.

[0002]

2. Description of the Related Art In the new synchronous multiplex communication, one frame (125 μ
The pointer processing is performed to switch the received data from the clock on the receiving side to the clock on the transmitting side to obtain the transmitted data without delay of (S) .For this reason, a memory that is a first-in first-out memory and also functions as a buffer memory (error Stick store) is used. At this time, in order to prevent memory slip and absorb frame jitter,
The stuff control is performed based on the phase comparison between the reception side clock and the transmission side clock.

FIG. 1 is a block diagram schematically showing a conventional configuration of a portion for performing such processing in the new synchronous multiplex communication.

In FIG. 1, a memory section indicated by reference numeral 1 is the above-mentioned first-in first-out memory and also functions as a buffer memory. Normally, input data is temporarily taken in and output data is output at a predetermined phase difference. Output as. Writing the input data to the memory unit 1
The write counter 2 shown as 1 / N.CTR operates according to the write clock RCK which generates N clocks per clock of the receiver clock. On the other hand, the memory unit 1
The output data from is read by the write counter 2 described above.
Similarly, the read counter 3 shown as 1 / N.CTR operates in accordance with the read clock SCK which generates N clocks per clock of the transmitting side clock.

Reference numeral 4 is a phase comparator, which compares the phases of a write clock RCK and a read clock SCK generated by both counters 2 and 3 and writes a window on the write side described later.
The W-WINDOW and the read side window R-WINDOW are generated and given to the write counter 2 and the read counter 3, respectively.

The timing chart of FIG. 2 shows the memory unit 1
The number of memory stages M is 17, and both counters 2 and 3 are 1/17
・ Indicates the optimum operating condition for CTR.

FIG. 2A shows the 0th to 16th write clocks RCK generated by the write counter 2, and FIG. 2D shows the 0th to 16th read clocks SCK generated by the read counter 3. Shown respectively. Further, FIG. 2B shows the timing of the write side window W-WINDOW described above, and the period from the third clock to the 13th clock of the write clock RCK given from the phase comparator 4 to the write counter 2 is active. (Low level).
Further, FIG. 2 (c) shows the read side window R-WINDOW described above.
Of the read clock SCK supplied from the phase comparator 4 to the read counter 3 is active (high level) only during the eighth clock period.

FIG. 2 (e) shows the timing of the received data, that is, the write data to the memory section 1, and FIG. 2 (f) shows the timing of the transmitted data, that is, the read data from the memory section 1. The write data is the write clock RC given from the write counter 2 to the memory unit 1.
It lasts for 17 K clocks. Normally, as described above, the write clock RCK and the read clock SCK are synchronized with each other, and the read side window R-WINDOW becomes active during the period of the eighth pulse in the middle thereof.
A read pulse is generated as shown in (f).
Then, by reading the write data by this read pulse, the read data is obtained as shown in FIG. 2 (g).

In other words, the eighth central period of the write data divided into 17 equal parts is taken out as the read data, so that the individual data such as the 0th clock or the 16th clock of the write clock RCK is extracted. Reliable data transmission is performed by avoiding reading an uncertain portion close to the conversion point.

Therefore, in the timing chart shown in FIG. 2, the phases of the write clock RCK and the read clock SCK output from both counters 2 and 3 are synchronized, but when they are not synchronized, both clocks are synchronized. If the phase difference of 1 is detected by the phase comparator 4, it is possible to detect the deviation between the input data and the output data to the memory unit 1. The amount of this deviation is such that the reading side window R-WINDOW shown in FIG. 2 (c) is within the writing side window W-WINDOW shown in FIG. 2 (a), or in an optimum state. The stuffing control signal for this purpose is phase comparison because stuffing control is required to speed up (DECREMENT) or delay (INCREMENT) the reading of data from the memory unit 1. It is output from the container 4. That is, the adjustment amount between the writing of the input data and the reading of the output data with respect to the memory unit 1 at the time of transferring the data from the receiving side clock to the transmitting side clock is referred to as stuff, and the signal amount input as the input data is output. Positive stuff (PSTF) is required when the amount of signal output as data is smaller, and negative stuff (NSTF) is required in the opposite case.

However, when the write clock RCK on the receiving side or the read clock SCK on the transmitting side is momentarily cut off, as shown in the timing chart of FIG.
Write-side window W-WINDOW and read-side window R-WI
A memory slip condition occurs that is not synchronized with NDOW. The stuff control as described above is performed in order to recover such a memory slip state. However, the SONET standard says that the stuff control cannot be performed for the three frames after the stuff control.

Therefore, for example, the write clock RCK shown in FIG. 3 (a) and the read clock SCK shown in FIG. 3 (d) are not synchronized, and are shown in FIG. 3 (b). From the active period of the writing side window W-WINDOW, the reading side window R- shown in Fig. 3 (c).
If the reading side window R-WINDOW is moved to the active range of the writing side window W-WINDOW when the WINDOW is removed, as shown in FIG.
Time staff control is required. Accordingly, 24 frames are required for the stuffing control six times, and one frame is required for the last stuffing control, so that stable transmission data may not be output to the reading side for a maximum of 25 frames.

[0013]

By the way, in the present situation, even if some trouble occurs in the data line, it is not interrupted, and it is socially required to recover in a short time by switching to the backup line. There is. Therefore, as described above
If SONET cannot recover from the memory slip state for up to 25 frames, it causes various problems.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a pointer processing circuit capable of easily and quickly recovering from a memory slip state.

[0015]

FIG. 4 is a block diagram showing the basic structure of a pointer processing circuit in the new synchronous multiplex communication according to the present invention. In FIG. 4, reference numeral 1 is a memory unit, which normally takes in input data once and outputs it as output data with a predetermined phase difference. The writing of the input data to the memory unit 1 is performed in accordance with the write clock RCK in which the write counter 2 shown as 1 / N.CTR generates N clocks per one clock of the receiving side clock.

On the other hand, in order to read the output data from the memory unit 1, the read counter 3 shown as 1 / N.CTR, as in the write counter 2 described above, is set to 1 on the transmission side clock.
Read clock SC that generates N clocks per clock
Done according to K.

Reference numeral 4 is a phase comparator, which compares the phases of the write clock RCK and the read clock SCK generated by both counters 2 and 3 and writes a window on the write side described later.
The W-WINDOW and the read side window R-WINDOW are generated and given to the write counter 2 and the read counter 3, respectively. The above reference numerals 1, 2, 3 and 4 are the same as those of the conventional device shown in FIG. 1, but in the pointer processing circuit of the present invention, the configuration and operation of the phase comparator 4 are different from those of the conventional device.
Further, a memory slip monitoring unit 5 indicated by reference numeral 5 is provided.

The memory slip monitor 5 receives the increment or decrement stuff control signal INCREQ or DECREQ output from the phase comparator 4 for stuff control, and monitors whether or not a memory slip has occurred. Then, when the occurrence of a memory slip is detected, the memory slip monitoring unit 5 gives the initial state control signal PTRRESET to both counters 2 and 3 and the phase comparator 4 to reset them to the initial state.

[0019]

In the pointer processing circuit of the present invention, the write clock RCK generated by the write counter 2 and the read counter 3 are generated.
The phase with the read clock SCK generated by the phase comparator 4
The stuffing control signal INCREQ or DECREQ of the increment request or the decrementing request is output by the comparison with the above, but the memory slip is monitored by supplying the stuffing control signal to the memory slip monitoring unit 5. When a memory slip occurs, the initial state control signal PT output from the memory slip monitor 5 is output.
Both counters 2 and 3 are reset to the initial state by RRESET and synchronized with each other, the head of the read data is fixed in one frame, and is stable after two frames.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof.

FIG. 5 and FIG. 6 are circuit diagrams showing a specific structure of a main part of the pointer processing circuit according to the present invention, that is, the phase comparator 4 and the memory slip monitoring part 5, respectively.

In FIG. 5 showing the structure of the phase comparator 4,
Reference numerals 20 and 30 are both decoders. decoder
The write clock RCK is input to 20 and outputs the 0th, 1st, 2nd, 14th, 15th and 16th clocks thereof. The read clock SCK is input to the decoder 30 and outputs the ninth clock.

Reference numerals 41 and 42 are both 3-input OR gates, which are write clocks output from the decoder 20.
The 0th, 1st, and 2nd clocks of RCK are input to the OR gate 41,
The 14th, 15th, and 16th clocks are input to the OR gate 42, respectively. Therefore, when the write side window W-WINDOW is not active, a high level signal is output from either of the OR gates 41 and 42 and input to the NAND gates 43 and 44, respectively.

Each of the NAND gates 43 and 44 has two inputs, and one input terminal of each of them has the above-mentioned OR gate 41,
The output signal of 42 is input, and the decoder is input to the other input terminal.
The ninth clock of the read clocks SCK output from 30 is input. Therefore, the NAND gate 43 outputs a low-level signal when the ninth clock of the read clock SCK is output at the same time as any of the 0th, first, and second clocks of the write clock RCK. Also, NAND gate
At 44, a low level signal is output when the ninth clock of the read clock SCK is output at the same time as any of the fourteenth, fifteenth, and sixteenth clocks of the write clock RCK.

Reference numerals 45 and 46 are both RS (reset set) flip-flops. The output signal of the NAND gate 43 is applied to the negative logic set terminal S of the RS flip-flop 45, and the AND gate described later is applied to the negative logic reset terminal R.
49 output signals are provided, and RS flip-flop
The output signal of the NAND gate 44 is applied to the negative logic set terminal S of 46, and the AND gate 49 described later is applied to the negative logic reset terminal R.
The output signal of is given.

Therefore, the RS flip-flops 45 and 46 are set when the output signals of the NAND gates 43 and 44 are low level, and output the high level signal from the output terminal Q, respectively. These RS flip flops 45
The high level output signal of is the increment request signal INCR
The high-level output signal from the RS flip-flop 46 is the decrement request signal DECREQ. In addition,
Reference numeral 47 is a 2-input OR gate, and when the high level signal is output from either of the RS flip-flops 45 and 46, in other words, the increment request signal.
The high-level signal INCDEC is output when either INCREQ or the decrement request signal DECREQ is output.

Reference numeral 48 is a 2-input NAND gate,
A high-level signal is input to one input terminal at the H2 byte timing (8k timing) included once in each frame of the new synchronous multiplex communication, and the output of the OR gate 47 described above is input to the other input terminal. The signal INCDEC is input. Therefore, this NAND gate 49 is 1 for each frame of each received data.
Increment request signal IN at H2 byte timing
A low level signal is output when either CREQ or decrement request signal DECREQ is output.

Reference numeral 49 is a two-input AND gate,
The output signal of the NAND gate 48 is input to one input terminal,
An initial state control signal PTRRESET, which will be described later, output from the memory slip monitoring unit 5 is input to the other input terminal. Therefore, this AND gate 49 is the NAND gate described above.
When 48 outputs a low level signal or when the initial state control signal PTRRESET is low level, it outputs a low level signal, which is the negative logic reset terminal of both RS flip-flops 45 and 46 described above. Since it is supplied to R, both RS flip-flops 45 and 46 are reset.

FIG. 6 showing the configuration of the memory slip monitoring unit 5.
In the figure, reference numeral 51 is a two-input OR gate, and the increment request signal INCREQ and the decrement request signal DECREQ output from the phase comparator 4 are input to the respective input terminals. Also, reference numeral 52
Is a 2-input AND gate, and the increment request signal INCREQ and the decrement request signal DECREQ output from the phase comparator 4 are input to the respective input terminals.

Reference numerals 53 and 54 are both D flip-flops, and a data input terminal D of the D flip-flop 53.
Is supplied with the output signal of the OR gate 51, and the clock terminal C is supplied with the read clock SCK. The output signal of the AND gate 52 is input to the data input terminal D of the D flip-flop 54, and the read clock SCK is input to the clock terminal C.

Therefore, the D flip-flop 53 latches and outputs the output signal of the OR gate 51 in synchronization with the fall of the read clock SCK. In other words, the D flip-flop 53 outputs a high level signal if either the increment request signal INCREQ or the decrement request signal DECREQ is high level. Also, the D flip-flop 54
Is the AND gate in synchronization with the falling edge of the read clock SCK.
The output signal of 52 is latched and output. In other words, the D flip-flop 54 outputs a high level signal if the increment request signal INCREQ and the decrement request signal DECREQ are simultaneously at high level.

The output signal of the D flip-flop 53 is applied to one input terminal of a 2-input AND gate 55,
A pointer value immediate change request flag NDF-en (N
ew Data Flag-enable) is given. Therefore, AND
The gate 55 outputs a high level signal when the output signal of the OR gate 51 is high level and the pointer value immediate change request flag NDF-en is active.

The output signal of the AND gate 55 is a 2-input N
The output signal of the D flip-flop 54 is applied to one input terminal of the OR gate 56 and the other input terminal. Therefore, the NOR gate 56 outputs a low level signal when either the output signal of the AND gate 55 or the output signal of the D flip-flop 54 is high level.

The output signal of the NOR gate 56 is applied to one input terminal of the 2-input OR gate 57, while the output signal of the 2-input OR gate 59 is applied to the other input terminal. A read clock SCK is input to one input terminal of the OR gate 59, and a signal which becomes high level at the timing of the H1 byte (8k timing) once for each frame of the received data is input to the other negative logic input terminal. Has been done. Therefore, this OR gate 59 outputs a low level signal when the read clock SCK is low level and not at the timing of H1 byte.

Therefore, the OR gate 57 outputs a low level signal only when the output signal of the NOR gate 56 is low level and the output signal of the OR gate 59 is low level, and the OR gate 57 outputs the low level signal of the 2-input AND gate 58. Apply to one input terminal. this
The other input terminal of the AND gate 58 is supplied with the low active reset signal Power on Reset of the entire device.
If any of the output signals of 57 is low level, the low active initial state control signal PTRRESET which is the output signal of the AND gate 58 becomes low level.

The initial state control signal PTRRESET which is the output signal of the AND gate 58 is the AND signal of the phase comparator 4 as described above.
In addition to being applied to the other input terminal of the gate 49, it is also applied to the write counter 2 and the read counter 3,
Reset each.

To summarize the above, the memory slip monitoring unit 5 is requested to prompt the pointer value immediate change request flag NDF-en and the increment request signal INCREQ or the decrement request signal DECREQ.
The occurrence of a memory slip is detected when and are given, and the occurrence of a memory slip is also detected when the increment request signal INCREQ and the decrement request signal DECREQ are given at the same time, and the initial state control signal PTRR is detected.
ESET is output from the memory slip monitoring unit 5. Then, when the initial state control signal PTRRESET is output from the memory slip monitoring unit 5, the RS flip-flops 45 and 46 are both reset in the phase comparator 4, and the write counter 2 and the read counter 3 are reset to reset the initial state. become.

In the pointer processing circuit of the present invention having such a structure, when the write clock RCK on the receiving side or the read clock SCK on the transmitting side is momentarily cut off, as shown in the timing chart of FIG. Operate.

When a memory slip state occurs in which the write side window W-WINDOW and the read side window R-WINDOW are not synchronized, that is, the write clock RCK shown in FIG. 7 (a) and the write clock RCK shown in FIG. 7 (d), for example. Read clock
The SCK becomes out of synchronization, and the read side window R-WINDOW shown in Fig. 7 (c) becomes a normal broken line from the active period of the write side window W-WINDOW shown in Fig. 7 (b). Move from the position of to the position of the solid line.

When such a state is encountered, as shown in FIG.
The boundary of the write data shown in (f) is shown in Fig. 7 (c).
Since the read side window R-WINDOW shown in FIG. 7 is located, the read data is in an indefinite state as shown in FIG. 7 (g).

Such a state is detected by the phase comparator 4, and the increment request signal INCREQ or the decrement request signal DECREQ is output. Since this is input to the memory slip monitoring unit 5, the memory slip monitoring unit 5 outputs the initial state control signal PTRRESET and gives it to the phase comparator 4, the write counter 2 and the read counter 3.

When the initial state control signal PTRRESET is given, both counters 2 are received in the next frame of the received data.
3 is reset, and the output of the increment request signal INCREQ and the decrement request signal DECREQ from the phase comparator 4 is stopped. As a result, as shown in FIG. 7 (e), the read side window R-WINDOW must be within the range of the write side window W-WINDOW shown in FIG. 7 (b). After the frame, stable data reading is performed.

[0043]

As described above in detail, in the conventional SONET, the transmission data was stable after a maximum of 25 frames when the memory slip occurred, but according to the pointer processing circuit of the present invention, the transmission data is stable after a maximum of 2 frames. The transmitted data is stable.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a conventional configuration of a portion that performs pointer processing in new synchronous multiplex communication.

FIG. 2 is a timing chart showing an optimum operating state in the new synchronous multiplex communication when the number of memory stages M of the memory unit is 17 and both counters are both 1/17 · CTR.

3 is a timing chart showing an operation state when a memory slip state occurs from the state of FIG.

FIG. 4 is a block diagram showing a basic configuration of a pointer processing circuit in the new synchronous multiplex communication of the present invention.

FIG. 5 is a circuit diagram showing a specific configuration of a phase comparator of the pointer processing circuit of the present invention.

FIG. 6 is a circuit diagram showing a specific configuration of a memory slip monitoring unit of the pointer processing circuit of the present invention.

FIG. 7 is a timing chart showing an operation state of the pointer processing circuit of the present invention when a memory slip occurs.

[Explanation of symbols]

 1 memory section 2 write counter 3 read counter 4 phase comparator 5 memory slip monitoring section RCK write clock SCK read clock DECREQ decrement request signal INCREQ increment request signal PTRRESET initial state control signal

Claims (1)

[Claims] 1. A write counter (2) and a read counter for respectively generating a write clock (RCK) and a read clock (SCK) obtained by dividing a period of each bit of input data into N.
(3) and each bit of the input data to the write clock (R
The memory unit (1) is divided into a plurality of regions by N clocks of (CK), and the substantially central region of each bit stored in the memory unit (1) is read. A pointer processing circuit provided with a phase comparator (4) for generating a control signal (INCREQ, DECREQ) for synchronizing the read clock (SCK) to be output based on the phase difference between the both clocks (RCK, SCK). In, the phase comparator (4) from the control signal (INCREQ, DECREQ)
Is output, a memory slip monitoring unit (5) for generating a reset signal (PTRRESET) for initializing the counters (2, 3) and the phase comparator (4) is provided. Pointer processing circuit.