JPH06120837A - Delta sigma modulator - Google Patents

Abstract

PURPOSE:To produce the small capacities equivalently and to reduce the gain of a feedback stage by connecting three electrostatic capacities in a T-shape to prescribe the gain of a feedback part with regard to a delta sigma modulator consisting of a switched capacitor circuit. CONSTITUTION:A 5-stage delta sigma modulator consisting of a switched capacitor circuit has two feedback paths led to the input of an integrator 2 from the output of an integrator 3 and to the input of an integrator 4 from the output of an integrator 5 respectively. The capacities Cb21, Cb22 and Cb23 of the feedback path to the integrator 2 from the integrator 3 are connected together in a T-shape with its feedback gain set at 1/32. meanwhile the capacities Cb41, Cb42 and Cb43 of the feedback path to the integrator 4 from the integrator 5 are connected together in a T-shape with its feedback gain set at 3/16 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta-sigma modulator (hereinafter referred to as "delta-sigma modulator"), and more particularly to a delta-sigma modulator constructed by using a switched capacitor circuit.

[0002]

2. Description of the Related Art As is conventionally known, noise shaping for reducing quantization noise in a base band in a ΔΣ modulator is more effective as the number of integrators connected in cascade is increased. In particular, in a second-order or higher ΔΣ modulator, a zero point can be created at a frequency other than dc during the quantization noise shape in order to further reduce the quantization noise in the baseband. Such a zero point is created by adding a feedback system (so-called local feedback) that includes two or more of the integrators connected in cascade and does not pass through the quantizer.

FIG. 3 is a block diagram showing the operation in a discrete value system (Z region) in such a fourth-order ΔΣ modulator. In this figure, four integrators 1 to 4 are connected in cascade, and the amount of attenuation of each integrator is k ₁ to k ₄ . Then, there are feedforward stages 6 to 9 from the respective integrators 1 to 4 to the adder 5, and the respective gains are a ₁ to
a ₄ . Each feedforward stage has a delay Z ^-1 . These feedforward stages are for independent control of the gain (ie time constant) of each order loop. This gain is determined by the product of the amount of attenuation of the integrators cascaded in the loop and the gain of the feedforward stage.

The output of the adder 5 is input to the quantizer 10 and quantized. Here, the quantizer 10 is modeled by a gain stage 11 of a gain a ₀ , an addition stage 12 of a quantization noise Qz, and a delay stage (Z ⁻¹ ) 13. Quantizer 10
The output of is subtracted from the input of the ΔΣ modulator, which results in Δ
The entire Σ modulator constitutes a negative feedback loop.

There is a negative feedback loop (ie, local feedback 17) that subtracts from the input of integrator 3 through the feedback gain stage b ₁ from the output of integrator 4. This local feedback 17 is for creating a zero point other than dc in the quantization noise shape. This feedback stage has a delay (Z ⁻¹ ) 16.

Next, the process of obtaining the zero-point frequency of the fourth-order ΔΣ modulator shown in FIG. 3 will be described.

When the loop filter section of the ΔΣ modulator in FIG. 3 is replaced with the block H (Z), the result is as shown in FIG. At this time, the transfer function of the loop filter H (Z) is

[0008]

[Equation 1]

When the transfer function of the entire modulator is obtained using this H (Z), and the formula in the Z region is converted into the s region,

[0010]

[Equation 2]

Is given by

Here, the brackets [] in the above equation (2)
Represents the transfer function of the quantization noise.

From the transfer function of the above quantization noise, the zero point is

[0014]

[Equation 3]

Is given by This allows

[0016]

[Equation 4]

There are two zero points at DC and one set of conjugate complex roots.

The frequency f (z) of the zero point due to the conjugate complex root is obtained from the equation (4) as follows.

If 1 / T is fs,

[0020]

[Equation 5]

As a result of the above calculation, there is one set of zero points of the complex conjugate root other than dc, and its frequency is given by equation (5).

In a CMOS LSI, such a ΔΣ modulator is composed of a switched capacitor circuit. FIG. 5 shows the block diagram of FIG. 3 in the form of a switched capacitor circuit.

FIG. 6 is a timing chart showing the operation of the fourth-order ΔΣ modulator shown in FIG.

In the case of such a switched capacitor circuit, the amount of attenuation of the integrator is determined by the ratio of the integral capacity and the sampling capacity. For example, in the case of the integrator 3, k ₃ = C _i3
/ C _s3 . The gain b ₁ of the local feedback ratio of the feedback capacitance C _b3 and C _s3 C _b3 / C _s3
Depends on.

[0025]

In such a ΔΣ modulator, since the ratio of the sampling frequency to the baseband frequency is large, b ′ in the equation (5) is not small in order to make a zero point in the baseband. must not. The b 'for the smaller, the integrator attenuation k _3, k ₄ be increased or, it is conceivable to reduce the gain b ₁ of the feedback stage.

Now, _let us consider a method for reducing b ', assuming that the sampling capacitances of C _s3 and C _s4 in FIG. 5 are fixed to a certain unit capacitance whose analog noise or precision of the integrator is determined by the constant.

First, increasing k ₃ and k ₄ means increasing C _i3 and C _i4 , increasing the area occupied by the integrator and increasing the parasitic capacitance between the integrating capacitor and the silicon substrate. The load on the operational amplifier increases. Further, the attenuation amount of the integrators 3 and 4 is related to the stability of the ΔΣ modulator by controlling the gain of the loop of the third order or more in the ΔΣ modulator, and therefore cannot be determined only by the convenience of the zero point. .

In order to reduce the gain b _{1 of the} feedback stage, the feedback capacitance C _b3 must be sufficiently smaller than C _s3 . In a switched capacitor circuit, the gain is determined by the capacitance ratio. Further, in the CMOS process, the capacitance ratio is affected by the random error of the process. The influence of this random error is less likely to occur as the capacitance area increases.

Therefore, reducing the value of C _b3 reduces the accuracy of the gain b ₁ . Also, the LS to be used
Since a capacity smaller than the minimum size determined by the I process cannot be produced, there is a limit to the capacity ratio that can be achieved even if the accuracy is sacrificed.

On the contrary, if C _b3 is fixed to the unit capacity so as not to reduce the accuracy of the gain b ₁ , C _s3 and C _i3 are also increased in order to maintain b ₁ and k ₃ , so that the area is increased and the calculation is performed. This will increase the load on the increaser.

As described above, the conventional technique has a drawback that the circuit area and the load of the operational amplifier are increased or the zero point is controlled at the expense of the feedback gain accuracy. In addition, there is a defect that there is no freedom to decide the attenuation amount of the integrated value only by the stability of the ΔΣ modulator.

Therefore, an object of the present invention is to provide a ΔΣ modulator in which the above-mentioned conventional drawbacks are eliminated.

[0033]

According to the present invention, in a delta-sigma modulator constructed by using a switched capacitor circuit, a loop filter of second order or higher is provided, and a feedback section is provided in the loop filter. As the capacitance that regulates the gain of the feedback unit, 3
The capacitance of each is T-type connection.

[0034]

According to the above configuration of the present invention, in a ΔΣ modulator having a quadratic loop filter, feedback exists in the loop filter for the purpose of creating a zero point other than dc in the quantization noise shape. And yet Δ
When the Σ modulator is composed of a switched capacitor circuit, the capacitance for controlling the feedback gain is realized by connecting three capacitances in a T-shape.

By connecting the three capacitors in a T-shape in this way, an equivalently small capacitor can be produced. As a result, a large capacitance ratio that sufficiently reduces the gain of the feedback stage can be realized without degrading accuracy.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a ΔΣ modulator according to an embodiment of the present invention, as described in detail below, an equivalent small capacity can be produced by connecting three capacitors in a T-shape. As a result, a large capacitance ratio that sufficiently reduces the gain of the feedback stage can be realized without degrading accuracy.

First, the reason will be described with reference to FIGS. 7 and 8.

FIG. 7 shows a typical switched capacitor integrator. Frequency f of unit gain in integrator
u is a sampling frequency fs,

[0039]

[Equation 6]

Is given by

The time constant τ is

[0042]

[Equation 7]

Is given by

FIG. 8 shows a switched capacitor integrator using a T-connection of capacitance.

In this integration,

[0046]

[Equation 8]

In the above equation, the capacitance of C ₁ and C ₃ is 1, and C
_If the capacitance of ₄ is 8,

[0048]

[Equation 9]

Therefore, equivalently, a capacitance of 1/10 can be obtained.

The capacitance of C ₄ shown in FIG. 8 increases in inverse proportion to the feedback gain in order to reduce the feedback capacitance equivalently. That is, the area occupied by the feedback capacitance increases as C ₄ increases.

However, in the case of the ΔΣ modulator, since the attenuation amount of the integrator is generally 1 or more, when the feedback capacity is fixed to the unit capacity and the accuracy is to be maintained, the integration is performed from the ratio of increasing the sampling capacity. Since the capacity is further increased, the above-described method of the present invention is advantageous in area. Further, the settling load of the operational amplifier used in the integrator becomes lighter when the sampling capacitance is fixed to the unit capacitance and the feedback capacitance is equivalently reduced by the T-shaped connection.

FIG. 1 is an embodiment of a ΔΣ modulator to which the present invention is applied, and FIG. 2 is a timing chart showing the operation of the embodiment.

The embodiment shown in FIG. 1 is a fifth-order ΔΣ modulator composed of a switched capacitor circuit. There are now two local feedbacks from the output of integrator 3 to the input of integrator 2 and from the output of integrator 5 to the input of integrator 4. That is, there are two sets of zero points of the complex conjugate root in the quantization noise shape.

The feedback capacitance in each local feedback is constituted by a T-connection of three capacitors. In this circuit, the feedback gain b ₁ from the output of the integrator 3 to the input of the integrator 2 is 1/32.
It is given by the following formula.

[0055]

[Equation 10]

Here, the sampling capacitance C _s2 is a capacitance determined by the analog noise constant. Since 1/32 of C _s2 is smaller than the minimum size of the process used and cannot be realized, the T-type connection method was adopted.

The feedback gain b ₂ from the output of the integrator 5 to the input of the integrator 4 is 3/16 and is given by the following equation.

[0058]

[Equation 11]

In the circuit shown in FIG. 1, the amount of attenuation of the integrator 4 is as large as 16. Therefore, in order not to increase the circuit area, the sampling capacitance C _s4 here is the minimum capacitance determined by the accuracy _constraint of the integrator attenuation amount. Therefore, in order to realize an accurate feedback gain b ₂ without changing the capacitance of C _s4, a T-type connection method is adopted here.

If, here, in order to improve the accuracy of b ₂ , T
If the feedback capacitance is increased by the conventional method instead of the type connection, C _s4 becomes 16/3 times as large, and the integral capacitance C _i4 becomes 16 times as large as that. Therefore, the circuit area and the load of the operational amplifier increase. Is remarkable.

_Thus , by selecting the capacitances of C _b21 , C _b22 , C _b23 and C _b41 , C _b42 , C _b43 ,
It is possible to control two sets of zero points without changing the capacitances of C _s2 and C _s4 and maintaining the degree of freedom of the attenuation amount of the integrators 2 to 5.

The switch capacitors and switches shown in FIG. 1 use NMOS semiconductor switches in this embodiment, but it goes without saying that they can be replaced with other switching means.

[0063]

As described above, according to the present invention, the zero point in the quantization noise shape for the purpose of reducing the quantization noise in the base band is accurately considered and the minimum size of the use process is taken into consideration. It can be controlled without having to. Further, it is also advantageous in reducing the area of the circuit and reducing the load of the operational amplifier as compared with the conventional method. Further, the degree of freedom for controlling the zero point can be obtained without being affected by the amount of attenuation of the integrator in the loop.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a fifth-order ΔΣ modulator according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation of the circuit shown in FIG.

FIG. 3 is a block diagram showing a commonly known fourth-order ΔΣ modulator.

FIG. 4 is a diagram in which the loop filter unit in FIG. 3 is replaced with a block H (Z).

5 is a diagram obtained by converting the block diagram of FIG. 3 into a switched capacitor circuit.

FIG. 6 is a timing diagram showing the operation of FIG.

FIG. 7 is a diagram showing a general switched capacitor integrator.

FIG. 8 is a diagram showing a switched capacitor integrator for explaining the principle of the present invention.

[Explanation of symbols]

a ₀ Comparator gain k _{1 to} k ₄ Integrator attenuation amount a _{1 to} a ₄ Feedback forward gain b ₁ Feedback gain

Claims (1)

[Claims] 1. A delta-sigma modulator configured by using a switched capacitor circuit, which has a loop filter of a second order or higher and a feedback section in the loop filter, the static value defining a gain of the feedback section. A delta-sigma modulator having three capacitances connected in a T-shape as capacitance.