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JPH06120305A - Jig for testing electrical characteristics of semiconductor devices - Google Patents

Jig for testing electrical characteristics of semiconductor devices

Info

Publication number
JPH06120305A
JPH06120305A JP4263393A JP26339392A JPH06120305A JP H06120305 A JPH06120305 A JP H06120305A JP 4263393 A JP4263393 A JP 4263393A JP 26339392 A JP26339392 A JP 26339392A JP H06120305 A JPH06120305 A JP H06120305A
Authority
JP
Japan
Prior art keywords
semiconductor device
jig
solder ball
inspection jig
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4263393A
Other languages
Japanese (ja)
Inventor
Takayoshi Miyazaki
高好 宮崎
Chiyouichirou Mizuno
長市郎 水野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4263393A priority Critical patent/JPH06120305A/en
Publication of JPH06120305A publication Critical patent/JPH06120305A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

(57)【要約】 【目的】 半導体装置を損傷させることなく、非パッケ
ージング状態の半導体装置の電気的特性検査を確実に行
い得る検査用治具を提供する。 【構成】 半田ボール電極50を受ける凹部10を治具
本体1の対応する箇所に設け、凹部10の内面をすり鉢
状導電層13Aと円筒状導電層13Bで被うとともに、
円筒状導電層13Bに引出し配線14を介して外部電極
12を電気的に接続させることによって、凹部10に電
気的に接触させた半田ボール電極50と外部電極12と
を導電接続する。また、真空経路11を真空吸引装置6
で真空に引くことによって、治具本体1に半導体装置5
を引き付けるようにした。 【効果】 真空吸引によって検査用治具に半導体装置が
引き付けられるので、検査用治具と半田ボール電極との
電気的な接触が確実に行われるのに加えて、検査用治具
と半導体装置との間に位置ずれが生じるのが防止され
る。
(57) [Summary] [Object] To provide an inspection jig capable of surely inspecting the electrical characteristics of a semiconductor device in a non-packaged state without damaging the semiconductor device. A recess 10 for receiving the solder ball electrode 50 is provided at a corresponding position of the jig body 1, and the inner surface of the recess 10 is covered with a mortar-shaped conductive layer 13A and a cylindrical conductive layer 13B.
By electrically connecting the external electrode 12 to the cylindrical conductive layer 13B via the lead wiring 14, the solder ball electrode 50 electrically contacting the recess 10 and the external electrode 12 are conductively connected. In addition, the vacuum path 11 is connected to the vacuum suction device 6
By pulling a vacuum with
I tried to attract. [Effect] Since the semiconductor device is attracted to the inspection jig by the vacuum suction, the inspection jig and the solder ball electrode can be reliably electrically contacted with each other, and the inspection jig and the semiconductor device can be connected to each other. It is possible to prevent the positional deviation from occurring.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体技術さらには半
導体装置の検査技術に適用して特に有効な技術に関し、
例えば半田ボール電極を有する半導体装置の電気的特性
検査に利用して有用な検査用治具に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology and a technology particularly effective when applied to a semiconductor device inspection technology.
For example, the present invention relates to an inspection jig useful for inspecting electrical characteristics of a semiconductor device having a solder ball electrode.

【0002】[0002]

【従来の技術】従来、高集積回路の形成された半導体装
置は樹脂やセラミックなどで封止された半導体パッケー
ジの状態でユーザーに出荷されるため、出荷直前に行う
半導体装置の電気的特性の完成検査は、非パッケージン
グ状態の半導体装置単体ではなく、半導体装置をパッケ
ージに封入した半導体パッケージの状態で行われてい
た。すなわち、半導体パッケージの各リードに、検査装
置に設けられた検査用の各端子を電気的に接続し、これ
ら各端子及び各リードを介して、検査装置と半導体装置
の各電極との間で電気信号の授受を行うことによって、
電気的特性を測定していた。リードと端子との接続につ
いては、例えば、リードとして半田ボール電極が用いら
れている表面実装用の半導体パッケージの場合には、そ
の半田ボール電極に検査装置の端子となるプローブ針を
ばね等を用いて機械的に押圧させて行っている。
2. Description of the Related Art Conventionally, a semiconductor device on which a highly integrated circuit is formed is shipped to a user in the state of a semiconductor package sealed with a resin or ceramic. The inspection has been performed in the state of a semiconductor package in which the semiconductor device is enclosed in a package, not in the unpackaged semiconductor device alone. That is, each of the leads of the semiconductor package is electrically connected to each of the terminals for inspection provided in the inspection device, and the terminals of the inspection device and the electrodes of the semiconductor device are electrically connected to each other through the terminals and the leads. By exchanging signals,
The electrical characteristics were measured. Regarding the connection between the lead and the terminal, for example, in the case of a semiconductor package for surface mounting in which a solder ball electrode is used as the lead, a probe needle to be the terminal of the inspection device is used with a spring or the like for the solder ball electrode. It is mechanically pressed.

【0003】ところで、近年、半導体装置を実装した様
々の製品の更なる小型化を図るため、それら製品の実装
ボードに非パッケージング状態の半導体装置、すなわち
半導体チップをそのまま実装する技術が考えられてい
る。この様なチップダイレクト実装技術においては、半
導体装置の各電極上に半田ボール電極(半田バンプ)を
形成したフリップチップ形式の半導体装置が用いられ
る。
By the way, in recent years, in order to further miniaturize various products on which semiconductor devices are mounted, a technique of mounting unpackaged semiconductor devices, that is, semiconductor chips on the mounting boards of those products has been considered. There is. In such a chip direct mounting technique, a flip chip type semiconductor device in which a solder ball electrode (solder bump) is formed on each electrode of the semiconductor device is used.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上述し
た半導体パッケージにおける電気的特性の検査技術を適
用して、非パッケージング状態における半導体装置の電
気的特性を検査するには、以下に述べる様な問題点があ
る。すなわち、その問題点とは、半導体装置における半
田ボール電極の大きさ及びピッチ(相互に隣接する半田
ボール電極間の距離)が半導体パッケージの半田ボール
電極の大きさ及びピッチに比べて極めて小さいため、全
プローブ針を全半田ボール電極に確実に接触させて、そ
れらを電気的に接続することが非常に困難であるだけで
なく、半導体装置が所定位置からわずかにずれただけ
で、プローブ針の先端で半導体装置の表面を傷付けた
り、半導体装置の表面を汚染する虞があるというもので
ある。
However, in order to inspect the electrical characteristics of the semiconductor device in the non-packaging state by applying the above-described technique for inspecting the electrical characteristics of the semiconductor package, the following problems are encountered. There is a point. That is, the problem is that the size and pitch of the solder ball electrodes in the semiconductor device (distance between the solder ball electrodes adjacent to each other) is extremely smaller than the size and pitch of the solder ball electrodes of the semiconductor package. Not only is it very difficult to make sure that all probe needles are in contact with all solder ball electrodes and to electrically connect them, but the tip of the probe needle is only slightly displaced from the semiconductor device. Therefore, the surface of the semiconductor device may be damaged or the surface of the semiconductor device may be contaminated.

【0005】本発明はかかる事情に鑑みてなされたもの
で、その使用により半導体装置を損傷させることなく、
非パッケージング状態の半導体装置の電気的特性検査を
確実に行い得る半導体装置の電気的特性の検査用治具を
提供することを主たる目的としている。この発明の前記
ならびにそのほかの目的と新規な特徴については、本明
細書の記述及び添附図面から明らかになるであろう。
The present invention has been made in view of the above circumstances, and the use thereof does not damage a semiconductor device,
It is a main object to provide a jig for inspecting electric characteristics of a semiconductor device, which can surely inspect the electric characteristics of a semiconductor device in a non-packaging state. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0006】[0006]

【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を説明すれば、下記のと
おりである。すなわち、本発明の半導体装置の電気的特
性の検査用治具においては、半導体装置の半田ボール電
極を受ける凹部を治具本体の対応する箇所に設け、その
凹部の内面を金属薄膜で被うとともに、その金属薄膜に
引出し配線を介して外部電極を電気的に接続させること
によって、凹部に電気的に接触させた半田ボール電極と
外部電極とを導電接続する。また、凹部に連通接続され
た真空経路を真空吸引装置に接続することによって、凹
部と半田ボール電極とで閉塞される空間を真空吸引する
構成とした。
The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the jig for inspecting the electrical characteristics of the semiconductor device of the present invention, a concave portion for receiving the solder ball electrode of the semiconductor device is provided in a corresponding portion of the jig body, and the inner surface of the concave portion is covered with a metal thin film. By electrically connecting the external electrode to the metal thin film via the lead wiring, the solder ball electrode electrically contacting the recess and the external electrode are conductively connected. Further, by connecting a vacuum path communicating with the recess to a vacuum suction device, the space closed by the recess and the solder ball electrode is vacuum-sucked.

【0007】[0007]

【作用】上記した手段の検査用治具を用いれば、治具本
体の凹部に半導体装置の半田ボール電極が電気的に接触
した状態で入り込み、真空吸引によって、検査用治具に
半導体装置が引き付けられる。
If the inspection jig of the above-mentioned means is used, the solder ball electrode of the semiconductor device enters into the concave portion of the jig body in an electrically contacting state, and the semiconductor device is attracted to the inspection jig by vacuum suction. To be

【0008】[0008]

【実施例】(第1実施例)本発明に係る半導体装置の電
気的特性の検査用治具(以下、単に「検査用治具」とす
る。)の第1実施例を図1乃至図4に示し、以下に説明
する。それらのうち、図1は検査用治具が半導体装置に
取り付けられた状態の縦断面図、図2は図1の部分拡大
縦断面図、図3は検査用治具の要部断面斜視図、図4は
検査用治具が接続された検査装置の概略図である。
(First Embodiment) A first embodiment of a jig for inspecting electric characteristics of a semiconductor device according to the present invention (hereinafter simply referred to as "inspection jig") will be described with reference to FIGS. And described below. Among them, FIG. 1 is a vertical cross-sectional view of a state in which an inspection jig is attached to a semiconductor device, FIG. 2 is a partially enlarged vertical cross-sectional view of FIG. 1, and FIG. FIG. 4 is a schematic diagram of an inspection device to which an inspection jig is connected.

【0009】この検査用治具100は半田ボール電極5
0を有する半導体装置5の電気的特性検査に用いられる
検査用の治具であり、その治具本体1は、図1に示すよ
うに、特にその数を限定しないが、例えば4層のパネル
からなる多層構造をしていて、半導体装置5に対向する
第1層目の表層パネル1Aと、第2層目以下の配線層パ
ネル1B,1C,1Dとからできている。そして、表層
パネル1Aには、半田ボール電極50に電気的に接触可
能な凹部10が、半田ボール電極50に対応して複数の
箇所に設けられているとともに、半田ボール電極50で
閉塞される各凹部10内を真空に引く真空経路11が設
けられている。また、治具本体1の裏面、すなわち第4
層目の配線層パネル1Dの表面には、凹部10に電気的
に接続された外部電極12が少なくとも凹部10に対応
した数だけ露出して設けられている。
This inspection jig 100 has a solder ball electrode 5
The jig body 1 is an inspection jig used to inspect the electrical characteristics of the semiconductor device 5 having 0, and the jig body 1 is not particularly limited in its number as shown in FIG. It has a multi-layered structure and is made up of a first-layer surface layer panel 1A facing the semiconductor device 5 and second-layer and lower wiring layer panels 1B, 1C, 1D. Further, the surface layer panel 1A is provided with the recesses 10 capable of electrically contacting the solder ball electrodes 50 at a plurality of positions corresponding to the solder ball electrodes 50, and each of the recesses 10 is closed by the solder ball electrodes 50. A vacuum path 11 that draws a vacuum in the recess 10 is provided. In addition, the back surface of the jig body 1, that is, the fourth
External electrodes 12 electrically connected to the recesses 10 are provided on the surface of the wiring layer panel 1D of the second layer so as to be exposed at least by the number corresponding to the recesses 10.

【0010】前記凹部10は、図2及び図3に示すよう
に、半田ボール電極50を受ける受け部10Aに貫通部
10Bが連通接続されてできている。受け部10Aは、
すり鉢状に成形されていて、表層パネル1Aの表面1a
においては半田ボール電極50よりも大きな径で開口し
ているとともに、配線層パネル1Bに向かうに連れて徐
々にその径が小さくなっている。貫通部10Bは空洞に
なっていて、表層パネル1Aを上下に貫通している。受
け部10Aおよび貫通部10Bの内面は、それぞれ例え
ば金属などの導電体からなる連続したすり鉢状導電層1
3Aと円筒状導電層13Bで被われていて、すり鉢状導
電層13Aに半田ボール電極50が電気的に接触するよ
うになっている。
As shown in FIGS. 2 and 3, the recess 10 is formed by connecting a through portion 10B to a receiving portion 10A for receiving the solder ball electrode 50. The receiving portion 10A is
It is shaped like a mortar and the surface 1a of the surface panel 1A
In, the opening has a diameter larger than that of the solder ball electrode 50, and the diameter gradually decreases toward the wiring layer panel 1B. The penetrating portion 10B is hollow and vertically penetrates the surface layer panel 1A. The inner surfaces of the receiving portion 10A and the penetrating portion 10B are respectively continuous mortar-shaped conductive layers 1 made of a conductor such as metal.
It is covered with 3A and the cylindrical conductive layer 13B so that the solder ball electrode 50 electrically contacts the mortar-shaped conductive layer 13A.

【0011】前記真空経路11は、表層パネル1Aの内
部において、表層パネル1Aに凹設された全ての凹部1
0,…の前記貫通部10B,…に連通接続されている。
そして、その終端11aは、検査用治具100の外部に
設けられるロータリーポンプなどの真空吸引装置6(図
4参照)にチューブ60を介して接続されるようになっ
ている。
The vacuum path 11 has all the recesses 1 formed in the surface layer panel 1A inside the surface layer panel 1A.
0, ... Are connected to the through portions 10B ,.
The terminal end 11a is connected to a vacuum suction device 6 (see FIG. 4) such as a rotary pump provided outside the inspection jig 100 via a tube 60.

【0012】前記外部電極12は、検査用治具100の
外部に設けられる測定装置7(図4参照)の接続端子7
0を電気的に接続するためのもので、前記凹部10の前
記円筒状導電層13Bに多層配線構造の引出し配線14
によって導電接続されている。すなわち、円筒状導電層
13Bの終端から、表層パネル1Aと配線層パネル1B
との境界部分に一層目の横配線部14A(配線層)が設
けられ、配線層パネル1B,1Cの境界部分、および配
線層パネル1C,1Dの境界部分に、夫々、二層目の横
配線部14B(配線層)、および三層目の横配線部14
C(配線層)が設けられている。一層目の横配線部14
Aと二層目の横配線部14B、二層目の横配線部14B
と三層目の横配線部14C、三層目の横配線部14Cと
外部電極12とは、それぞれ、配線層パネル1B,1
C,1Dを上下に貫通する縦配線部14D,14E,1
4Fによって電気的に接続されている。
The external electrodes 12 are connection terminals 7 of a measuring device 7 (see FIG. 4) provided outside the inspection jig 100.
0 is electrically connected to the cylindrical conductive layer 13B of the concave portion 10 and has a lead wiring 14 of a multilayer wiring structure.
Conductive connection by. That is, from the end of the cylindrical conductive layer 13B to the surface layer panel 1A and the wiring layer panel 1B.
The horizontal wiring portion 14A (wiring layer) of the first layer is provided at the boundary portion between the wiring layer panels 1B and 1C and the boundary portion of the wiring layer panels 1C and 1D. Portion 14B (wiring layer) and the horizontal wiring portion 14 of the third layer
C (wiring layer) is provided. First horizontal wiring section 14
A, horizontal wiring portion 14B of the second layer, horizontal wiring portion 14B of the second layer
And the horizontal wiring portion 14C of the third layer, and the horizontal wiring portion 14C of the third layer and the external electrode 12, respectively.
Vertical wiring portions 14D, 14E, 1 vertically penetrating C, 1D
It is electrically connected by 4F.

【0013】なお、前記測定装置7は、図4に示すよう
に、コンピュータなどの制御装置8に接続されて、その
制御装置8によってオン/オフや大きさが制御された電
流や電圧等の電気信号を、検査用治具100の各外部電
極12,…に出力するようになっている。また、その出
力した電気信号によって半導体装置5内に引き起こされ
る電流や電圧等の電気信号を検出して制御装置8に出力
するようになっている。制御装置8には、キーボード等
の操作装置80及びディスプレイ等の表示装置85が接
続されているのはいうまでもない。これら測定装置7、
制御装置8、前記真空吸引装置6および当該検査用治具
100によって、検査装置が構築されている。
As shown in FIG. 4, the measuring device 7 is connected to a control device 8 such as a computer, and the control device 8 turns on / off the electric power such as current and voltage whose magnitude is controlled. A signal is output to each external electrode 12, ... Of the inspection jig 100. Further, an electric signal such as a current or a voltage caused in the semiconductor device 5 is detected by the outputted electric signal and is outputted to the control device 8. It goes without saying that the control device 8 is connected with an operation device 80 such as a keyboard and a display device 85 such as a display. These measuring devices 7,
An inspection device is constructed by the control device 8, the vacuum suction device 6, and the inspection jig 100.

【0014】次に、上述した構造の検査用治具100の
製造方法に付いて説明する。先ず、ガラス板材などでで
きた絶縁性を有する表層パネル1Aに、受け部10Aお
よび貫通部10Bを孔開け加工して、凹部10を形成す
るとともに、真空経路11を孔開け加工して設けた後、
その凹部10を、スパッタリング法等のPVD(Physi
cal Vapor Deposition)法やCVD(Chemical Vap
or Deposition)法などにより、すり鉢状導電層13A
および円筒状導電層13Bで被覆する。或は、無電解め
っき法などですり鉢状導電層13Aおよび円筒状導電層
13Bを被覆させてもよい。
Next, a method of manufacturing the inspection jig 100 having the above structure will be described. First, after the receiving portion 10A and the penetrating portion 10B are perforated to form the concave portion 10 and the vacuum path 11 is perforated to the surface layer panel 1A having an insulating property made of a glass plate material or the like, ,
The recess 10 is formed by PVD (Physi
cal vapor deposition (CVD) and chemical vapor deposition (CVD)
mortar-shaped conductive layer 13A
And the cylindrical conductive layer 13B. Alternatively, the mortar-shaped conductive layer 13A and the cylindrical conductive layer 13B may be coated by an electroless plating method or the like.

【0015】次に、引出し配線14を、半導体装置にお
けるアルミニウム多層配線の形成技術と同様にして、形
成する。具体的には、表層パネル1Aの裏面1bにPV
D法やCVD法によりアルミニウムなどの導体層を被着
させ、ホトレジストを用いたホトリソグラフィ技術によ
り所定の配線パターンをした一層目の横配線部14Aを
形成する。しかる後、ホトレジストを除去してから、そ
の上に絶縁性を有するPIQ(Polyimido Isoindro
Quinazolinedione)などを塗布して配線層パネル1
Bを設けるとともに、ホトリソグラフィ技術およびエッ
チング等により配線層パネル1Bに上下に貫通する、縦
配線部14D用の貫通孔を設ける。さらに、ホトレジス
ト除去後、その上に、一層目の横配線部14Aと同様に
して、二層目の横配線部14Bを形成する。この時、縦
配線部14Dも作られる。
Next, the lead wiring 14 is formed in the same manner as the aluminum multi-layer wiring forming technique in the semiconductor device. Specifically, PV is provided on the back surface 1b of the surface layer panel 1A.
A conductor layer such as aluminum is deposited by the D method or the CVD method, and the first lateral wiring portion 14A having a predetermined wiring pattern is formed by the photolithography technique using a photoresist. Then, after removing the photoresist, PIQ (Polyimido Isoindro) having an insulating property is formed on the photoresist.
Quinazolinedione) etc. are applied and the wiring layer panel 1
Along with B, a through hole for the vertical wiring portion 14D is provided which vertically penetrates the wiring layer panel 1B by photolithography and etching. Further, after removing the photoresist, a second-layer horizontal wiring portion 14B is formed thereon in the same manner as the first-layer horizontal wiring portion 14A. At this time, the vertical wiring portion 14D is also made.

【0016】同様にして、配線層パネル1C,1D、三
層目の横配線部14C、縦配線部14E,14Fおよび
外部電極12を形成すれば、検査用治具100が出来あ
がる。
Similarly, if the wiring layer panels 1C and 1D, the horizontal wiring portion 14C of the third layer, the vertical wiring portions 14E and 14F and the external electrodes 12 are formed, the inspection jig 100 is completed.

【0017】以上のようにして作られた検査用治具10
0を使用する際には、図4に示すように、真空経路11
に真空吸引装置6のチューブ60を接続するとともに、
外部電極12に測定装置7の接続端子70を半田や導電
性ペーストなどで導電接続すればよい。
The inspection jig 10 produced as described above
When using 0, as shown in FIG.
While connecting the tube 60 of the vacuum suction device 6 to
The connection terminal 70 of the measuring device 7 may be conductively connected to the external electrode 12 with solder or a conductive paste.

【0018】(第2実施例)本発明に係る検査用治具の
第2実施例を図5および図6に示し、以下に説明する。
図5は検査用治具が半導体装置に取り付けられた状態の
縦断面図、図6は図5の部分拡大縦断面図である。な
お、第1実施例と同一の部材および装置等については同
一の符号を付し、その説明を省略する。
(Second Embodiment) A second embodiment of the inspection jig according to the present invention is shown in FIGS. 5 and 6 and will be described below.
FIG. 5 is a vertical sectional view showing a state in which the inspection jig is attached to the semiconductor device, and FIG. 6 is a partially enlarged vertical sectional view of FIG. The same members and devices as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

【0019】この検査用治具200が第1実施例の検査
用治具100と異なるのは、以下の点である。すなわ
ち、真空経路11を治具本体1の表面1aの凹部10以
外の部分に開口させ、治具本体1と半導体装置5との間
の隙間空間Aを真空に引くことによって、検査用治具2
00に半導体装置5を引き付けるようにした点である。
The inspection jig 200 differs from the inspection jig 100 of the first embodiment in the following points. That is, the inspection jig 2 is opened by opening the vacuum path 11 in a portion of the surface 1 a of the jig body 1 other than the recessed portion 10 and drawing a vacuum space A between the jig body 1 and the semiconductor device 5.
The point is that the semiconductor device 5 is attracted to 00.

【0020】真空経路11は、表面1aから真空経路1
1に達するように穴開け加工された真空縦穴部15,…
によって前記隙間空間Aに連通接続されている。この真
空縦穴部15,…は、半導体装置5の各半田ボール電極
50,…間に一つずつ位置するように設けられているの
が望ましい。
The vacuum path 11 extends from the surface 1a to the vacuum path 1
Vacuum vertical hole 15 that has been drilled to reach 1 ...
Is connected in communication with the gap space A. It is preferable that the vacuum vertical hole portions 15, ... Are provided so as to be located between the solder ball electrodes 50 ,.

【0021】また、凹部10の貫通部10Bは、凹部1
0のすり鉢状導電層13Aおよび一層目の横配線部14
Aに導電接続されたアルミニウムなどの導電体13Cで
埋められている。この導電体13Cは、すり鉢状導電層
13Aまたは一層目の横配線部14Aを被着させる時に
貫通部10Bに堆積されて作られる。なお、すり鉢状導
電層13Aと一層目の横配線部14Aとが導電接続され
れば、必ずしも貫通部10B全体に導電体13Cが充填
されている必要はない。
The penetrating portion 10B of the recess 10 is the recess 1
0 mortar-shaped conductive layer 13A and first lateral wiring portion 14
It is filled with a conductor 13C such as aluminum which is conductively connected to A. The conductor 13C is formed by being deposited on the through portion 10B when the mortar-shaped conductive layer 13A or the horizontal wiring portion 14A of the first layer is applied. If the mortar-shaped conductive layer 13A and the first lateral wiring portion 14A are conductively connected, the conductor 13C does not necessarily have to be filled in the entire penetrating portion 10B.

【0022】上記第1及び第2実施例によれば、凹部1
0に半導体装置5の半田ボール電極50が電気的に接触
した状態で入り込むとともに、真空経路11を介して真
空吸引装置6によって検査用治具100(200)に半
導体装置5が引き付けられるので、凹部10と半田ボー
ル電極50との電気的な接触が確実に行われ、電気的な
接触抵抗が小さくなるのに加えて、検査用治具100
(200)と半導体装置5との間に位置ずれが生じるの
が防止され、半導体装置5を損傷させることなく、半導
体装置5の電気的特性検査を確実に行うことができる。
According to the first and second embodiments described above, the recess 1
0 into the solder ball electrode 50 of the semiconductor device 5 in an electrically contacting state, and the semiconductor device 5 is attracted to the inspection jig 100 (200) by the vacuum suction device 6 via the vacuum path 11. The electrical contact between the solder ball electrode 10 and the solder ball electrode 50 is ensured, and the electrical contact resistance is reduced.
The positional deviation between (200) and the semiconductor device 5 is prevented from occurring, and the electrical characteristic inspection of the semiconductor device 5 can be reliably performed without damaging the semiconductor device 5.

【0023】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。例えば、上
記第1及び第2実施例においては、治具本体1は表層パ
ネル1Aおよび配線層パネル1B,1C,1Dからなる
4層構造になっているとしたが、これに限定されるもの
ではなく、3層以下または5層以上でもよいのはいうま
でもないし、表層パネル1Aのみからなる単層構造でも
よい。また、引出し配線14は多層配線構造になってい
るとしたが、凹部10と外部電極12とを電気的に接続
するとともに異なる引出し配線14,14同士が接触し
て電気的に短絡しなければ、如何様な構造になっていて
もよい。さらに、表層パネル1Aおよび配線層パネル1
B,1C,1Dは、電気的な絶縁性を有する材質であれ
ば、上記実施例のものに限らない。外部電極12、すり
鉢状導電層13A、円筒状導電層13B、導電体13C
および引出し配線14は、導電性を有していれば、上記
実施例のものに限らない。さらにまた、外部電極12に
測定装置7の接続端子70を半田などで導電接続する代
わりに、従来と同様に、外部電極12に検査装置の端子
となるプローブ針をばね等を用いて機械的に押圧させて
もよいのはいうまでもない。
Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above-described first and second embodiments, the jig body 1 has the four-layer structure including the surface layer panel 1A and the wiring layer panels 1B, 1C, 1D, but is not limited to this. Needless to say, the number of layers may be 3 or less or 5 or more, and may be a single-layer structure including only the surface layer panel 1A. Further, although the lead-out wiring 14 has a multilayer wiring structure, unless the recess 10 and the external electrode 12 are electrically connected and different lead-out wirings 14 and 14 are in contact with each other and electrically short-circuited, It may have any structure. Furthermore, the surface layer panel 1A and the wiring layer panel 1
B, 1C, and 1D are not limited to those in the above-described embodiment as long as they are materials having an electrical insulating property. External electrode 12, mortar-shaped conductive layer 13A, cylindrical conductive layer 13B, conductor 13C
The lead wiring 14 is not limited to that of the above embodiment as long as it has conductivity. Furthermore, instead of conductively connecting the connection terminal 70 of the measuring device 7 to the external electrode 12 by soldering or the like, a probe needle to be a terminal of the inspection device is mechanically connected to the external electrode 12 mechanically by using a spring or the like as in the conventional case. It goes without saying that they may be pressed.

【0024】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である非パッ
ケージング状態の半導体装置単体の電気的特性検査に適
用した場合について説明したが、この発明はそれに限定
されるものではなく、半導体装置を実装したパッケージ
ング状態の半導体装置の電気的特性検査に利用すること
ができる。
In the above description, the invention made by the present inventor was mainly applied to the electrical characteristic inspection of a single semiconductor device in a non-packaging state, which is the field of application of the invention. The present invention is not limited to this, and can be used for the electrical characteristic inspection of a packaged semiconductor device on which the semiconductor device is mounted.

【0025】[0025]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば下記
のとおりである。すなわち、非パッケージング状態の半
導体装置の電気的特性を測定する場合に、この検査用治
具を用いれば、治具本体の凹部に半導体装置の半田ボー
ル電極が電気的に接触した状態で入り込み、真空吸引に
よって、検査用治具に半導体装置が引き付けられるの
で、凹部と半田ボール電極との電気的な接触が確実に行
われ、電気的な接触抵抗が小さくなるのに加えて、検査
用治具と半導体装置との間に位置ずれが生じるのが防止
され、半導体装置を損傷させることなく、半導体装置の
電気的特性検査を確実に行うことができる。
The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, when measuring the electrical characteristics of a semiconductor device in a non-packaging state, if this inspection jig is used, the solder ball electrode of the semiconductor device enters the recess of the jig body in an electrically contacted state, Since the semiconductor device is attracted to the inspection jig by the vacuum suction, the concave portion and the solder ball electrode are surely electrically contacted with each other, and the electrical contact resistance is reduced. The positional deviation between the semiconductor device and the semiconductor device can be prevented, and the electrical characteristic inspection of the semiconductor device can be reliably performed without damaging the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】第1実施例における検査用治具が半導体装置に
取り付けられた状態の縦断面図である。
FIG. 1 is a vertical cross-sectional view of a state in which an inspection jig according to a first embodiment is attached to a semiconductor device.

【図2】図1の部分拡大縦断面図である。FIG. 2 is a partially enlarged vertical sectional view of FIG.

【図3】検査用治具の要部断面斜視図である。FIG. 3 is a cross-sectional perspective view of a main part of an inspection jig.

【図4】検査用治具が接続された検査装置の概略図であ
る。
FIG. 4 is a schematic diagram of an inspection device to which an inspection jig is connected.

【図5】第2実施例における検査用治具が半導体装置に
取り付けられた状態の縦断面図である。
FIG. 5 is a vertical cross-sectional view showing a state in which an inspection jig according to a second embodiment is attached to a semiconductor device.

【図6】図5の部分拡大縦断面図である。6 is a partially enlarged vertical sectional view of FIG.

【符号の説明】[Explanation of symbols]

1 治具本体 1A 表層パネル(パネル) 1B,1C,1D 配線層パネル(パネル) 6 真空吸引装置 10 凹部 11 真空経路 12 外部電極 13A すり鉢状導電層(導電層) 13B 円筒状導電層(導電層) 14A,14B,14C 横配線部(配線層) 14 引出し配線 50 半田ボール電極 100,200 検査用治具 1 jig body 1A surface layer panel (panel) 1B, 1C, 1D wiring layer panel (panel) 6 vacuum suction device 10 recessed portion 11 vacuum path 12 external electrode 13A mortar-shaped conductive layer (conductive layer) 13B cylindrical conductive layer (conductive layer) ) 14A, 14B, 14C horizontal wiring portion (wiring layer) 14 lead wiring 50 solder ball electrode 100, 200 inspection jig

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 治具本体の一面に半田ボール電極に対応
して複数の凹部が形成され、この凹部の内面には前記半
田ボール電極に電気的に接触可能な導電層が形成されて
いるとともに、治具本体の他の面には前記凹部に対応し
た数の外部電極が、また治具本体内には上記各凹部内の
導電層と外部電極とを電気的に接続する引出し配線が形
成されていることを特徴とする半導体装置の電気的特性
の検査用治具。
1. A plurality of recesses are formed on one surface of the jig body in correspondence with the solder ball electrodes, and a conductive layer electrically contacting the solder ball electrodes is formed on the inner surface of the recesses. A number of external electrodes corresponding to the recesses are formed on the other surface of the jig body, and lead wires for electrically connecting the conductive layers in the recesses to the external electrodes are formed in the jig body. A jig for inspecting the electrical characteristics of a semiconductor device.
【請求項2】 前記治具本体内には、真空吸引装置に接
続可能で、前記凹部と前記半田ボール電極とで閉塞され
る空間を真空吸引する真空経路が設けられていることを
特徴とする請求項1記載の半導体装置の電気的特性の検
査用治具。
2. A vacuum path, which is connectable to a vacuum suction device and vacuum-sucks a space closed by the recess and the solder ball electrode, is provided in the jig body. A jig for inspecting the electrical characteristics of the semiconductor device according to claim 1.
【請求項3】 上記治具本体は複数のパネルが積層され
てなり、前記凹部内の各導電層と前記外部電極とは各パ
ネルにそれぞれ形成された配線層からなる多層配線構造
の引出し配線を介して接続されていることを特徴とする
請求項1または2記載の半導体装置の電気的特性の検査
用治具。
3. The jig body is formed by stacking a plurality of panels, and each of the conductive layers in the recess and the external electrode has a lead wiring of a multi-layer wiring structure including a wiring layer formed in each panel. 3. The jig for inspecting the electrical characteristics of a semiconductor device according to claim 1, wherein the jig is connected through the jig.
JP4263393A 1992-10-01 1992-10-01 Jig for testing electrical characteristics of semiconductor devices Pending JPH06120305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4263393A JPH06120305A (en) 1992-10-01 1992-10-01 Jig for testing electrical characteristics of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4263393A JPH06120305A (en) 1992-10-01 1992-10-01 Jig for testing electrical characteristics of semiconductor devices

Publications (1)

Publication Number Publication Date
JPH06120305A true JPH06120305A (en) 1994-04-28

Family

ID=17388874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4263393A Pending JPH06120305A (en) 1992-10-01 1992-10-01 Jig for testing electrical characteristics of semiconductor devices

Country Status (1)

Country Link
JP (1) JPH06120305A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882169B2 (en) 1997-09-19 2005-04-19 Fujitsu Limited Semiconductor testing device
JP2006208208A (en) * 2005-01-28 2006-08-10 Mitsubishi Electric Corp Testing jig
KR100675008B1 (en) * 2006-01-27 2007-01-29 삼성전자주식회사 Test Sockets, Test Circuits and Test Methods
WO2009130737A1 (en) * 2008-04-21 2009-10-29 富士通株式会社 Substrate for inspection, method for manufacturing substrate for inspection, and inspection method using the substrate for inspection
JP2015108625A (en) * 2013-12-03 2015-06-11 エルジー エレクトロニクス インコーポレイティド Solar cell measuring device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882169B2 (en) 1997-09-19 2005-04-19 Fujitsu Limited Semiconductor testing device
US7161370B2 (en) 1997-09-19 2007-01-09 Fujitsu Limited Semiconductor testing device
JP2006208208A (en) * 2005-01-28 2006-08-10 Mitsubishi Electric Corp Testing jig
JP4509811B2 (en) * 2005-01-28 2010-07-21 三菱電機株式会社 Inspection jig
KR100675008B1 (en) * 2006-01-27 2007-01-29 삼성전자주식회사 Test Sockets, Test Circuits and Test Methods
WO2009130737A1 (en) * 2008-04-21 2009-10-29 富士通株式会社 Substrate for inspection, method for manufacturing substrate for inspection, and inspection method using the substrate for inspection
US20100264951A1 (en) * 2008-04-21 2010-10-21 Fujitsu Limited Interconnection card for inspection, manufacture method for interconnection card, and inspection method using interconnection card
JPWO2009130737A1 (en) * 2008-04-21 2011-08-04 富士通株式会社 Inspection substrate, inspection substrate manufacturing method, and inspection method using the inspection substrate
US8330480B2 (en) 2008-04-21 2012-12-11 Fujitsu Limited Interconnection card for inspection, manufacture method for interconnection card, and inspection method using interconnection card
US9476914B2 (en) 2008-04-21 2016-10-25 Fujitsu Limited Interconnection card for inspection, manufacture method for interconnection card, and inspection method using interconnection card
JP2015108625A (en) * 2013-12-03 2015-06-11 エルジー エレクトロニクス インコーポレイティド Solar cell measuring device
US9825585B2 (en) 2013-12-03 2017-11-21 Lg Electronics Inc. Solar cell measuring apparatus

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