JPH06119437A - Graphic plotter - Google Patents

Abstract

PURPOSE:To accelerate graphic plotting by reducing the number of times of memory access. CONSTITUTION:This device is provided with an address comparator 3 for detecting coincidence between plotting addresses A and AL of plural picture elements p1 and p2 in continuous plotting orders. Then, a plotting mask link circuit 4 is provided to output a link plotting mask MC of the plural picture elements p1 and p2 corresponding to an address coincident signal CA. Further, a plotting data link circuit 5 is provided to output link plotting data PC of the plural picture elements p1 and p2 similarly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic drawing device, and more particularly to a graphic drawing device for drawing a graphic on a display, a printer or the like.

[0002]

2. Description of the Related Art When a drawing command and a drawing parameter are received from a CPU, a drawing device generates a drawing address and drawing data by built-in hardware and firmware, and performs a memory access based on the drawing address and drawing data. Generate a graphic image on top.

FIG. 4 is a diagram showing a general example of the correspondence between each pixel forming a figure and the bit of the memory. That is, when the width of the data bus connecting the graphic drawing device and the memory is m (32 in this example), and the number of bits of one pixel is n (8 in this example), m / There will be n pixels. At this time, in order to specify a certain pixel, an address of a word (1 word is m bits) including this pixel and a drawing mask for specifying the position of the pixel in the word are used.

Each bit of the drawing mask has a one-to-one correspondence with each bit in the memory (D _{0- (m-1)} ) of the designated address. When the drawing data is written to the memory by accessing the memory, the drawing data is written to the bit in the memory corresponding to the bit of which the value of the drawing mask is 1 but in the memory corresponding to the bit of 0. Bit is masked during writing, indicating that the original value should be retained.

As shown in FIG. 5, the conventional graphic drawing apparatus 11 has an address generating circuit 21 for sequentially generating a drawing address which is an address of a word including a pixel position of a drawing target by a drawing command from the CPU 10 and the above word. Generation circuit 22 for generating a drawing mask that specifies the pixel position of
Memory control for controlling the memory 9 having a figure generating circuit 2 having a drawing data generating circuit 23 for generating drawing data at the pixel position and a drawing data synthesizing circuit 121 for outputting drawing addresses and synthesizing drawing data. Circuit 1
It was equipped with 2 and.

Next, the procedure of drawing the pixels p1 to p3 shown in FIG. 4 will be described as an example in accordance with the operation of the conventional graphic drawing apparatus.

The figure generation circuit 2 first generates the address 12001 for the drawing address A and ff000000H for the drawing mask M as the values corresponding to the pixel p1. Next, the memory control circuit 12 makes a read access to the memory 9 via the address bus 17 without changing the value of the drawing address A.
The value obtained by this read access is set to Di (0 ≦ i
≤31), the drawing data synthesizing circuit 121 calculates the synthetic drawing data DSi by the following equation.

DSi = Mi · Pi + BMi · Di where 0 ≦ i ≦ 31 (1) where BMi is the inverted value of Mi, Pi is the value of the drawing data P, and is the internal sequence of the figure generation circuit 2. Therefore, the color code corresponding to the pixel in the generated solid line or dotted line is shown.

The DSi obtained as a result of the equation (1) is newly written (written) to the address of the memory 9 designated by the drawing address A.

As a result, the value at address 12001 of the memory is in a state in which only the portion corresponding to the pixel p1 is rewritten by the drawing data.

Similarly, the drawing address A is 12001, the drawing mask M is 00ff0000H, and the pixel p2 is
Is rewritten, and then drawing address A is set to 12001
Set the address and drawing mask M to 0000ff00H and pixel p
Rewrite the part of 3.

The timing of the above operation is shown in FIG. Here, the figure generator 2 has the ability to calculate the information of the pixel to be drawn every cycle, and the memory control circuit 1
2 can read or write the memory 9 in one cycle.

The drawing information (drawing address A, drawing mask M, drawing data D) for the pixel p1 calculated by the figure generating circuit 2 during the T1 cycle is fetched into the memory control circuit 12 at the beginning of the T2 cycle and drawn at the drawing address A. The memory read cycle begins immediately for the address pointed to by. In the T3 cycle, the equation (1) is calculated using the memory value read in the T2 cycle, the drawing mask M, and the drawing data P, and the result is written back to the memory 9. Hereinafter, the procedure of "read / calculate / write" as performed in T2-T3 is referred to as read modify write.

On the other hand, the figure generation circuit 2 calculates the drawing information for the pixel p2 in the T2 cycle, but since the memory control circuit 12 cannot take in the drawing information in the T3 cycle, the next pixel information is calculated in the T3 cycle. Without doing so, it enters a wait state and holds drawing information for the pixel p2.

After the T4 cycle, T is calculated in units of two cycles.
The pattern is such that the 2-T3 cycle is repeated.
That is, in the T4 and T6 cycles, the memory control circuit 1
In step 2, the drawing information is fetched at the beginning of the cycle and the first half read access of the read modify write access is performed. Further, the figure generation circuit 2 calculates the next pixel information.
In cycles T5 and T7, the memory control circuit 12 performs the write access in the latter half of the read modify write access, and the figure generation circuit 2 is in the wait state.

Since the calculation time for calculating the position of the pixel to be drawn by the figure generation device is shorter than the drawing time for the memory control circuit to perform the read modify write access to the memory, the actual figure drawing time is the memory. It is considered to be proportional to the number of accesses. That is, the difference between the drawing time and the calculation time is the wait cycle of the figure generation circuit.

[0017]

The above-described conventional figure drawing apparatus draws a figure in units of one pixel when drawing a line figure. Therefore, when a plurality of pixels are drawn in one word. Has the drawback that the number of memory accesses increases and the drawing time of the graphic becomes long.

It is an object of the present invention to provide a graphic drawing apparatus which can reduce the number of times of memory access to reduce the wait cycle of the graphic generating circuit and the drawing time.

[0019]

A graphic drawing apparatus of the present invention sequentially designates an address generating circuit for generating a drawing address which is an address of a word including a pixel position of a drawing target graphic and the pixel position in the word. A graphic generating means having a mask generating circuit for generating a drawing mask and a drawing data generating circuit for generating drawing data at the pixel position is provided, and image data of a graphic specified in the memory is generated by a drawing command from the CPU. In a figure drawing device, an address comparison unit that detects a match between the drawing addresses of first and second pixels whose drawing order is continuous and outputs an address match signal, and the first and second pixels based on the address match signal. To the drawing mask combining means for combining the drawing masks corresponding respectively to and outputting the combined drawing mask, and the address matching. No., the drawing data combining means for combining the drawing data corresponding to the first and second pixels and outputting the combined drawing data, the drawing address, the combined drawing mask, and the combined drawing data are temporarily stored. The first-in first-out storage means and the address of the memory indicated by the drawing address output from the first-in first-out storage means are accessed, and the combined drawing data is written in the bit position of the memory indicated by the combined drawing mask. And a memory control means having a drawing data synthesizing circuit.

[0020]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the graphic drawing apparatus of the present invention.

As shown in FIG. 1, the figure drawing device 1 of the present embodiment has a figure generating circuit 2 having an address generating circuit 21, a mask generating circuit 22 and a drawing data generating circuit 23, which are the same as those in the conventional case. Addresses the above two pixels by the address comparator 3 which outputs the address match signal CA if the drawing addresses of the two pixels having consecutive drawing orders are compared and outputs the address match signal CA, the latch 13 which temporarily holds the address, and the address match signal CA. Drawing masks M to be combined and combined drawing mask M
A mask combining circuit 4 for outputting C and an address match signal C
A data combination circuit 5 for combining the drawing data P corresponding to the two pixels by A and outputting the combined drawing data PS;
A memory having a drawing data synthesizing circuit 61 instead of the conventional memory control circuit 12 and a FIFO (first-in first-out storage circuit) 62 for temporarily storing a drawing address A, a combined drawing mask MC, and combined drawing data PS in an input section. And a memory control circuit 6 for controlling the control unit 9.

FIG. 2A shows the mask coupling circuit 4 at (B).
Is a data combining circuit 5 and (C) is a drawing data synthesizing circuit 6
2 is a circuit diagram showing the details of each of FIG.

Next, the operation of this embodiment will be described.

The figure generator 2 is a CPU similar to the conventional example.
Based on the drawing command given from 10, the drawing address A, the drawing mask M, and the drawing data D for one pixel are generated as one set for each cycle.

The address comparator 3 compares the drawing address A from the figure generating circuit 2 with the output from the latch 13 which holds the drawing address A for the pixel immediately before the pixel which is currently being generated, and outputs the address match signal. Output CA. If the address coincidence signal CA is 1, the pixel generated last time by the graphic generation circuit 2 and the pixel generated this time are in the same word, and if 0, they are in different words.

As shown in FIG. 2 (A), the mask combining circuit 4 has an AND gate A41 for taking the logical product of the address coincidence signal CA and the output bit for each bit, the input bit and the output of the AND gate A41. OR gate O41 which is ORed with the initialization signal I
Of the combined drawing mask MC and the latch L41 for outputting as an output bit of the combined drawing mask MC. When the address match signal CA is 0, the value of the drawing mask M is used as it is as the value of the combined drawing mask MC, and when the address match signal CA is 1, the value of the drawing mask M and the combined drawing mask MC currently being output.
The logical sum with the value of is newly set as a combined drawing mask MC.

As shown in FIG. 2A, the data combination circuit 5 has an AND gate A51 for ANDing the drawing data P and the drawing mask M for each bit, an inverted value of the drawing mask M, and output bits. AND gate A52 that takes the logical product of
And an OR gate O51 that takes the logical sum of the outputs of the AND gates A51 and A52, and a latch L51 that latches the output of the OR gate O51 and outputs it as combined drawing data PC. The bit whose drawing mask M is 0 holds the value of the combined drawing data PC, and the bit whose drawing mask M is 1 sets the value of the drawing data P as a new value of the combined drawing data PC.

The drawing data synthesizing circuit 61, as shown in FIG. 2 (C), includes an AND gate A61 for ANDing the combined drawing data PC and the combined drawing mask MC for each bit.
A latch L61 that latches the memory read data D, an AND gate A62 that obtains a logical product of the inverted value of the combined drawing mask MC and the latch L61, and AND gates A61 and A6.
An OR gate O61 is provided to take the logical sum of the outputs of 2 and output as the combined drawing data DS.

The memory control circuit 6 receives the address match signal C
When A is 0, the value of drawing address A is used as an address,
A read-modify-write access is performed by applying the combined drawing mask MCi (0 ≦ i ≦ 31) and the combined drawing data PCi by the drawing data synthesizing circuit 611 according to the following equation.

DSi = MCi * PCi + BMCi * Di However, 0≤i≤31 (2) As described above, the mask generation circuit 2 and the drawing data connection circuit 5 work so that the drawing address A from the figure generation circuit 2 is the same. When the pixel information is continuously output, the logical sum of the drawing masks M corresponding to the plurality of pixels is obtained as the combined drawing mask MC, which is the mask combining circuit 4
Is output from. The drawing data P corresponding to the plurality of pixels is output from the drawing data combining circuit 5 as combined drawing data PC.

On the other hand, a FIFO 62 for temporarily storing the drawing address A and the combined drawing mask MC combined drawing data PC is provided at the input portion of the memory control circuit 6. This F
The IFO 62 is for allowing the graphic generation circuit 2 to calculate pixel information even while the memory control circuit 6 is executing a memory access.

Next, the pixel p shown in FIG.
An operation procedure for drawing 1, p2, ..., P5 will be described. FIG. 3 is a time chart showing the operation in that case.

First, the graphic generator 2 has a control line (not shown).
Is used to initialize the address comparator 3, the mask coupling circuit 4, and the FIFO 62 in the memory control circuit. By this initialization, the address comparator 3 causes the address match signal C to be generated regardless of the value of the drawing address A input first.
A becomes 1. This is because when the drawing address A is output for the first pixel of the figure, there is no drawing address for the pixel immediately before it.

The mask combining circuit 4 clears all the values of the combined drawing mask MC to 0 by initialization. Also, F
All data in the IFO 62 is invalidated.

In the T1 cycle, the figure generation circuit 2 generates drawing information for the pixel p1. In this cycle,
The address comparator 3 unconditionally sets the address match signal to 1.

In the T2 cycle, the value of the drawing address A is held in the latch 13 at the beginning of the cycle and is set as the drawing address A2. Further, the value of the drawing mask M (= ff000
000) is the value of the combined drawing mask MC (= 0000000
0) and a new combined drawing mask MC (= ff00
0000). The data combining circuit 5 replaces the portion of the combined drawing data PC corresponding to the bit of which the value of the drawing mask M is 1 with the value of the drawing data P (= aaaaaaaaa).

Further, the figure generation circuit 2 generates drawing information for the pixel p2. The address comparator 3 draws the drawing address AL, that is, the drawing address (= 120001) for the pixel p1 and the drawing address A, that is, the pixel p2.
The drawing address (12001) is compared with each other, and when both are equal, the address coincidence signal CA is set to 1.

Similarly, in the T3 cycle, the mask coupling circuit 4 and the drawing data coupling circuit 5 respectively operate on the pixel P.
The two pieces of information are combined, and the figure generation circuit 2 outputs drawing information corresponding to the pixel p3.

In the T4 cycle, the mask combining circuit 4 and the drawing data combining circuit 5 combine the information of the pixel p3, and the figure generating circuit 2 outputs the drawing information corresponding to the pixel p4. Here, the drawing address of the pixel p4 is 1100.
The address match signal CA is 0.

In the T5 cycle, since the address coincidence signal CA is 0 at the beginning of the cycle, the memory control circuit 6 performs the read access in the first half of the read modify write access using the value of the drawing address AL as an address.

Further, the combined drawing mask MC is cleared of the values so far to become the value of the drawing mask M, that is, the value of only the pixel p4. In the combined drawing data PC, as in the previous cycles, the portion corresponding to the pixel p4 is simply replaced with the value of the drawing data D.

In the T6 cycle, the memory control circuit performs the read access in the latter half of the read modify write access. At this time, the values of the drawing address AL and the combined drawing mask MC are changed in the T5 cycle, and the pixel p4 has already been changed.
Has become a value for. However, the data to be written (the value obtained by combining the information of the pixels p1, p2, and p3) is FIF.
Since it is stored in O62, memory access can be performed with correct information even if the value on the bus 8 changes. These data will be stored in the FIF when the write access is completed.
Removed from O62.

In other points, the address match signal is 0 in this cycle as well, so the same processing as in the T5 cycle is performed.

Although the same processing is performed in the subsequent cycles, if the memory access time is longer than the speed at which the figure generation circuit generates the pixel information, the data is accumulated in the FIFO 62, but in this case, the wait control is performed. Signal C
The W causes the figure generation circuit 2 to wait.

As can be seen by comparing FIG. 3 and FIG. 6, in the method of the present invention, there is a large delay from the generation of the pixel information to the actual writing of the pixel information in the memory. However, this delay only shifts the memory access timing to the rear, and does not increase the drawing time of the figure.

[0047]

As described above, the graphic drawing apparatus of the present invention combines the plurality of pixels by the address comparing means for detecting the coincidence of the drawing addresses of the plurality of pixels in the drawing order and the address matching signal. A memory is provided by providing a drawing mask combining means for outputting a drawing mask and a drawing data combining means for outputting combined drawing data, and by drawing the plurality of pixels collectively when the plurality of pixels are included in the same word. There is an effect that the number of times of access can be reduced and the speed of graphic drawing can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a graphic drawing apparatus of the present invention.

FIG. 2 is a circuit diagram showing details of a mask combining circuit, a data combining circuit, and a drawing data combining circuit of the present embodiment.

FIG. 3 is a time chart showing an example of the operation of the graphic drawing apparatus of this embodiment.

FIG. 4 is a diagram showing a general correspondence between a drawing pixel and a bit of a memory.

FIG. 5 is a block diagram showing an example of a conventional graphic drawing device.

FIG. 6 is a time chart showing an example of the operation of the conventional graphic drawing apparatus.

[Explanation of symbols]

1, 11 Graphic drawing device 2 Graphic generation circuit 3 Address comparator 4 Mask coupling circuit 5 Data coupling circuit 6, 12 Memory control circuit 7 Address bus 8 Data bus 9 Memory 10 CPU 13, L41, L51, L61 Latch 21 Address generation circuit 22 mask generation circuit 23 drawing data synthesizing circuit 61, 121 drawing data synthesizing circuit A41, A51, A52, A61, A62 AND gate O41, O51, O61 OR gate

Claims (1)

[Claims] 1. An address generation circuit that sequentially generates a drawing address that is an address of a word including pixel positions of a drawing target graphic, a mask generation circuit that generates a drawing mask that specifies the pixel position in the word, and the pixel position. In a figure drawing device that includes a figure generation unit having a drawing data generation circuit that generates the drawing data, and that generates image data of a figure specified in the memory by a drawing command from the CPU, An address comparison unit that detects a match of the drawing addresses of the second pixels and outputs an address match signal, and a combined drawing mask that combines the drawing masks corresponding to the first and second pixels by the address match signal. And a drawing mask combining means for outputting to the first and second pixels by the address match signal. Drawing data combining means for combining the corresponding drawing data and outputting combined drawing data, first-in first-out storage means for temporarily storing the drawing address, the combined drawing mask, and the combined drawing data, respectively. A memory control means having a drawing data synthesizing circuit for accessing the address of the memory indicated by the drawing address outputted from the advance storage means and writing the combined drawing data into a bit position of the memory indicated by the combined drawing mask; A graphic drawing apparatus comprising: