JPH06113290A - Motion vector detector - Google Patents

Abstract

PURPOSE:To obtain the motion vector detector with a small occupied area, low power consumption and at a high speed operation. CONSTITUTION:A motion vector detector includes a processor array (10) in which element processors storing search window data and template data are arranged in a shape of 2-dimension array. Each of the element processors included in the processor array (10) is provided with a function taking a difference absolute value of the search window data and template data stored and with a function shifting storage data to an adjacent element processor. The motion vector detector includes a total sum section (12) summing the total of the difference absolute values outputted from each element processor of the processor array (10) and a comparator section (3) detecting a motion vector with respect to the template block according to the output of the total sum section (12).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for detecting a motion vector used for motion compensation of a moving image.

[0002]

2. Description of the Related Art In order to transmit or store an image signal having an enormous amount of data, a data compression technique for reducing the amount of data is indispensable. The image data has a considerable degree of redundancy due to the correlation between neighboring pixels and human perception characteristics. A data compression technique that suppresses this data redundancy and reduces the amount of transmission data is called high efficiency coding. An interframe predictive coding system is one of the high efficiency coding systems. In this interframe predictive coding method, the following processing is executed.

A prediction error, which is a difference between each pixel data of the current frame to be encoded at present and each pixel data at the same position of the preceding frame to be referred to, is calculated. This calculated prediction error is used for subsequent encoding. With this method, an image with little motion can be coded with high efficiency because the correlation between frames is large. However, for an image with a large amount of motion, the error between the frames is small because the correlation between the frames is small, and conversely, the amount of data to be transmitted increases.

As a method for solving the above problems, there is an interframe predictive coding system with motion compensation. In this method, the following processing is performed. That is, before calculating the prediction error, the motion vector is calculated in advance using the pixel data of the current frame and the previous frame. The predicted image of the previous frame is moved according to the calculated motion vector.
That is, pixel data at a position shifted by the motion vector of the previous frame is used as a reference pixel, and this reference pixel is used as a prediction value. Next, the prediction error of each pixel between the previous frame and the current frame after this movement is calculated, and the prediction error and the motion vector are transmitted.

FIG. 86 is a block diagram showing the overall configuration of an encoder for encoding image data according to the conventional predictive encoding system with motion compensation. In FIG. 86, the encoder is
A pre-processing circuit 910 that performs a predetermined pre-processing on the input image signal, and a source coding circuit that removes redundancy and quantizes the input signal for the signal pre-processed by the pre-processing circuit 910. 912, and a video multiplex encoding circuit 914 that encodes the signal from the source encoding circuit 912 according to a predetermined format and multiplexes it into a code string having a predetermined data structure.

The pre-processing circuit 910 converts the input image signal into a common intermediate format (CIF) using a temporal and spatial filter and performs filtering for noise removal.

The source coding circuit 912 performs orthogonal transform processing such as discrete cosine transform (DCT) on the given signal, performs motion compensation on the input signal, and quantizes the orthogonally transformed image data. .

Video multiplex encoding circuit 914
Performs two-dimensional variable-length coding on a given image signal, and after variable-length coding various attributes (motion vector etc.) of a block which is a data processing unit, a code string of a predetermined data structure. To multiplex.

The encoder further includes a transmission buffer 916 for buffering the image data from the video multiplex encoding circuit 914, and a transmission encoding circuit 918 for adapting the image data from the transmission buffer 916 to the transmission channel. Including.

The transmission buffer 916 smoothes the information generation rate to a constant rate. The transmission encoding circuit 918 executes addition of error correction bits, addition of voice signal data, and the like.

FIG. 87 is a diagram showing an example of a specific configuration of the source encoding circuit shown in FIG. In FIG. 87, the source encoding circuit detects a motion vector for an input image signal and generates a motion-compensated reference pixel according to the motion vector, and reference pixel data from the motion-compensated predictor 920. A loop filter 922 for performing a filter process on the output signal, a subtractor 924 for obtaining a difference between the output of the loop filter 922 and the input image signal, an orthogonal transformer 926 for orthogonally transforming the output of the subtractor 924,
It includes a quantizer 928 for quantizing the data orthogonally transformed by the orthogonal transformer 926.

Although the structure of the motion compensation predictor 920 will be described in detail later, it includes a frame memory for storing the pixel data of one frame before, and detects a motion vector in accordance with the input image signal data and the pixel data in this frame memory. And generation of motion-compensated reference pixel data. The loop filter 922 is provided to improve image quality.

The orthogonal transformer 926 performs orthogonal transformation such as DCT transformation on the data from the subtractor 924 using a predetermined block (usually 8 × 8 pixels) as one unit. The quantizer 928 quantizes the orthogonally transformed pixel data.

Motion compensated predictor 920 and subtractor 924
By this, inter-frame prediction with motion compensation is executed, and temporal redundancy in the moving image signal is removed. Further, the orthogonal transformation by the orthogonal transformer 926 removes spatial redundancy in the moving image signal.

The source encoding circuit further includes a quantizer 92.
An inverse quantizer 930 for converting the data quantized in 8 into a signal state before quantization, and an inverse orthogonal transformer 932 for performing an inverse orthogonal transform on the output of the inverse quantizer 930,
It includes an adder 934 for adding the output of the loop filter 922 and the output of the inverse orthogonal transformer 932. This inverse quantizer 93
An image used for interframe prediction for the next frame is generated by the 0 and the inverse orthogonal transformer 932. The generated image data is written in the frame memory included in the motion compensation predictor 920. Since the input image signal (difference data between frames) is added, the data of the current frame is reproduced. Generally, the inverse quantization process, the inverse orthogonal transform process and the addition process are generally called a local decoding process.

Next, the calculation of the motion vector will be specifically described. A block matching method is generally used to calculate the motion vector.

As shown in FIG. 88 (A), the (m-1) th
The image A in the frame is A ′ in the mth frame
Consider the state of moving to. In the block matching method, an image (one frame) is divided into blocks of P × Q pixels (generally P = Q). The block closest to the block of interest in the current frame is searched for in the previous frame. The shift from this block of interest to the block that most closely approximates the previous frame is called a motion vector. The details will be described below.

As shown in FIG. 88B, it is assumed that the m-th frame is the current frame to be coded. The frame is divided into blocks of N × N pixels. N × N in the m-th frame
The upper left pixel position (Nk, N
Let the value of the pixel data in l) be Xm (Nk, Nl). The absolute value sum of the differences between the block in the previous frame and the block in the current frame in which the pixel position is shifted by the position (i, j) is obtained. Next, the deviation (i, j) is changed into various values, and the sum of absolute differences is obtained. A position (i, j) that gives the sum of absolute differences of the minimum values is called a motion vector.

It is necessary to transmit one motion vector for each block pixel. If the block size is reduced, the amount of transmission information increases and effective data compression cannot be performed. On the other hand, if the block size is increased, effective motion detection becomes difficult. So the block size is 16x16 pixels,
Motion vector search range (maximum change width of i, j) is -15
It is generally set to +15. The calculation of the motion vector by the block matching method will be specifically described below.

FIG. 89 is a diagram showing a method of calculating a motion vector by the block matching method. Now consider an image 950 consisting of 352 dots × 288 lines. Image 95
0 is divided into blocks with a 16 × 16 pixel group as one block. Motion vector detection is performed in block units. A block that is larger by ± 16 pixels in the horizontal and vertical directions with respect to a block 954 in the previous frame at the same position as a block to be detected (hereinafter referred to as a template block) 952, that is, a block 954 at the center 48 × A block 956 composed of 48 pixels is a search block (hereinafter referred to as a search area). The motion vector search for template block 952 is performed in this search area. The motion vector search method according to the block matching method includes the following processing steps.

A predicted image block (indicated by (i, j) in FIG. 89) having a displacement corresponding to a motion vector candidate is obtained. An evaluation function value such as a sum of absolute differences (or a sum of squared differences) of pixels at corresponding positions of the obtained block and the template block is obtained.

In the above operation, (i, j) is (-16, -1)
6) to (+16, +16) for all displacements. After obtaining the evaluation function (evaluation value) for all the predicted image blocks, the predicted image block having the smallest value of this evaluation function is detected. The vector from the block at the same position as the template block (hereinafter, referred to as the true back) (block 954 indicated by (0,0) in FIG. 89) to the prediction image block having the smallest evaluation function value is defined as the motion vector for this template block. decide.

Various configurations for obtaining such a motion vector by hardware have been proposed.

FIG. 90 is a diagram showing the overall structure of a conventional motion vector detecting device, for example, 1989 IEEE.
E, ICASSP'89 Proceedings, 245
See pages 3 through 2456 by A. Artieri et al. In FIG. 90, the motion vector detection device has a search area input register 962 for inputting one column of the search area pixel data.
And a processor array 966 including a plurality of processors arranged in a matrix of rows and columns having the same size as the template block evaluation points, and a search area side register 964a for storing data of the same column in the search area for this processor array. And 964b, and a motion vector detection unit 968 that detects a motion vector according to the calculation result of the processor array 966.

Processors are arranged in the processor array 966 in correspondence with the displacement vector (i, j). That is, the processor Pij arranged in the i-th row and the j-th column calculates the displacement vector D (i, j).

FIG. 91 shows a structure of a processor included in the processor array shown in FIG. In FIG. 91, a processor 970 receives search area data transmitted from processors in three horizontal and vertical directions of the array, and responds to a selection signal SEL to pass one input thereof. Input register 972
Distortion calculation section 974 for calculating distortion (sum of absolute differences) based on the search area data Y from and the template block data X given from the outside, and a processor adjacent to the distortion D from the distortion calculation section 974 in the horizontal direction. 2 and selectively pass one of them according to the selection signal To.
It includes an input register 976.

This processor is arranged two-dimensionally in the processor array shown in FIG. 90 so as to correspond to all displacement vectors that are candidates for motion vectors in the search area. The same template block data X is applied to all the processors 970 of the processor array 966 (see FIG. 90). At this time, to the processor 970,
The corresponding data of the search area block is given. That is, for example, the template block data X is X
In the case of (m, n), the search area block data Y (i + m, j + n) is given to the processor Pij. The search window data is transferred via the search area side registers 964a and 964b and each processor 970 of the processor array 966. Template block data X (m, n) given from the outside
, The search area block data Y (m +
To give i, n + j), the template block data and the search area block data must be scanned with some regularity.

FIG. 92 is a diagram showing a method of scanning the data of this template block. In FIG. 92,
The template block data is first scanned from top to bottom along the same column in template block 999, as indicated by the arrows in the figure, then 1
It is generated by scanning the data next to the column from the bottom to the top. This scanning method is called “snake scan”. According to the "snake scan" method of the template block data, the search area block data provided to the processor array is also scanned. The processor needs to transfer the search area data in the vertical direction in the figure or in the left direction in FIG. 91 according to the arrangement position. Therefore, a 3-input register 972 is provided.

The 2-input register 976 transmits the distortion calculated by the processor to the motion vector detecting section 968 in order to obtain the displacement vector which gives the minimum distortion in the motion vector detecting section 968 after each displacement vector is calculated. It is provided to do. The motion vector detection unit 968 detects the minimum distortion among the distortions from the respective processors, and obtains the processor position giving the minimum distortion, that is, the motion vector. Next, the operation of the motion vector detecting device shown in FIG. 90 will be briefly described.

In the processor array 966, the i-th row and the j-th row
The processors Pij arranged in columns calculate the distortion D (i, j) represented by D (i, j) = Σ | X (m, n) -Y (m + i, n + j) |. Where the sum Σ
Is performed for m and n. The change range of m and n is determined by the size of the search area.

Consider a pixel arranged in M rows and N columns as a template block 980 as shown in FIG. In the first cycle, search area block data indicated by reference numeral 982 is stored in each processor in the processor array. From the outside, the pixel X (1,1) in the first row, first column in the template block 980
Is given to all processors in the processor array. Each processor 970 has search window data Y stored therein and given template block data X.
The absolute value of the difference between and is calculated and accumulated.

In the next cycle, the search area data is shifted downward by one row in FIG. 93 in the processor array. In this state, the next pixel data X (2,1) is then supplied from the template block 980.
In the processor 970, the stored search area data is Y (m + i + 1, n + j). Absolute difference values are again taken and accumulated using these data. This operation is repeated M times.

When the above operation is repeated M times, the search area pixel data for one column of the search area is externally written via search area input register 962 shown in FIG. Pixel data for one column of the search area that has become unnecessary is released. As a result, new search area data is stored in the search area side registers 964a and 964b and the processor array 966. This operation is repeatedly executed.

That is, as shown in FIG. 94, first, the calculation of the sum of absolute differences is executed using the search window 990, and after the completion of M cycles, the next search window 99 is displayed.
The same calculation is performed again using the data of 2, and thereafter,
The same operation as the search window 994, ... Is repeated. When the calculation is finally performed on the pixel data for all the search areas 996, the distortion D (i, j) is obtained and held in the processor Pij.

The distortion D (i, j) obtained by each processor Pij is transmitted to the motion vector detecting unit 968 (see FIG. 90), and the distortion giving the minimum distortion is detected as a motion vector.

The above-mentioned motion vector detecting device detects the motion vector using the pixel data of the search area and the pixel data of the template block. The motion vector obtained in this case is called an integer precision motion vector. This is because the minimum unit of horizontal and vertical components of the motion vector is one pixel unit. Such an integer-precision motion vector is specified in the moving image coding system for TV phones and video conferences (CCITT Recommendation H.261).

On the other hand, in the storage type moving image coding system using a digital storage medium, a 1/2 pixel unit (hereinafter,
This is called 1/2 pixel precision. In addition, detection precision that is finer than integer precision is called fractional precision). In motion compensation with 1/2 pixel accuracy, not only the position shifted in pixel units on the reference frame used for prediction is checked, but also the position between pixels is generated by data interpolation, and with respect to this interpolation data Even the block matching process is executed. Motion compensation using this 1/2 pixel precision motion vector is called “half-pel motion compensation”.

FIG. 95 is a diagram schematically showing the overall structure of a conventional fractional precision motion vector detecting device. This Figure 9
The configuration of the apparatus shown in 5 is, for example, 1989, IEEE,
Proceedings of ICASSP'89 No. 243
No. 7, pp. 2440 to Young.

In FIG. 95, the fractional precision motion vector detection device is provided with a reference image frame memory 801 for storing the pixel data of the entire reference frame image one frame before, and a current image frame for storing the pixel data of the entire current frame image. Memory 802 and frame memories 801 and 80
First, the search window block data and the template block data are read from No. 2 through the data lines 807 and 809 to detect the motion vector with integer precision.
The calculator 805 of FIG. The processing contents executed by the first arithmetic unit 805 are the same as those described above.

The fractional precision motion vector detection device further comprises:
A fractional precision search window memory 804 for receiving and storing search window block data for detecting a motion vector with fractional precision from the reference image frame memory 801 via a data line 808, and a current image frame memory 802. From the fraction precision template memory 803, which receives and stores the template block data used at that time via the data line 810 from the fraction precision template memory 803 and the fraction precision search window memory 804. And 812 to receive pixel data and detect a fractional precision motion vector. The motion vector detected from the first computing unit 805 is the signal line 81.
3 to the second arithmetic unit 806. The second arithmetic unit 806 sets the motion vector with the integer precision and the motion vector with the newly obtained fractional precision as a set to the signal line 8
Communicate on 14. Next, the operation will be described.

The first computing unit 805 reads the search window block data from the reference image frame memory 801, reads the template block data from the current image frame memory 802, and evaluates the displacement function (evaluation value) for each displacement vector. To calculate. After all the search window block data in the search area is read from the reference image frame memory 801 and the evaluation value is calculated, the first arithmetic unit 805 detects the minimum evaluation value from this evaluation value and The displacement vector corresponding to the smallest evaluation value is determined as the motion vector.

After the motion vector is detected, the current image frame memory 802 transmits the template block data used at that time to the fraction accuracy template memory 803 via the data line 810. The reference image frame memory 801 transmits the search window block data corresponding to the displacement vector giving the motion vector and its peripheral data to the fraction accuracy search window memory 804 via the data line 808. For example, when the search window block is composed of 16 × 16 pixels, the reference image frame memory 801 supplies 18 × 18 pixel data including the peripheral pixel data to the fractional precision search window memory 804. .

As a result, as shown in FIG. 96, the template memory 803 stores the pixel data of the template block in the area 820 (indicated by the white circles), while the search window memory 804 stores the search indicated by the area 822. Stores window block data. The following operation is executed in the second arithmetic unit 806.

First, interpolation processing is performed on each pixel data (indicated by white circles) of the search window block 822 to generate interpolation data between pixels. Here, FIG. 96 shows a case where a motion vector with 1/2 pixel precision is detected. The motion vector candidates are (-1
16 displacement vectors including fractional components between / 2, -1/2) and (1/2, 1/2). That is, 1/2
In the case of pixel accuracy, 16 search window blocks are formed, and an evaluation value is calculated for each block. As indicated by an X mark in FIG. 96, two pixels P (A) and P
The interpolation data between (B) is (P (A) + P (B)) /
4 pixels P (A), P (B), P
Interpolated data between (C) and P (D) is (P (A)
It is calculated by + P (B) + P (C) + P (D)) / 4.
Rounding processing is executed on the interpolation data. An operation similar to motion vector detection with integer precision is executed on the generated interpolation data.

FIG. 97 shows the relationship between the integer precision motion vector and the fraction precision motion vector. In FIG. 97,
Displacement vectors are arranged in units of one pixel in the vertical direction and the horizontal direction (shown by white circles in the figure). A displacement vector with a fractional precision is obtained by the second computing unit around the motion vector MI (shown by a broken line circle in FIG. 97), and the displacement vector giving the minimum value among these displacement vectors is obtained, and an integer is obtained. The motion vector MF with fractional precision (detailed accuracy) is obtained by combining the fractional precision component with the motion vector MI with precision.

[0046]

In the motion vector detecting device shown in FIG. 90, the same template block data is given to all the processors in the processor array. Therefore, a large driving force is required for the circuit for writing the pixel data of the template block, and the current consumption in the template block pixel data writing circuit becomes large, and the power consumption of the entire device becomes large. The problem arises.

Further, in the motion vector detecting device shown in FIG. 90, each processor in the processor array corresponds to a displacement vector which is a motion vector candidate. Search area is vertical direction +16 to -16, horizontal direction -16
In the case of up to +16, the number of displacement vectors as motion vector candidates is 33 × 33 = 1089, and accordingly, the number of processors becomes very large, which causes a problem that the area occupied by the device becomes large.

In each operation cycle, data transfer is performed via the processor. At this time, a 3-input register is used to determine the data transfer direction, which causes a problem that power consumption during data transfer increases.

Further, in the motion vector detecting device shown in FIG. 90, each processor calculates an evaluation value (distortion). That is, the difference absolute value (or difference square) is calculated, and the calculation result is accumulated. For this reason, there arises a problem that the area occupied by the processor is increased and the current consumption is increased.

Further, in the configuration of the fractional precision motion vector detection device shown in FIG. 95, a frame memory for integer precision and a frame memory for fractional precision are provided. During the motion vector detection operation with fractional precision, it is necessary to transfer the required search window block data from the reference precision frame memory for integer precision to the fractional precision search window memory. After the data is transferred to the search window memory, it is necessary to read the search window block data from the search window memory again to detect the motion vector with the fractional accuracy. Therefore, the number of accesses to the memory becomes extremely large, and the throughput of the motion vector detection apparatus as a whole is limited by the access time to the memory, which causes a problem that the motion vector cannot be detected at high speed.

Similarly, for the template block data, it is necessary to read the template block data from the template memory after transferring the data from the frame memory for the current image to the template memory for the fractional precision, and store the current frame image data. There is a problem that the access time to the frame memory becomes long, the throughput of the motion vector detecting device is limited by the access time to the current image frame memory, and the motion vector cannot be detected at high speed.

Therefore, an object of the present invention is to provide a motion vector detecting device capable of detecting a motion vector at high speed.

Another object of the present invention is to provide a motion vector detecting device which operates with low power consumption.

Still another object of the present invention is to provide a motion vector detecting device having a small occupied area.

[0055]

SUMMARY OF THE INVENTION In summary, a motion vector detecting apparatus according to the present invention has an array of element processors which respectively store different template block data and different search window block data. , The processors arranged in the array are simultaneously driven to calculate the evaluation value of one displacement vector. The search window block data is transferred through this processor array along one direction, and unnecessary search window block data is sequentially shifted out.

The data shifted out from this processor array is used during the motion vector detection operation with fractional precision and during the interpolative prediction motion vector detection.

That is, the motion vector detecting apparatus according to the first aspect comprises a plurality of element processors each including a transfer means for transferring data substantially along one direction.
The element processor has first storage means for storing pixel data of a first block of the current frame image and second storage means for storing pixel data of a second block related to the first block in the reference frame image. Storage means and a calculation means for performing a predetermined calculation process on the data stored in the first and second storage means.

The motion vector detecting apparatus according to claim 1 is further responsive to the outputs of the respective calculating means of the plurality of element processors, and the evaluation value indicating the degree of correlation between the image of the first block and the image of the second block. And an deciding means for deciding a motion vector for the first block in accordance with a plurality of evaluation values associated with the first block from the evaluation value producing means.

A motion vector detecting device according to claim 2 is
The determining means according to claim 1 determines a motion vector with integer precision, and further receives the reference frame image data and the current frame image data, and calculates the motion vector of the first block with fractional precision finer than integer precision. And a means for giving at least one of the reference frame image data and the current frame image data output from the multi-element processor to the arithmetic processing means as data to be processed.

In the motion vector detecting device according to a third aspect of the present invention, each of the element processors of the first aspect includes, as a first storing means, a storage means for storing M pixel data corresponding to mutually different pixels, and The second storage unit includes a storage unit that stores N pieces of pixel data corresponding to mutually different reference frame pixels. Both M and N are positive integers and satisfy the relationship of N ≧ M.

A motion vector detecting device according to a fourth aspect is
The arithmetic means of the element processor according to claim 1 performs a subtraction between the pixel data of the first block and the pixel data of the second block, and a code bit indicating the sign of the subtraction result and a size bit indicating the size are obtained. And a gate means for outputting a value corresponding to the absolute difference value of the subtraction result by performing addition of the module 2 of each magnitude bit and the sign bit of the subtraction means. The output of the computing means is given as a set of a sign bit and a value corresponding to the absolute difference value.

A motion vector detecting apparatus according to claim 5 is
In the motion vector detecting device according to the fourth aspect, the evaluation value generating means includes a summing circuit for calculating a sum of outputs of the calculating means. The summing circuit includes a plurality of stages of full adder circuits arranged in a tree shape, in which all outputs are transmitted to the next stage. The sign bit provided from the arithmetic means is applied to the carry input of the full adder circuit of the least significant bit of this full adder circuit stage.

A motion vector detecting device according to a sixth aspect is
A device for obtaining a motion vector of a template block composed of pixels arranged in Q rows and P columns by block matching processing, each of which stores first M template block data and N search windows. Q / including second storage means for storing block data
A linear processor array including M element processors and data buffer means cascaded to the Q / M element processors includes P processor arrays arranged in parallel. The data buffer means includes means for storing R search window data. N + R indicates the size of one row of the search area. The element processor further includes calculation means for performing a predetermined process on the data stored in the first storage means and the data stored in the second storage means.

A motion vector detecting apparatus according to claim 7 is
7. The motion vector detection device according to claim 6, wherein each of the element processors includes means for transferring the search window data only along one direction in the linear processor array.

A motion vector detecting device according to an eighth aspect is
In the motion vector detecting device according to the seventh aspect, the template block data is in a direction orthogonal to the transfer direction of the search window data.

A motion vector detecting device according to a ninth aspect is
In the motion vector detecting device according to the seventh aspect, the template block data is in the same direction as the transfer direction of the search window data.

In the motion vector detecting apparatus according to the tenth aspect, the calculation speed of the calculation means is N times the transfer speed of the search window data.

According to an eleventh aspect of the motion vector detecting apparatus of the sixth aspect, in the motion vector detecting apparatus of the sixth aspect, the calculating means executes the calculation at a speed N times the transfer rate of the search window data.

A motion vector detecting apparatus according to a twelfth aspect is the motion vector detecting apparatus according to the sixth aspect, wherein the first storage means in each element processor stores the first block of the current frame. Means and a second storage means for storing the second template block data in this current frame.

A motion vector detecting apparatus according to a thirteenth aspect stores first pixel means for storing pixel data of a first block of the current frame image and pixel data of a second block of the current frame image. Second storage means, third storage means for storing pixel data of blocks of reference frames related to the first and second blocks, pixel data stored in the first storage means, and third storage A first arithmetic means for performing a predetermined arithmetic processing on the pixel data stored in the means; a predetermined arithmetic operation for the pixel data stored in the second storage means and the pixel data stored in the third storage means; Second arithmetic means for performing arithmetic processing is included. Both the first and second arithmetic means perform predetermined arithmetic processing using the same pixel data of the reference frame. First and second
The arithmetic means may operate in parallel, or may have the same configuration and operate in a time division manner.

The motion vector detecting device according to the thirteenth aspect of the present invention further includes the degree of correlation between the first block and the reference frame image block and the second block based on the calculation result generated by the first and second calculating means. Evaluation value generating means for generating an evaluation value indicating the degree of correlation between each of the first block and the reference frame image block, and motion vectors for the first block and the second block are determined in parallel in response to the output of the evaluation value generating means Including means to do.

The motion vector detecting apparatus according to the fourteenth aspect of the present invention comprises a template block image according to a template block image to be encoded in a current claim image and a partial reference image in a reference frame image associated with the template block image. A plurality of one-sided predictive motion detecting means for calculating a motion vector for the block matching evaluation value, and partial reference image data used by the plurality of one-sided predictive motion detecting means are input, and an interpolated partial reference image by interpolation processing. Is generated, and an interpolated predicted motion detecting means for performing block matching processing between the template block image and this interpolated partial reference image to detect a motion vector according to the evaluation function value, and a plurality of one-sided predicted motion detecting means are calculated. The evaluation function value and the evaluation function calculated by this interpolation prediction motion detection means. And an output determining unit that determines and outputs the final motion vector of the template block image according to the value.

The plurality of one-sided prediction motion detecting means inputs partial reference image data in different reference images.

In the motion vector detecting device according to the fifteenth aspect, each of the one-side predictive motion detecting means according to the fourteenth aspect is
Integer precision motion vector detecting means for detecting a motion vector with integer precision, buffer memory means for receiving corresponding partial reference image data from the integer precision motion vector detecting means, and partial reference image from this buffer memory means A fractional precision motion vector detecting means for calculating a motion vector with a fractional precision according to the data and the template block image data, and the interpolation prediction motion detecting means further inputs the corresponding partial reference image data from each of the buffer memory means. Is being done.

A motion vector detecting device according to a sixteenth aspect is the motion vector detecting device according to the fourteenth aspect, further comprising a block matching evaluation function value, a motion vector, and a part calculated from a plurality of one-sided prediction motion detecting means. A transfer means is provided for transferring the reference image data from the corresponding one-sided prediction motion detection means to the interpolation prediction motion detection means.

[0076]

In the motion vector detecting device according to the first aspect, the number of element processors is the maximum number of pixels in the template block, and the number of element processors can be reduced.

Template block data also remains resident in the processor until its associated motion vector is detected. Since only the search window data is transferred, it is possible to reduce current consumption / power during data transfer.

Further, in the element processor, only a predetermined operation is executed, and the evaluation value indicating the degree of association between the final blocks is obtained by the evaluation value generating means provided outside the array, so that the area occupied by the processor array is reduced. Therefore, the area occupied by the device can be reduced accordingly.

According to the second aspect of the present invention, the data used for the motion vector determination with fractional precision is transmitted as it is as the data used for the motion vector determination with integer precision. Therefore, the number of times of access to the frame memory can be significantly reduced, and a motion vector with a fractional accuracy can be detected at high speed.

In the invention according to claim 3, since the element processor stores M template block data and N search window data, the number of element processors in the processor array can be reduced.
Further, at this time, in the processor means, one arithmetic means is M
Since the calculation of the template block data and the N search window data is executed, the number of calculation means operating at the same time is also reduced, so that the current consumption required for the calculation can be reduced. Further, by driving the arithmetic means in a time-division manner, the circuit scale of the evaluation value generating means provided outside is also reduced accordingly, and the power consumption is accordingly reduced.

In the invention according to claim 4, the calculation means performs addition of the signed subtraction result by the module 2 of the sign bit and each size bit to obtain the sign bit and the value corresponding to the absolute difference value. Configures the output. This eliminates the need to use an incrementer required for displaying a negative number in the 2's complement display, and this reduction in the scale of the arithmetic circuit can be realized, and the sign bit and the difference absolute value can be simply used only by the gate means. Since the values corresponding to and are generated, the calculation result can be output at high speed.

In the invention according to claim 5, the summing circuit for summing the outputs of the calculating means is composed of a plurality of stages of full adder circuits arranged in a tree form, and the sign bit is the maximum of the full adder circuit stage. It is given to the carry input of the lower bit.
As a result, the carry propagation delay time can be significantly reduced, the summation operation can be executed at high speed, and the evaluation value can be generated accordingly.

A motion vector detecting apparatus according to claim 6 is
It includes element processors arranged in an array. The evaluation value of the displacement vector can be efficiently generated with the minimum number of element processors, and low power consumption and a small occupied area can be realized.

A motion vector detection device according to a seventh aspect is
In the motion vector detecting device according to the sixth aspect, the transfer of the search window data is executed in the linear array only in one direction at all times. As a result, the search window data can be efficiently transferred, and the data transfer can be executed with low power consumption.

In the motion vector detecting apparatus according to the eighth aspect, the search window data transfer direction and the template block data transfer direction are arranged so as to be orthogonal to each other. In this case, the template block data can be transferred corresponding to the raster-scanned image data, and the data transfer can be performed efficiently.

In the motion vector detecting device according to the ninth aspect, the search window data and the template block data are transferred along the same direction. in this case,
Since the data transfer signal line is arranged within the element processor width along this one direction, the wiring occupying area can be significantly reduced.

In the motion vector detecting device according to the tenth aspect, the calculating means in the motion vector detecting device according to the sixth aspect executes the calculation at a speed N times the search window data transfer speed. As a result, each element processor can execute the operation of a plurality of search window block data and template block data by using only one operation means, and the circuit scale of the element processor can be reduced.

In the invention according to claim 11, the motion vector detecting device according to claim 6 executes the calculation at a speed N times the transfer speed of the search window data. In this case, there is search window data for which calculation is not executed. At this time, the template block data is thinned out (subsampled) and stored in the storage means of each element processor, so that the motion vector can be determined using the minimum necessary template block data, and the motion can be performed at high speed. Vectors can be detected.

In the twelfth aspect of the invention, the motion vector detecting apparatus according to the sixth aspect calculates the motion vectors of the two template blocks in parallel using the same search window block data. This makes it possible to detect the motion vector at high speed.

In the motion vector detecting apparatus according to the thirteenth aspect, the motion vector is determined in parallel for the two template blocks by using the data of the same search window block. As a result, the motion vector can be detected at high speed without increasing the device scale and power consumption.

In the motion vector detecting apparatus according to the fourteenth aspect, since the partial reference image data used for detecting the interpolated motion vector predictor is supplied from the corresponding one-sided motion vector predictor to the interpolated motion predictor. The number of accesses to the frame memory that stores the reference image data is reduced, and the interpolation prediction motion detection can be performed at high speed.

In the motion vector detecting apparatus according to the fifteenth aspect, since the partial reference image data is read from the buffer memory means to perform the interpolative predictive motion detection, the interpolative predictive motion vector of the detailed accuracy can be obtained without increasing the scale of the apparatus. Detection can be performed.

In the motion vector detecting apparatus according to the sixteenth aspect, all necessary data is transferred from the one-sided predictive motion detecting means to the content predictive motion detecting means by the transferring means, so that the processing operation is executed in a pipeline manner. Therefore, the motion vector can be detected at high speed.

[0094]

[Embodiment 1] FIG. 1 is a block diagram schematically showing the overall configuration of a motion vector detecting device according to a first embodiment of the present invention. The motion vector detection device shown in FIG. 1 detects a motion vector with integer precision.

In FIG. 1, the motion vector detecting device is
An input section 2 that receives the search window data Y and the template data X and outputs the given data at a predetermined timing, and an evaluation of a displacement vector for one template block based on the data given from the input section 2. The calculation unit 1 for calculating a value (evaluation function) and the evaluation value (Σ | a−b |) obtained by the calculation unit 1 are received, and 1
It includes a comparison unit 3 which obtains a minimum evaluation value associated with one template block and determines a displacement vector corresponding to the minimum evaluation value as a motion vector. The comparison unit 3 outputs the motion vector.

The arithmetic unit 1 sums the processor array 10 including a plurality of element processors arranged in an array, and the operation result values (absolute difference values in this embodiment) output by each element processor of the processor array 10. Summation section 12
Including and The element processors included in the processor array 10 store different template block data,
A component of an evaluation value indicating the degree of correlation between one template block and one search window block is calculated. In the processor array 10, the template block data is always stored during the operation cycle for obtaining the motion vector for this template block. The search window block data is shifted by one pixel in the processor array for each operation cycle. As a result, the evaluation value for each displacement vector can be calculated with the minimum search window data transfer operation.
A reduction in power can be obtained. Next, a specific configuration of the arithmetic unit 1 shown in FIG. 1 will be described.

FIG. 2 is a diagram showing the sizes of the template block and the search area used in this embodiment. Template block 20 includes pixels arranged in Q rows and P columns. The search area 22 has a horizontal search range of + t1 to -t2 and a vertical search range of + r1 to -r2. That is, search area 2
2 includes (t2 + P + t1) × (r2 + Q + r1) pixels.

FIG. 3 is a diagram schematically showing a configuration of an element processor included in the processor array shown in FIG. Figure 3
In, the element processor PE includes M data registers 25-1 to 25-M connected in cascade for storing template block data. Data register 25-
1 to 25-M store different template block data. This data register 25-1 to 25
-M corresponds to the storage means in the first storage means.

Element processor PE also includes N cascaded data registers 26-1 to 26-N for storing search window data. The data registers 26-1 to 26-N correspond to the storage means of the second storage means. N is an integer multiple (n times) of M. In addition, the number Q of rows in the template block is determined by the data register 25-1.
.About.25-M is an integer multiple of the number M of stages. In this element processor PE, there are M data registers 25-1 to 25-25.
An operation is performed using the template block data stored in -M. At this time, the data registers 26-1 to 26-N for storing the search window data are replaced by the data registers 25-1 to 25 for storing the template block data.
There may be a one-to-one correspondence with -M (N = M), and the operation may be executed using the data stored in each corresponding register. Other combinations may be used.

The element processor PE executes an operation on M template block data. Element processor P
The calculation means in E is the M data registers 25.
Used in a multiplexed manner for -1 to 25-M. That is, in this embodiment, only one arithmetic means is provided in the element processor PE.

Search window data and template block data are transferred only between adjacent element processors in one direction.

FIG. 4 is a diagram showing the structure of the processor array shown in FIG. In FIG. 4, the processor array 10
Are linear processor arrays LA1 to LA arranged in P columns
Including P. The linear processor arrays LA1 to LAP have the same structure and m element processors P arranged in a cascade form.
The data buffer DL includes E1 to PEm and R (= r1 + r2) pieces of search window data and also functions as a delay unit.

The element processors PE1 to PEm transmit the search window data and the template block data along one direction (vertical upward direction in FIG. 4) in the same linear processor array LA. During data transfer to the adjacent linear processor array, the search window data from the most upstream element processor PE1 is supplied to the data buffer DL of the adjacent linear processor array (left side in FIG. 4). The template block data from the most upstream element processor PE1 is given to the most downstream element processor PEm of the adjacent linear processor array. That is, the search window data is transmitted via the element processor PE and the data buffer DL, while the template block data is transmitted only via the element processor PE.

The data buffer DL has a delay function as described above, and also has a function of outputting given data in a first-in first-out (FIFO) mode. As a data buffer DL, therefore R
Data latches with shift function may be used, and a register file for storing R data may be used.

As described above, in the processor array 10, by arranging the signal lines for transmitting the search window data and the signal lines for transmitting the template data in parallel, it is possible to secure a sufficient wiring area for the signal lines. In addition, the wiring occupancy area can be minimized. This is because the area corresponding to the width of the element processor PE can be used as the wiring area.

FIG. 5 is a diagram showing another form of this data transfer path. As shown in FIG. 5, the data transfer path may be set so that the template data transfer direction 32 and the search window data transfer direction 30 are orthogonal to each other. In a normal frame memory or the like, since image signals are raster-scanned, image data that is adjacent and continuous in the row direction (horizontal direction in the drawing) is stored. Therefore, in this case, as shown in FIG. 5, when transferring data in the horizontal direction in the figure, the data in the same row can be accessed and sequentially read from the frame memory, which is convenient for reading and transferring the data. Even in this case,
The search window data and the template data are transferred only in one direction in each element processor. Next, the operation will be described.

As shown in FIG. 6, one frame image is converted into 8
Consider a state of being divided into × 8 macroblocks. Figure 6
As shown in (A), a macro block indicated by diagonal lines in the current frame image 36 is a template block TB1. Consider a case where a motion vector is detected for this template block TB1.

In this case, the processor array 10 stores three macroblocks MB1, MB2 and MB3 indicated by diagonal lines in the previous frame image 35 as shown in FIG. 6B. The pixel data of the template block TB1 shown in FIG. 6A is stored in each data register of the element processor PE. One element processor PE stores Q / m template block data arranged in the vertical direction in the figure. On the other hand, for the search window data, Q.n / m pieces of pixel data adjacent in the vertical direction in the drawing are stored in one element processor. Elements of the processor array are Q in the vertical direction and P in the horizontal direction for the processor.
A total of P and Q search window pixel data are stored. This P · Q pixel data will be referred to as search window block pixel data in the following description. The remaining R and P search window pixel data are stored in the data buffer DL. This state is shown in FIG.

That is, the search window data composed of P · Q pixel data is the search window block 4
2 and is stored in each element processor PE of the processor array. The remaining (r1 + r2) · P pixel data are stored in the data buffer DL. The pixel data area 44 stored in the data buffer DL is referred to as a side window block in the following description. In the following description, the search window block 42 and the side window block 44 will be collectively referred to as the search window 40.

In general, one element processor PE stores M template block data and N search window block data, as shown in FIG. By connecting m element processors PE in cascade, the pixel data arranged in one column of Q pieces are stored in the element processor PE in the linear processor array. Next, a specific operation will be described.

To simplify the following description, assume the following conditions. Template block size: P = Q = 16 Motion vector search range: r1 = r2 = 15, t2 =
0, t1 = 15 m = 8 M = N = 2 FIG. 9 is a diagram showing a data storage state in the first operation cycle in the motion vector detection operation. In FIG. 9, the data of the template block 43 consisting of pixel data of 16 rows × 16 columns is stored in each element processor PE of the processor array 10. Correspondingly, the pixel data of the search window block 42 of 16 rows × 16 columns is stored in each element processor PE in the processor array. This state corresponds to the displacement vector (0, -15). In this state, each element processor PE obtains the absolute difference value between the template block data and the corresponding search window block data. The absolute difference value obtained in each element processor PE is transmitted to the summation unit 12, where the summation is executed and this displacement vector (0, −15)
An evaluation value (evaluation function) for is obtained.

Next, the template block data is transferred to one pixel only in the search window block data while being held in each element processor PE.

In this state, as shown in FIG. 10A, the data in the uppermost row in the search window block 42 is transferred to the data buffer DL in the adjacent column, and accordingly the first data in this search window block is transferred. Is shifted out. In parallel with this shift-out, new search window block data is input. The shift-out search window block data and the new shift-in search window block data are indicated by hatched areas in FIG.

As a result, as shown in FIG. 10B, the element processor PE in the processor array 10 stores the search window block 42a which is shifted downward by one line in the search window 40. In this state, the displacement between the template block 43 and the search window block 42a becomes the vector (0, -14).

In this state, the difference absolute value calculation and the summation calculation similar to the above are performed again to obtain the evaluation value for the displacement vector (0, -14).

By repeating this operation, the displacement vector (0,
0), as shown in FIG. 11A, the search window block 42 in the search window 40.
b corresponds to the back of the template block 43. In this state, as shown in FIG. 11B, the data of the search window 40 stored in the processor array is located at a position displaced to the right in the one-column diagram in the upper 15 pixel × 16 pixel area. The search window data of is stored. As described above, the search window data that is unnecessary for the evaluation value calculation operation is shifted out by 1 bit, and the search window data is newly shifted in by one pixel, so that the evaluation value calculation operation is newly performed in parallel. The search window data of the next column is stored.

When the displacement vector finally becomes the (0, +15) state, the search window block 42c is arranged in the lowermost area of the search window 40 as shown in FIG. . After the evaluation value for the displacement vector (0, +15) in this state is calculated, the search window data PY1 that has become unnecessary for one pixel is shifted out from the processor array, and the search window data PY2 is newly shifted. Will be in. After that, the shift operation is repeated 16 times. By this shift operation, all the data necessary for the calculation of the next step are prepared in the processor array.

In the next step, the evaluation value is calculated for the search window which is displaced to the right in the one-column diagram in the search area. That is, as shown in FIG. 13, the next search window 40a in the search area 45 is composed of pixel data at a position displaced to the right in the one-column diagram from the original search window 40. In the state shown in FIG. 12B, the pixel data of the shaded area 50 is stored in the processor array.

The search window 40 shown in FIG. 13 is newly added to each element processor PE in the processor array.
In order to store the search window block located at the top of a, the remaining 15 pixels of data are shifted in as described above in this state (FIG. 12B). As a result, as shown in FIG. 14, a new search window 40 is displayed.
The uppermost search window block 42d in a is stored in each element processor PE of the processor array.

In this state, the displacement vector (1, -15)
Corresponds to a state in which the search window block 42d and the template block 43 corresponding to are stored in the element processor. In this state, the above-described operation is again performed, that is, the evaluation value is derived by calculating the absolute difference value and calculating the total sum. Here, the area of one column shown by the dotted line in FIG. 14 indicates the shifted-out search window data and the shifted-in search window data.

The above shift operation is (15 + 15 + 16)
When it is executed × 15 + (15 + 15 + 1) = 736 times, calculation of the evaluation value for the displacement vector (15,15) as shown in FIG. 15 is executed. That is, in this state, with respect to the template block 43, the search window block 42e at the lower right corner of the search area 45.
Calculation of the evaluation value for is performed.

In this state, as shown in FIG. 16, the data in the shaded area 50a is stored in the element processor in the processor array. 16 remaining
An area (side window area) 52 of x30 pixels is stored in the data buffer. By performing the above operation, all necessary evaluation functions (evaluation values) for the template block 43 can be calculated.
The minimum evaluation value (evaluation function) is obtained in the comparison unit for all of the calculated evaluation functions (evaluation values), and the displacement vector corresponding to this is obtained in this template block 4.
3 is determined as a motion vector.

The above-mentioned movement of the image data will be specifically described by paying attention to the search window pixel data. FIG. 17 now
It is assumed that the processor array 10 includes 64 element processors PE0 to PE63 arranged in 8 rows and 8 columns, as shown in FIG. The buffer DL is not shown in FIG. 17 to simplify the drawing. Each pixel data of the template block is stored in the element processors PE0 to PE63.

As shown in FIG. 18, this template block has pixel data a0, 0 to a arranged in 8 rows and 8 columns.
Including 7, 7. Pixel data a i, j indicates pixel data arranged at the position of the i th row and the j th column in the template block having the size of 8 rows and 8 columns. The template pixel data a0, 0 to a7, 7 are resident in the corresponding element processor during the motion vector calculation period. The search range is assumed to be -8 to +8 in the horizontal direction and -8 to +8 in the vertical direction.
FIG. 19 shows half the search area, that is, 0 to + in the horizontal direction.
8 shows an arrangement of pixel data in the area of the search range of 8. Figure 1
9, the search area includes pixel data b0,0 to b23,15 arranged in 24 rows and 16 columns. Here, the pixel data bi, j indicates the data of the reference pixels arranged in the i-th row and the j-th column in this search area.

In the arrangements shown in FIGS. 17, 18 and 19, as shown in FIG. 20, the displacement vectors (0, -8) .about.
An evaluation value for each (8,8) is calculated. The element processors PE0 to PE63 are arranged in a matrix, but the data transfer direction is only one direction. Therefore, as shown in FIG. 21, the element processors PE0 to PE63 and the buffer BL included in the processor array 10 are arranged in one column with respect to the search window pixel data.

In FIG. 21, processor row PL1 includes element processors PE0 to PE7, and processor row PL2 includes element processors PE8 to PE15. Processor row PLk
Includes element processors PE (8k) to PE (8k + 7). However, k = 0 to 7.

Processor row PLk and processor row PL (k +
The buffer DL (k + 1) is provided between the buffer DL8 and the buffer DL8 (1), and the buffer DL8 is provided at the input section of the processor row PL7 at the most downstream side (position closest to the pixel data input section). Each of the buffers DL1 to DL8 stores data of 16 pixels and transfers the data only in one direction.

As a starting state, as shown in FIG. 21, search window pixel data b0,
1 to 0 are stored in the buffer DL1, and pixel data b8,0 to b23,0 are stored in the buffer DL1.
Consider a state in which the pixel data b of the 0th to 23rd rows and the 0th to 7th columns of the search area shown in FIG. 9 are stored in the corresponding element processors.

The processor columns PL0 to PL7 store the pixel data of the 0th to 7th rows and the 0th to 7th columns of the search area of FIG. At this time, in the element processors PE0 to P63, the template block pixel data a0, 0 to a7 shown in FIG.
Corresponding pixel data is stored in such a manner that 7 and k are stored. This state corresponds to the displacement vector (0, -8), and the evaluation value for this displacement vector (0, -8) is calculated.

In the next cycle, the search window pixel data is shifted. That is, FIG.
As shown in (a), the pixel data b0,0 is shifted out and the pixel data b0,8 is shifted in. This shift operation is a buffer (shown by diagonal lines in FIG. 22)
Through.

In the processor rows PL0 to PL7,
Pixel data of the search window block one row below the search area shown in FIG. 19 is stored. This new search window block corresponds to the displacement vector (0, -7) (template block pixel data is not shifted). When the calculation is performed in this state, the evaluation value for the displacement vector (0, −7) is calculated.

Next, as shown in FIG. 22B, when the pixel data b1,8 in the first row, eighth column is shifted in and the pixel data b1,0 is shifted out, the processor column PL0 is changed. The pixel data stored by PL7 is shifted downward by one row in FIG. That is, the search window block pixel data b is stored in the processor row PLk.
2, k to b9, k are stored. This search window block corresponds to the displacement vector (0, -6), and the evaluation value (evaluation function) for this displacement vector (0, -6) is calculated.

When the shift and calculation operations are repeated, the state shown in FIG. 22C is reached, the pixel data b7, 8 is shifted in, and the pixel data b7, 0 is shifted out. Pixel data b8, k to b1 are stored in the processor row PLk.
5, k are stored. The search window block including the pixel data stored in the processor rows PL0 to PL7 corresponds to the displacement vector (0,0).

After the evaluation value is calculated for the displacement vector (0,0), the shift / calculation operation is performed eight times, as shown in FIG.
As shown in (d), the pixel data b15, 8 is shifted in, and the pixel data b15, 0 is shifted out.
It is stored in the pixel data processor columns PL0 to PL7 of the search window block corresponding to the displacement vector (0, 8). This search window block corresponds to the displacement vector (0,8).

After the evaluation value of the displacement vector (0, 8) is calculated, the evaluation value for the displacement vector (1, -8) is calculated. At this time, it is still the eighth in the search area.
All pixel data in the columns are not shifted in. Therefore, the remaining search window pixel data b1 in the eighth column
6, 8 to b23, 8 are sequentially shifted in, and accordingly unnecessary pixel data b16, 0 to b23, 0 are shifted out. This state is shown in FIG.

In the state shown in FIG. 23 (a), pixel data b0, k + 1 to b7, k are stored in the processor example PLk.
+1 is stored. That is, the displacement vector (1,-
The pixel data of the search window block for 8) is stored in the element processors PE0 to PE63, and the evaluation value for the displacement vector (1, -8) is calculated by using these stored pixel data.

Again, the shift of one pixel data and the calculation operation after the shift are executed. In this case, the pixel data b0 and 9 are shifted in and the pixel data b0 and 1 are shifted out as shown in FIG. 23B, and the evaluation value for the displacement vector (1, -7) is calculated.

After that, the above-mentioned shift / calculation operation is repeated, and as shown in FIG.
Is shifted in, the pixel data b15, 8 is shifted out, and the evaluation value for the final displacement vector (8, 8) is calculated.

The above-described shift operation of the search area pixel data is similar to the operation of connecting the columns of the search area matrix shown in FIG. 19 to form one pixel data column and shifting the pixel data by one pixel. The buffer DL is inserted so that only necessary pixel data (search window pixel data) is stored in the element processor.

In the above structure, the data of the template block resides in each element processor in the processor array. Only the data in the search area shifts in each operation cycle. The scanning direction of the data in the search area at this time is only one direction (from the top to the bottom of the drawing) in the search area 45, as shown in FIG. Since the data transfer in the search area is performed only in one direction, the circuit configuration for selecting the data transfer direction becomes unnecessary, and the circuit scale required for the data transfer can be reduced. Accordingly, power consumption can be reduced.

FIG. 25 is a diagram showing a specific structure of the element processor PE. In the above configuration, only the search window data storage means and the template block data storage means have been described. The specific configuration of the element processor PE will be described below with reference to FIG.

In FIG. 25, the element processor PE is 2
Registers 26-1 and 26-2 for storing cascaded search window data, and a selection signal S
A selector 60 for selecting one of the stored data in the registers 26-1 and 26-2 according to EL0, two stages of cascade-connected registers 25-1 and 25-2 for storing template data, and a selection signal SEL1 It includes a selector 62 for selecting data stored in one of the registers 25-1 and 25-2, and a difference absolute value circuit 64 for obtaining a difference absolute value for the data selected by the selectors 60 and 62. This configuration is M = N in the configuration of FIG.
= 2.

Registers 26-1 and 26-2 form a shift register stage, and transfer and latch data applied according to a clock signal (not shown). Registers 25-1 and 25-2 similarly configure a shift register, and perform shift and latch of template block data applied according to a transfer clock signal (not shown).

The selectors 60 and 62 operate synchronously,
A pair of register 26-1 and register 25-1 or a pair of registers 26-2 and 25-2 is selected.

In the structure shown in FIG. 25, one element processor PE executes an operation on template pixel data of 2 pixels.

The template block data is registered in the register 2
In 5-1 and 25-2, it remains resident until the corresponding motion vector is detected. The registers 26-1 and 26-2 for storing the search window data are
The data is shifted by one pixel for each cycle. The selectors 60 and 62 alternately select two registers during the transfer period of the search window for one pixel. That is, 1 / of the transfer period of search window data
In the cycle of 2, the difference absolute value circuit 64 executes the calculation for obtaining the difference absolute value.

FIG. 26 is a diagram showing an example of a specific configuration of the differential absolute value circuit shown in FIG. 24, the absolute difference circuit 64 receives the search window data from the selector 60 shown in FIG. 25 at its negative input (A), and
Included is a subtractor 70 which receives the template block data from the selector 62 shown in FIG. 5 at its positive input (B). Subtractor 7
0 displays the subtraction result with a signed multi-bit. The code bit S (A> B) is “1” when the search window data is larger than the template block data, and is “0” otherwise. It is assumed that the output of the subtractor 70 is displayed in 2's complement.

The difference absolute value circuit 64 further includes an ExOR circuit 72 that receives the sign bit S (A> B) and the remaining bits (referred to as magnitude bits) from the subtractor 70, and the sign bit S (A> B). 1) to the output of the ExOR circuit 72 according to
Incrementer 74 for adding The incrementer 74 sets Ex when the sign bit S (A> B) is "1".
1 is added to the output of the OR circuit 72. Incrementer 7
4 is Ex when the sign bit S (A> B) is “0”
The output of the OR circuit 72 is passed through as it is without adding 1. The ExCR circuit 72 operates on multi-bit pixel data. Each bit of pixel data is inverted or non-inverted according to the value of the sign bit.

The ExOR circuit 72 outputs the sign bit S (A>
When B) is "0", the magnitude bit from the subtractor 70 (the remaining bits of the output of the subtractor 70 excluding the sign bit) is passed as it is. Sign bit S (A> B)
Is 1, the ExOR circuit 72 inverts each of the magnitude bits of the subtractor 70. That is, the ExOR circuit performs module 2 addition of each bit of the magnitude bits from the subtractor 70 and the sign bit S (A> B).

Subtractor 70 performs the operation (B-A).
If this subtraction result is positive, the sign bit S (A> B) is "0", and if it is negative, the sign bit S (A> B) is "1". The output of the subtractor 70 is displayed in 2's complement. Therefore, the ExOR circuit 72 and the incrementer 74 selectively perform bit inversion and increment by 1 of the subtractor output in accordance with the sign bit S (A> B), and the absolute difference value of | BA is output.

In the structure shown in FIG. 25, the element processor PE includes two search window block data storage registers and two template block data storage registers. This state corresponds to the state of M = N = 2. In this state, the selectors 60 and 62
Performs the selection operation at a cycle twice the bit transfer rate of the search window data, and accordingly, the absolute difference circuit 64 also executes the calculation at a rate twice the bit rate of the search window data. Generally, when N registers are provided, as shown in FIG. 27, the selectors 60 and 62 sequentially select the N registers according to the selection signals SEL0 and SEL1 within one cycle of the search window data transfer. In this case, the differential absolute value circuit executes the operation at a speed N times the bit transfer cycle of the search window data (provided that N = M).

As shown in FIG. 25, two search window block data storage registers and two template block data storage registers are used, and these two sets of registers are alternately driven to perform the absolute difference calculation. By doing so, as shown in FIG. 28, the difference absolute value calculation operation regarding the two pixel data is executed in one element processor. With the above-described configuration, it is possible to obtain the difference absolute value by halving the number of element processors, and it is possible to reduce the size of the processor array. In this case, another advantage can be obtained by providing a plurality of data storage registers.

Now, as shown in FIG. 29, the selection signal SEL0
And SEL1 are switched at a speed twice the transfer speed of the search window data. In this case, the same selection as at the time of calculation for the above-mentioned two pixel data sets is executed. The arithmetic unit activation control signal φS is generated at the same cycle as the search window data transfer rate (see FIG. 29). At this time, only the calculation result (absolute difference value) for the pixel data set initially selected by the selection signals SEL0 and SEL1 is generated. The operation result for the second set of pixel data designated by the second selection signals SEL0 and SEL1 is not output.

The search window block data is shifted by one pixel in each cycle. Template block data remains resident in the processor array until the motion vector is determined. Therefore, in this case, as shown in FIG. 30, it is equivalent to subsampling the calculation result in the motion vector calculation, the evaluation points in the calculation of the absolute difference value can be thinned, and a low-speed calculation circuit is used. An evaluation function (evaluation value) can be generated. This reduces power consumption,
Moreover, the scale of the evaluation value generation circuit can be reduced.

In this case, as shown in FIG. 30, in the element processor, the difference absolute value calculation is executed using only one template block data (in FIG. 30, only the pixel data indicated by diagonal lines in the template block 43). Is used). In this case, in order to perform subsampling, the template block 43
It is not necessary to store all of the pixel data in the element processor in the processor array. A similar effect can be achieved by storing only the required valid data in the element processor.

FIG. 31 is a diagram showing another example of the configuration of the element processor. In FIG. 31, the element processor PE sequentially selects the two-stage cascade-connected search window data storage registers 26-1 and 26-2 and the data stored in the registers 26-1 and 26-2 according to the selection signal SEL. Selector 60, a one-stage register 25 for storing template block data, and a difference absolute value circuit 64 for obtaining a difference absolute value between the data selected by the selector 60 and the data stored in the register 25.

Only valid data (data indicated by diagonal lines) in the template block 43 shown in FIG. 30 is stored in the register 25 for storing the template block. The selector 60 operates in accordance with the selection signal SEL to register 2 at a speed twice as high as the transfer speed of the search window data Y.
The stored data of 6-1 and 26-2 is selected. The absolute difference circuit 64 executes the calculation at the same speed as the transfer speed of the search window data Y. As a result, the absolute difference value between the data stored in one of the registers 26-1 and 26-2 and the data stored in the register 25 is always obtained. The differential absolute value circuit 64 may always execute the operation based on the given data, and the output stage of the differential absolute value circuit 64 may be provided with a subsampling data latch.

With the above configuration, the motion vector for the template block can be calculated at high speed,
Also, the circuit scale of the element processor is reduced.

Instead of using the selector 60, a register 26-1 is provided by wiring so that the evaluation value calculation is performed on the valid data of the template block 43 shown in FIG.
And 26-2 may be configured to transfer data to the absolute difference circuit 64.

FIG. 32 shows an example of the structure of the data register. In FIG. 32, the data register has a shift register configuration. The shift register SR includes an n-channel MOS transistor (insulated gate field effect transistor) NT1 that receives the transfer clock signal φ at its gate.
And a p-channel MOS transistor PT1 receiving the complementary transfer clock signal / φ at its gate. Transistor N
T1 and PT1 form a CMOS transmission gate transmitting the applied data in response to clock signal φ.

Shift register SR further includes an inverter circuit IV1 for inverting the data transferred from transistors NT1 and PT1, an inverter circuit IV2 for inverting the output data of inverter circuit IV1 and transmitting it to the input of inverter circuit IV1. Transfer clock signal / φ
Channel MOS transistor NT2 which receives at its gate
And a p-channel M whose gate receives the transfer clock signal φ.
It includes an OS transistor PT2, an inverter circuit IV3 that inverts the data transmitted by the transistors NT2 and PT2, and an inverter circuit IV4 that inverts the output data of the inverter circuit IV3 and transmits it to the input of the inverter circuit IV3.

Inverter circuits IV1 and IV2 form an inverter latch circuit, and inverter circuits IV3 and IV4 also form the other inverter latch circuit. Transistors NT2 and PT2 are CMs for transmitting the applied data in response to complementary transfer clock signal / φ.
Configure OS transmission gate.

A plurality of shift registers as shown in FIG. 32 are provided in parallel according to the number of data bits.

By utilizing the shift register SR as shown in FIG. 32 as a search window storage data register and a template block data storage data register, one-way transfer of data and selection of data can be easily realized. When data is given to the absolute difference circuit, the data may be taken out from the input part of the inverter circuit IV3.

FIG. 33 is a diagram showing another configuration example of the element processor. In FIG. 33, the element processor PE has an N-word register file 73 for storing N-word search window data, an M-word register file 75 for storing M-word template block data, and an N-word register file 75.
It includes a difference absolute value circuit 64 for calculating a difference absolute value of 1-word data read from the word register file 73 and the M word register file 75. One word corresponds to one pixel data. Data is read out word by word from the N word register file 73 and the M word register file 75, and applied to the absolute difference circuit 64. The register files 73 and 75 include a plurality of registers having a FIFO structure.

In this structure, it is not necessary to provide a selector circuit, and a corresponding pixel data set can be applied to absolute difference value circuit 64 by synchronously reading data in register files 73 and 75. The structure of the register file will be described later in detail. In this case as well, the difference absolute value circuit 64 has a calculation speed determined or a data output speed determined according to its processing method (sub-sampling or sampling of all pixel data).

FIG. 34 is a diagram showing still another configuration example of the element processor. The element processor PE shown in FIG. 34 is the same as the element processor PE shown in FIG.
Instead of 4, the absolute difference value sum circuit 65 is included. That is, in the element processor PE shown in FIG. 34, the calculation of the absolute difference value for the M word template block data stored in the M word register file 75 and the accumulation of the obtained absolute difference values are executed. Since the partial sums of the M template block pixel data are transmitted to the summing unit, the summing operation can be speeded up.

FIG. 35 shows a structure of 1 bit in the register file shown in FIGS. 33 and 34. In FIG. 35, the basic unit of the register file includes memory cells MC arranged corresponding to the intersections of word lines WL and bit line pairs BL and / BL. Memory cell MC
Is an SRAM cell structure having n-channel MOS transistors NT10 and NT12 whose sources and drains are cross-connected and resistance-connected n which functions as a load element for pulling up the storage node SN1 to the "H" level. A channel MOS transistor NT14,
A resistance-connected n-channel MOS transistor NT16 for pulling up the storage node SN2 and the storage node S in response to the signal potential on the word line WL.
Includes n channel MOS transistors NT18 and NT20 connecting N1 and SN2 to bit lines BL and / BL, respectively.

This memory cell MC utilizes substantially cross-coupled inverter circuits as storage elements. The number of constituent elements is six transistors, and the occupied area per bit can be made smaller than that of the shift register shown in FIG.

FIG. 36 shows the overall structure of the register file. In FIG. 36, the register file is
A memory cell array 80 in which the memory cells shown in FIG. 35 are arranged in a matrix, a write address pointer 82 for generating a write address, and one word in the memory cell array 80 is selected according to the address from the address pointer 82, and selected. A write control circuit 84 for writing data to one word, a read address pointer 88 for generating a read word address, and a corresponding word in the memory cell array 80 is selected according to the address from the address pointer 88. A read control circuit 86 for reading the data of the selected word is included. The memory cell array 80 stores one pixel data in one word area. One word may correspond to one word line.

In data writing, address pointer 82 generates a write address, and write control circuit 84 causes a corresponding word line WL in accordance with the generated write address.
And a bit line pair (when multiple words are stored in one word line). Write data is written to the selected word under the control of write control circuit 84. At the time of data reading, word selection is similarly performed by address pointer 88 and read control circuit 86, and the data of the selected word is read.

In the pixel data shift operation, the address in which the oldest data is stored is first generated from the address pointer 88, and the read control circuit 86 selects the oldest data word and stores the data of the corresponding word in the memory. Read from the cell array 80. Address pointer 82
Specifies the address next to the most recently written address. The write control circuit 84 selects the address position next to the most recently written word, and writes the write data at that address position. As a result, the transfer of search window data for one pixel or the transfer of template block data is realized. Since the write path and the read path are different, read data and write data do not collide. This structure can be easily realized by using ring counters having the maximum count value M as the address pointers 82 and 88.

In the operation of calculating the absolute difference value, the read address pointer 88 generates an address so as to sequentially select the M words stored in a predetermined order. In this case, in the case of N> M in which subsampling is performed, the data word is sequentially read from the oldest written data. When N = M and sub-sampling is not performed, address pointer 88 generates an address so as to sequentially read all the word data stored in a predetermined order.

When sub-sampling is performed, only the required data may be read at a given sub-sampling rate.

When N word data or M word data is written in each register file at the initial setting value, data transfer is performed through this register file. In this case, when N or M data words are stored in the most downstream register file, data may be sequentially read and written word by word. With this configuration, when the address of the write address pointer 82 reaches a predetermined value, the read control circuit 8
This is realized by configuring 6 to be enabled.

A path for bypassing write data only to the initial set value to the read data bus path may be provided. In this configuration, when the transfer clock is counted in each register file, the bypass path is cut off when the clock count value reaches a predetermined value, data writing is performed, and when the writing of the predetermined word is completed. Writing of data is prohibited.

The register file shown in FIG. 36 is also shown in FIG.
It can also be used as a data buffer for storing side window data shown in.

FIG. 37 shows an example of a specific structure of the data buffer shown in FIG. In FIG. 37, the data buffer DL includes an R word register 90 that stores R word data. The R word register 90 may have a dual port memory configuration shown in FIG. It may also be composed of a shift register that stores R word data. Furthermore, a configuration in which delay elements such as D latches are connected in cascade may be used.

Unlike the shift register, a register file is used as the delay means, whereby the circuit scale and power consumption can be reduced (because the number of constituent transistors is small).

FIG. 38 is a diagram showing another configuration example of the difference absolute value circuit. The absolute difference circuit shown in FIG. 38 is a subtractor 70 that subtracts search window data and template block data, and an ExOR circuit that receives a magnitude bit and a sign bit S (A> B) of the output of the subtractor 70. 72
including. The absolute difference value circuit 64 shown in FIG.
Unlike the difference absolute value circuit shown in FIG. 6, it does not include an incrementer. The function of the incrementer is to determine the sign bit S (A
> B) is “1”, 1 is added to the output of the ExOR circuit 72. The operation of adding 1 is shown in FIG.
The difference absolute value circuit 64 shown in FIG. It is executed in the summing section in the next stage. That is, the absolute difference circuit 64 shown in FIG. 38 outputs the absolute difference value PE # and the sign bit S # and supplies them to the summing unit of the next stage.

FIG. 39 is a block diagram showing the entire structure of the summation unit when the difference absolute value circuit shown in FIG. 38 is used. In FIG. 39, the summation unit 12 determines the absolute difference values PE # 1 to PE # n from the n element processors and the sign bit S #.
1 to S # n are added. Difference absolute values PE # 1 to PE # n
Is multi-bit data, and sign bits S # 1 to S #
n is 1-bit data. The summing unit 12, whose configuration will be described later, is composed of a compressor including a full adder for receiving the absolute difference values PE # 1 to PE # n. Sign bits S # 1-S # n are applied to the carry input of the least significant bit of this compressor. This will speed up the addition operation and reduce the device scale.

FIG. 40 is a diagram showing an example of a specific structure of the summing unit shown in FIG. In FIG. 40, a configuration in the case of adding the outputs of n element processors is shown as an example. The configuration shown in FIG. 40 is expanded according to the number of element processors.

In FIG. 40, summation unit 12 has values P # 1 to P # corresponding to the absolute difference values from the four element processors.
4 to the inputs A, B, C and D respectively, and the carry input to receive the sign bit S # 1 to perform addition and to output the addition result from the two outputs E and F. Values corresponding to the values P # 5 to P # 8
To the inputs A to D and the sign bit S # 2 to the carry input of the least significant bit, add the given data, and output the addition result from the two outputs E and F. And 4 to 2 which receives the outputs of the 4 to 2 compressors 102a and 102b at their 4 inputs A, B, C and D, and receives the sign bits S # 3, S # 4 and S # 5 at their least significant bit positions. A compressor 102c is included.

The 4 to 2 compressor 102c can receive the sign bits S # 3, S # 4 and S # 5 of 3 bits because the 4 to 2 compressor 102c includes three full adder circuit stages. Is. This configuration will be specifically described later.

The summing unit 12 further receives the outputs (E and F) of the 4-to-2 compressor 102c at its inputs A and B, and has the sign bit S at the carry input of its least significant bit.
Includes adder 104 receiving # 6, S # 7 and S # 8. The summation result is output from the adder 104.

The summing unit 12 has a so-called Wallace Tree configuration, and can carry out addition at high speed with a minimum carry propagation delay. Here, the summing unit 12 shown in FIG. 40 does not include an accumulator. If the calculation speed is faster than the search window data transfer speed, it is necessary to execute additions a plurality of times. Therefore, an accumulator is provided at the output of the adder circuit 104 (when the element processor has a plurality of template block data storage means). The calculation result data (sum of absolute difference values) may be transferred from the element processor to the summing unit for each calculation cycle.

In the above structure, since the sign bit is given to the carry input of the least significant bit, the addition can be executed at a high speed with a small circuit scale. Next, the configuration of the 4-to-2 compressor (4-input 2-output adder) and the specific configuration of the summing unit will be described.

FIG. 41 is a diagram showing an example of a specific configuration of the 4 to 2 compressor shown in FIG. The 4 to 2 compressor shown in FIG. 41 has a configuration for the case where the supplied data has a 4-bit width. The configuration shown in FIG. 41 is expanded as the bit width of the input data increases.

In FIG. 41, the 4 to 2 compressor 10
2 has inputs A and B, carry input Cin, and
Full adders 110a, 110b, 110c and 11 arranged in parallel, each having a carry output Co and a sum output S
Including 0d. 4-bit input data A <3;0> and B are input to A and B inputs of full adder circuits 110a to 110d.
<3;0> is given and input data C <3;0> is given to carry input Cin. Here, "A <3; 0
>"Indicates that the data A is 4-bit data in which the bit A0 is the least significant bit and the bit A3 is the most significant bit.

The 4-to-2 compressor 102 further includes full adder circuits 110e, 110f, 110g for performing addition of the sum output S and carry output Co of the initial stage full adder circuits 110a to 110d and the input data D <3;0>. 110
Including h. The full-addition circuits 110a to 110d and the full-addition circuits 110e to 110h are aligned with each other. The sum output S of the first-stage full adder circuits 110a to 110d is given to the input (A or B) of the corresponding full-adder circuit of the next stage. The carry output Co of the first-stage full adder circuits 110a to 110d is applied to the carry input of the 1-bit higher full adder circuit in the next stage full adder circuit.

In the full adder circuit (FA), 0 is applied to the carry input 104 of the least significant bit full adder circuit 110h. That is, the carry input of full adder circuit 110h becomes an empty carry. In this embodiment, this empty carrier 1
The code bit S # is supplied to 04. 4 to 2 compressor 1
From 02, 5-bit data E <4;0> and F <4;
0> is output. Full adder circuits (FA) 110a-11
The sum output S of 0h gives data bits F <3;0>, and the carry outputs of full adder circuits (FA) 110e-110h give data bits E <4;0>. First-stage full adder circuit 1
The carry output of 10a provides the data bit F <4>.

The 4 to 2 compressor 10 shown in FIG.
In the configuration of 2, there is no carry propagation. The delay time required for the calculation is only for two full adder circuits. Thereby, the addition can be executed at high speed. Further, since the configuration is such that the sign bit S # is given to the empty carrier 104, the addition of absolute difference values can be executed without increasing the circuit scale.

FIG. 42 is a diagram showing a specific connection form of the circuit configuration shown in FIG. The summation section shown in FIG. 42 is
The 4 to 2 compressor shown in FIG. 41 is used. Now, the absolute difference value P # i is represented by (Pi3, Pi2, Pi1, Pi0).

The 4-to-2 compressor 102a has full adder circuits FA1 to FA4 for adding the absolute difference values P # 1 to P # 3.
And the outputs of the full adders FA1 to FA4 and the absolute difference value P #
4 and full adders FA5, FA6, A7 and FA8 are included. Sign bit S # 1 is applied to the carry input of full adder circuit FA8.

The 4-to-2 compressor 102b includes full adder circuits FA9 and FA1 for adding the absolute difference values P # 5 to P # 7.
0, FA11 and FA12, and full adder circuits FA9-F
Full adder circuits FA13, FA14, FA15 and FA16 for adding the output of A12 and absolute difference value P # 8 are included. Sign bit S # to carry input of full adder FA16
2 is given.

The 4 to 2 compressor 102c outputs the output of the 4 to 2 compressor 102a and the 4 to 2 compressor 10.
2b one output (sum output of full adder circuits FA13 to FA16 and carry output of full adder circuit FA9) full adder circuits FA17 to FA21 and full adder circuit FA17
To FA21 and full-addition circuits FA22 to FA26 for adding the other output of the 4-to-2 compressor 102b (carry output of full-addition circuits FA13 to FA16). Sign bits S # 4 and S # 5 are applied to the carry input and one input of full adder circuit FA26.

Adder 104 includes full adder circuit FA27 for adding sign bits S # 6 to S # 8, and full adder circuit FA28 for adding the output of full adder circuit FA27 and the output of 4-to-2 compressor 102c. FA33 and full adder circuits FA34 to FA39 which receive the outputs of full adder circuits FA28 to FA33 and output the final addition result. Full adders FA28 to FA33 form a 3 to 2 compressor. Full adders FA34 to FA39 form a ripple carry type adder. Other adder configurations (eg, carry look ahead adders) configurations may be utilized.

As shown in FIG. 42, by using a compressor to perform addition, the delay caused by carry propagation can be minimized, and the addition can be performed at high speed.

FIG. 43 is a diagram showing a specific structure of the comparison unit shown in FIG. In FIG. 43, the comparison unit 3 includes a register latch 130 for storing an evaluation value (evaluation function) given from the summation unit, an evaluation value stored in the register latch 130, and an evaluation value newly given from the summation unit ( A comparator 132 for comparing the size of the evaluation function), a counter 134 for counting the number of evaluation value calculation cycles, and a comparator 13.
A register latch 136 for storing the count value of the counter 134 in response to the output of 2 is included. Register latch 13
6 may output the motion vector as it is, or may be provided with a decoder that encodes the output of the register latch 136 in a predetermined format, as indicated by a broken line block 137 in the figure. Next, the operation will be described.

The counter 134, the register latch 130, and the register latch 136 are reset at the start of operation of the motion vector for one template block. The initial setting value of the register latch 130 is set to a value larger than the maximum evaluation value (for example, all bits “1”). When the evaluation value for one displacement vector is given, the comparator 132 compares the value stored in the register latch 130 with the evaluation value given by the summing section. Comparator 132 generates a latch instruction signal when the evaluation value (evaluation function) newly given from the summing unit is smaller than the value stored in register latch 130. The register latch 130 stores the evaluation value (evaluation function) given from the summing unit in response to the latch instruction signal. Similarly, the register latch 136 also latches the count value of the counter 134 as a motion vector candidate.

The counter 134 for the next displacement vector
Increments the count value by 1 in response to the control signal φC. When the calculation of the evaluation value is completed, the comparator 132 compares the size of the evaluation value (evaluation function) newly given from the summing unit with the value stored in the register latch 130. The newly given evaluation value is the register latch 130.
If it is larger than the value stored in, the comparator 13
2 does not generate a latch instruction signal. When the newly provided evaluation value (evaluation function) is smaller than the value stored in register latch 130, a latch instruction signal is generated. This operation is executed for the evaluation values for all displacement vectors. As a result, the register latch 130 stores the smallest evaluation value of all the evaluation values.
Further, the register latch 136 latches the count value of the counter 134 indicating the operation cycle that gives the minimum evaluation value. The count value of the counter 134 is used as a motion vector.

After the motion vector is obtained, the counter 134 and the register latches 130 and 136 are initialized again, and the motion vector for the next template block is calculated.

A dynamic random access memory or a static random access memory may be used as a frame memory for storing image data. In the case of a random access memory, a high speed operation mode such as page mode is used when reading continuous data.

A controller for reading out image data from the frame memory and giving it to the processor array may be provided in the motion vector detecting device.

[Embodiment 2] FIG. 44 is a diagram schematically showing the overall structure of a motion vector detecting device according to a second embodiment of the present invention. In FIG. 44, the motion vector detection device receives the search window data Y and the template block data X, and determines the motion vector with integer precision. The first calculation device 210 and the search from the first calculation device 210. A second arithmetic unit 250 for directly receiving the window data SY and the template block data TX to determine a motion vector with a fractional precision is included.

As shown in the first embodiment, the first arithmetic unit 210 includes a processor array 10 including element processors arranged in a two-dimensional array, and a processor array 1.
It includes a summation unit 12 that sums the absolute difference values from each element processor of 0, and a comparison unit 3 that determines a motion vector according to the summation (evaluation value) from the summation unit 12. Processor array 1
When the template block data TX and the search window data SY stored in 0 are shifted out according to the operation, they are directly applied to the second arithmetic unit 250. The operation of the second arithmetic unit 250 is controlled by the comparison result instruction (latch instruction signal) from the comparison unit 3.

In the structure of the motion vector detecting device shown in FIG. 44, the search window data and the template block data are once read from the frame memory and then used for motion vector detection with integer precision in the first arithmetic unit 210. Then, the used search window data and template block data are transferred from the first arithmetic unit to the second arithmetic unit. As a result, it is not necessary to access the frame memory during the motion vector determination operation with fractional precision, and the motion vector with fractional precision can be determined at high speed.

FIG. 45 shows the first embodiment of this second embodiment.
Processor array 10 and second processor unit 210 included in
It is a figure which shows an example of a structure of the data transmission system with the arithmetic unit 210 of this. In FIG. 45, the template block data TX from the processor array 10 is directly supplied to the second arithmetic unit 250, while the search window data SY from the processor array 10 is delayed by the delay circuit 260 for a predetermined time and then buffered. It is stored in the memory circuit 270. The buffer memory circuit 270 stores search window data required for motion vector detection with fractional accuracy. For example, the size of a macroblock (template block and search window block) is 1
In the case of 6 pixels x 16 pixels, 18 pixels x 18 including the periphery as a search window block in terms of fractional accuracy
The pixel is stored in the buffer memory circuit 270.

The search window data stored in the buffer memory circuit 270 and the template block data TX from the processor array 10 are used to determine a motion vector with a fractional precision. The delay time provided by the delay circuit 260 is determined by the storage capacity of the buffer memory circuit 270. When the buffer memory circuit 270 has a capacity for storing all pixels in the search area, the delay circuit 260 may not be provided. Now, consider a state in which the storage capacity of the buffer memory circuit 270 is set to a minimum capacity of 18 pixels × 18 pixels. The delay circuit 260 gives, for example, a delay time equal to the time required to transfer pixels in one column in the search area.

FIG. 46 shows an example of a specific structure of the buffer memory circuit shown in FIG. 45. In FIG. 40,
The buffer memory circuit 270 is a memory 272 that stores the search window data SY from the processor array 10.
And a write / read control circuit 274 for controlling writing and reading of data in memory 272. The output node Do of the memory 272 is connected to the second arithmetic unit 250.

The writing / reading control circuit 274 is connected to the memory 27.
Write address generating circuit 2 for generating write address to 2
81, a read address generation circuit 283 for generating a read address of the memory 272, and a control circuit 28 for generating a signal for controlling the read mode and the write mode of the memory 272.
6 and a selector 284 which selects one of a write address and a read address and supplies it to the address input node A of the memory 272 under the control of the control circuit 286.

Write address generating circuit 281 generates a write address in response to latch designating signal Rφ from the comparator shown in FIG. When this latch instruction signal Rφ is generated, the write address is reset to the initial value. Write address generating circuit 281 sequentially generates write addresses from address 0 in response to clock signal φ. Similarly, the read address generation circuit 283 sequentially generates read addresses from address 0. The selector 281 is the control circuit 28.
When 6 indicates data writing, the write address from write address generating circuit 281 is selected. If the control circuit 286 indicates the read mode, the selector 2
Reference numeral 84 selects the read address from the read address generation circuit 283.

Control circuit 286 responds to search window data transfer clock signal φ to generate a signal for determining the data writing timing and reading timing to memory 272. Control circuit 286 also generates a signal for controlling writing and reading of memory 272 in response to operation mode instruction signal φRW. When the memory 272 is composed of a dynamic random access memory, the control circuit 286 controls the row address strobe signal / RAS, the column address strobe signal CAS, the write enable signal / WE and the output enable signal / OE (the output is in three states). And if it is).

Control signal φR applied to control circuit 286
W may be given from an external controller. A count-up signal may be generated when the count value of the counter 134 of the comparison unit 3 shown in FIG. 43 reaches a predetermined count value, and this count-up signal may be used as the control signal φRW. This is because the evaluation value is continuously derived for one template block until the counter (see FIG. 43) reaches a predetermined count value. Next, the operation will be described.

Now, as shown in FIG. 47, assume that the search window has a size of 48 pixels × 16 pixels, and the macro block (template block and search window block) has a size of 16 pixels × 16 pixels. Think Now, it is assumed that the search window block 42 is being evaluated. The area required to obtain the fractionally accurate motion vector for the search window block 42 is 18 pixels including the area 42.
An area 48 of 18 pixels. The area 48 includes pixel data P0 to P325 as shown in FIG.

As shown in FIG. 48, the clock signal φ is
This is generated at each transfer of the search window pixel data. When one clock signal φ is generated, the search window data is shifted out by one pixel. In the operation of calculating the evaluation value for the search window block 42, the output of the delay circuit 260 shown in FIG. 45 is the data corresponding to the pixel P0. At this time, when the evaluation value of search window block 42 is the smallest among the evaluation values obtained so far, latch instruction signal Rφ is generated from the comparator shown in FIG. In response to this, the write address of write address generating circuit 281 shown in FIG. 47 is reset to initial value 0. The pixel data P0 is written in the position of address 0 of the memory 272. After that, data of 18 pixels, that is, P1 ... P17 are continuously stored in the positions of addresses 1 to 17 (when the signal Rφ is not generated).

Then, in order to prohibit the writing of unnecessary data, write address generating circuit 281 is in the idle state for 30 clock periods, that is, 30φ, and memory 272 is in the write inhibit state. To determine the write-prohibited rest period, latch instruction signal Rφ is applied to control circuit 286 again, and control circuit 286 counts clock signal φ 18 times after latch instruction signal Rφ is applied and then 30φ
A configuration is used in which the period memory 272 is put in a dormant state.

30 clock periods (30φ cycle period)
When elapses, the write address generation circuit 281 again generates the write address. The address at this time is address 1
8 and the pixel data P18 is at the position of this address 18.
Is stored. Thereafter, this operation is repeatedly executed. When the template block is changed, the search area is horizontally shifted by one macroblock size. Therefore, even if the macro block giving the motion vector is in contact with the boundary of the search area, all the data necessary for the fractionally accurate motion vector detection can be obtained. In this case, data outside the search area may be ignored. Adjacent data may be used.

As a result of the above-described operation, the memory 272 always stores only the data of the search window block corresponding to the displacement vector which is the motion vector candidate. At this time, the memory 272 has a minimum storage capacity of 18 words × 18 words, and the device configuration can be reduced.

In the case where buffer memory circuit 270 is constructed to store all pixel data of the entire search area for one template block, delay circuit 260 may not be provided. At this time, the read address is generated according to the value of the motion vector from the comparison unit 3 (FIG. 43).

FIG. 49 is a diagram showing a specific structural example of the second arithmetic unit shown in FIG. In FIG. 49, the second arithmetic unit 250 is the first arithmetic unit (processor array).
Generated by the fractional precision predicted image generation circuit 302 and the fractional precision predicted image generation circuit 302 that receives the search window data (more accurately, the output of the buffer memory) from The difference absolute value sum circuit 304 for obtaining the difference absolute value sum between the pixel data of the predicted image and the template block data X, and the displacement vector giving the smallest sum of the difference absolute values among the outputs of the difference absolute value sum circuit 304 are detected. The comparison unit 306 is included.

The fractional precision predicted image generation circuit 302 generates a plurality of predicted image pixel data in parallel. The difference absolute value sum circuit 304 also generates an evaluation value for a displacement vector that is a motion vector candidate in a parallel manner. Comparison unit 306
Detects the smallest sum of absolute values among the plurality of sums of absolute differences given from the sum of absolute differences circuit 304, and determines the displacement vector corresponding to the smallest sum of absolute values as a motion vector. Next, a specific configuration of each circuit configuration will be described.

FIG. 50 is a diagram showing a specific configuration example of the fractional precision predicted image generating circuit shown in FIG. In FIG. 50, a fractional accuracy predicted image generation circuit 302 includes a delay circuit 31 that delays given search window data for a predetermined time.
0, an adder 312 that adds the output of the delay circuit 310 and the search window data Y, and a multiplier 314 that multiplies the output of the adder 312 by a coefficient (1/2).

Multiplier 314 may be formed of a shifter that shifts data applied in the direction of the lower bit of 1 bit. The delay time provided by the delay circuit 310 is determined by which displacement vector the fractional accuracy predicted image generation circuit 302 corresponds to. The delay time of the delay circuit 310 will be described later. The fractional accuracy predicted image generation circuit 302 shown in FIG. 50 is used to detect a motion vector with 1/2 pixel accuracy.

FIG. 51 shows an example of a specific structure of the difference absolute value sum circuit shown in FIG. In FIG. 51,
The absolute difference sum circuit 304 subtracts the interpolation data YF given from the fractional accuracy predicted image generation circuit 302 and the template block data X, and the absolute value circuit 322 for obtaining the absolute value of the output of the subtractor 320. When,
An accumulator circuit 324 for accumulating the output of the absolute value circuit 322 is included. Next, a specific configuration example of the second arithmetic device for obtaining the motion vector with the fractional accuracy will be described.

FIG. 52 is a diagram showing an operation for obtaining a motion vector with a fractional accuracy in the second arithmetic unit. Second
The arithmetic unit 250 of 1 detects the motion vector with 1/2 pixel accuracy. Now consider 8 points as motion vector candidates.
That is, the pixel data of the eight neighborhoods Q1 to Q4 and Q6 to Q9 of the pixel of interest P are obtained by interpolation. Pixel data Q1 to Q4 and Q6 to be obtained by this interpolation
The absolute difference value between each Q9 and the template block data X is calculated and accumulated to calculate an evaluation value indicating a motion vector candidate.

Now, search window data are set to P1 to P9.
The period between adjacent column pixels is T, and the delay time between adjacent rows is H (18T: when the search window block size with fractional accuracy is 18 pixels × 18 pixels). Here, in FIG. 52, the arrangement of rows and columns is transposed to that of the above-described embodiment. The search window block data from the processor array is sequentially shifted out along the column direction of the search window, and the template block data is similarly shifted along the column direction (template block data transmission line and search window data). If the transmission lines and are arranged parallel to each other). In this case, it suffices to simply change the reference number given to each pixel data (change the row and the column), and there is no particular problem. Interpolation search window data Q1 shown in FIG.
Next, a configuration for obtaining a motion vector with fractional accuracy using Q4 to Q4 and Q6 to Q9 will be described.

FIG. 53 is a diagram showing a specific structure of the second arithmetic unit. In FIG. 53, the second arithmetic unit 250
Includes a delay circuit 335a that delays the supplied search window data for 1H period, and a delay circuit 335b that further delays the output of this delay circuit 335a by 1H. These two stages of cascaded delay circuits 335a and 335b form a path for generating data corresponding to each row in FIG.

In FIG. 53, the second arithmetic unit further includes a delay circuit 336a for delaying the input search window data P for 1T period, a delay circuit 336d for delaying the output of the delay circuit 336a for another 1T period, and a 1H delay circuit. Three
A delay circuit 336b for delaying the output of 35a by 1T period;
Delay circuit 3 for delaying the output of delay circuit 336b for 1T period
36e, a delay circuit 336c that delays the output of the 1H delay circuit 335b for 1T period, and an output of the delay circuit 336c that is 1
It includes a delay circuit 336f that further delays for the T period. This one
Search window data required for interpolation is generated by the T delay circuits 336a to 336f.

The second arithmetic unit 250 further adds the input search window data P and the output of the 1T delay circuit 336a and multiplies them by a coefficient (1/2).
Including 0a. The addition shift circuit 330a has a coefficient (1/2)
The multiplication of is realized by the shift operation. The second arithmetic unit 250 further includes the output of the 1T delay circuit 336a and the 1T delay circuit 336a.
An addition shift circuit 330b that performs an addition shift operation on the output of the delay circuit 336e, an addition shift circuit 330c that performs an addition shift operation on the outputs of the 1T delay circuit 336b and the 1T delay circuit 336e, and a 1H delay circuit. Addition shift circuit 330d that performs addition shift operation on the output of 335a and the output of 1T delay circuit 336b
And the output of the 1H delay circuit 335b and the 1T delay circuit 336.
An addition shift circuit 330e that performs an addition shift operation on the output of c and an addition shift circuit 330f that performs an addition shift operation on the outputs of the 1T delay circuit 336c and the 1T delay circuit 336f are included. The addition shift circuits 330a to 330f generate data for generating interpolation data between four pixels.

The second arithmetic unit 250 further executes an add shift circuit 330g for performing an add shift operation on the output of the add shift circuit 330a and the output of the add circuit 330d.
And the output of the 1T delay circuit 336a and the 1T delay circuit 336
b and the addition shift circuit 330h that performs the addition shift operation on the output of b, the addition shift circuit 330i that performs the addition shift operation on the outputs of the addition shift circuit 330b and the output of the addition shift circuit 330c, and the 1T delay circuit 336.
b and the output of the 1H delay circuit 335a, an add shift circuit 330j that performs an add shift operation, and an add shift circuit that performs an add shift operation on the output of the 1T delay circuit 336e and the output of the 1T delay circuit 336b. 330
k, an output of the addition shift circuit 330d and an output of the addition shift circuit 330e, an addition shift circuit 330l that performs an addition shift operation, an output of the 1T delay circuit 336b, and an output of the 1T delay circuit 336c. And an addition shift circuit 330m for executing
And an add shift circuit 330n that performs an add shift operation on the output of 30c and the output of add shift circuit 330f. Interpolation pixel data Q9 to Q6 and Q4 to Q1 shown in FIG. 52 are added from the addition shift circuits 330g to 330n.
The pixel data at the position of is generated.

The absolute difference sum circuit 304 outputs the outputs Q9 to Q6 and Q4 to Q of the addition shift circuits 330g to 330n.
The difference absolute value sum circuit 304 which receives 1 and the template block data A and calculates the sum of difference absolute values of given signals
a to 304h are included. The search window block data P and the template block data A are in the relationship of the back side.

The outputs of the difference absolute value sum circuits 304a to 304h are applied in parallel to the comparison unit 306, and the displacement vector which gives the minimum difference absolute value sum is detected as a motion vector. The comparison unit 306 uses the absolute difference value sum circuit 30.
The outputs of 4a to 304h are compared, and the code attached to the difference absolute value sum circuit that gives the minimum value is output as a motion vector. Each of the absolute difference value sum circuits 304a to 304h corresponds to a displacement vector giving eight evaluation points. Therefore, this allows the motion vector to be determined with fractional accuracy.

In the structure shown in FIG. 53, only one or four absolute difference value summing circuits are provided, which are activated in a time division manner to sequentially add and accumulate the outputs of the addition shift circuits 330g to 330n. Good. In the case of this shared structure, the accumulation result in the difference absolute value sum circuit is stored in the register file, and the accumulation operation is executed using the value of the register file. In this case, the comparison unit 306 is shown in FIG.
A configuration similar to that of the comparison unit shown in can be used. This is because the sequential comparison operation is executed.

Further, in the above configuration, the motion vector is detected with 1/2 pixel precision. A configuration for detecting a motion vector with finer fractional precision such as ¼ pixel precision may be used. Although the evaluation score is 8 points, a configuration in which more evaluation points are used may be used.

FIG. 54 is a diagram showing a modification of the second embodiment of the present invention. In the motion vector detection device shown in FIG. 54, the first method for detecting a motion vector with integer precision
Buffer memories 280 and 282 are provided between the arithmetic unit 210 and the second arithmetic unit 250 for detecting a motion vector with a fractional precision. Buffer memory 28
0 and 282 store the template block data TX and the search window data SY output from the first arithmetic unit 210, respectively. Buffer memory 2
The configuration of 80 and 282 is similar to that shown in FIG.

The buffer memory 280 has a capacity for storing pixel data of all template blocks,
The buffer memory 282 may have a capacity for storing pixel data of all search areas for this template block. The buffer memory 282 may have a capacity to store only pixel data of an area required for motion vector detection with fractional accuracy, as in the previous embodiment.

In the structure shown in FIG. 45, the template block data TX from the first arithmetic unit 210 is directly applied to the second arithmetic unit 250. In the case of that configuration, the motion vector detection operation period with the fractional accuracy is the load period of the template block data to the processor array included in the first arithmetic unit 210. This is because the template block data is sequentially shifted out from the processor array during this period. In this case, the second arithmetic unit 250 is required to perform arithmetic at an operation speed substantially the same as the transfer speed of the template block data.

However, by providing the buffer memories 280 and 282 for both the template block data TX and the search window data SY as shown in FIG. 54, the second arithmetic unit 250 executes the arithmetic operation with a sufficient margin. be able to. Further, it becomes easy to apply the template block data TX and the search window data SY to the second arithmetic unit 250 at the same timing.

In this case, as shown in FIG. 55, the first
The arithmetic operation in the arithmetic unit 210 and the second arithmetic unit 250 can be pipelined. here,
FIG. 55 is a diagram showing an operation mode of the motion vector detection device shown in FIG. 54, and the horizontal axis shows time. In the first arithmetic unit 210, the process for the Nth macroblock (template block) is performed, and after the motion vector determination operation for this Nth macroblock (template block) is completed, the process for this Nth macroblock is performed. Second arithmetic unit 250 using the search window data and template block data used for
In, the motion vector detection with fractional precision for the Nth macroblock is performed. In parallel with the motion vector determination operation with fractional precision of the Nth macroblock, the motion vector detection operation with integer precision for the (N + 1) th macroblock (template block) is performed in the first arithmetic unit. Run.

By thus pipelining the operation of the first arithmetic unit 210 and the second arithmetic unit 250, the operation of the first arithmetic unit 210 and the second arithmetic unit 25
The arithmetic operation at 0 can be executed separately from each other in time, and the motion vector detection with the fractional accuracy can be executed with a margin in the timing requirement for the arithmetic operation. Also in this case, the first arithmetic device 210 and the second arithmetic device 250 operate in parallel with each other, and the motion vector can be detected at high speed with fractional accuracy.

In the structure shown in FIG. 54, buffer memory 280 is used to store template block data TX, but it may be an element (delay line or line memory) having a delay function.

FIG. 56 shows still another modification of the second embodiment of the present invention. In FIG. 56, the portion of the first arithmetic unit that detects a motion vector with integer precision is shown. In FIG. 56, the first arithmetic unit 400 is
Element arithmetic units 411a to 411w connected in series are included. Each of the element arithmetic units 411a to 411w has the same configuration, and registers 413a to 413w for latching search window data and registers 414a to 414w for latching template block data.
And corresponding search window registers 413a-41
3w and template block data storage register 41
Included are absolute difference circuits 412a to 412w for obtaining absolute difference values of the data values stored in 4a to 414w.

Each of the registers 413a to 413w can transfer data along one direction. Each of the registers 414a to 414w can also transfer the stored data to the adjacent element arithmetic unit along one direction.
The search window register 413a of the element arithmetic unit 411a at the first stage is connected to the frame memory 4 via the signal line 415.
The search window data is transmitted from 01. The template block data is transmitted from the frame memory 402 to the template block data register 414a of the element calculator 411a via the signal line 416.

The frame memory 401 stores all pixel data of the reference frame image (previous frame image). The frame memory 402 stores all pixel data of the current frame image. The element calculators 411a to 411w are provided by the number corresponding to the size of one macroblock. That is, when the template block size is 16 rows × 16 columns, a total of 256 element calculators 411a to 411w are provided.

The first arithmetic unit 400 further includes a summation unit 417 for adding the outputs of the absolute difference circuits 412a-412w of the element arithmetic units 411a-411w.
It includes a comparison unit 418 which detects the minimum evaluation value in response to the output of the summation unit 417 and determines the displacement vector of the corresponding search window block as the motion vector.

In the structure shown in FIG. 56, template block data is stored in registers 414a to 414w and one search window block data is stored in registers 413a to 413w in first arithmetic unit 400. When one operation cycle (evaluation value determination cycle) is completed, one row or one column data of the search window block is shifted out.

Also in this case, the shifted-out search window data SY is given to the second arithmetic unit, and similarly the template block data TX is shifted out in the next motion vector detection cycle.
It is provided to the second arithmetic unit. Of the shifted-out search window data SY, the search window data required for the motion vector with fractional accuracy is shown in FIG.
It is retrieved using the configuration shown in.

In the structure shown in FIG. 56, all the registers 414a to 414w are set to the through state, the same template block data is given to the element arithmetic units 411a to 411w, and one window of search window data is input to the registers 413a to 413w. The same effect can be obtained by shifting in and shifting out by minutes. In this case, the unit window is supplied with the search window data such that the supplied template block TX and the supplied search window data always have the same displacement vector. In that case, a difference absolute value sum circuit is used instead of the difference absolute value circuit. Other configurations may be used as long as they are circuit configurations having a function of detecting a motion vector with integer precision.

Further, as shown in FIG. 56, in the case where the element arithmetic units are cascade-connected, the search window data required for the fractional accuracy can be easily obtained. That is,
A shift register is provided at the output stage of the search window data, and a latch circuit for latching the search window data at appropriate intervals is provided in the element calculator. The position where this latch circuit is arranged corresponds to a position outside one pixel from one search window block. That is,
Inside the first arithmetic unit 400, all the search window data required for fractional precision are latched, and only the element arithmetic unit corresponding to the pixel data required for motion vector detection with integer precision is latched. Are arranged to detect the motion vector with integer precision.

In this case, the template block data T
Since the search window data required for the fractional precision is sequentially shifted out in parallel with the transmission of X, it is possible to easily obtain the required window data in the reference frame when detecting the motion vector with the fractional precision. Is possible and the device configuration is simplified.

For example, when the size of the template block and the search window block is 16 pixels × 16 pixels, the block size of the search window required for detecting the motion vector with the fractional accuracy is 18 pixels × 18 pixels. At this time, a shift circuit that latches the first 18 pixels is provided in the output stage, and then a latch circuit that latches the upper and lower 1-bit data of each column of the search window block (16 pixels × 16 pixels) Is arranged at a predetermined position between the element calculators. In this case, the search window data required for the fractional accuracy is read from the frame memory and given to the first arithmetic unit. This state is shown in FIG.

In FIG. 57, element calculators 411a-4d.
The data of the search window block 434 is stored in 11f. In FIG. 57, a state in which the search window block data YB is stored in the element calculator 411d is illustrated. When detecting a motion vector with a fractional accuracy, the pixel data of the area 438 including the peripheral pixels 436 of the search window block 434 is used. The data in the peripheral pixel area 436 is stored in each latch and shift register. In FIG. 57, the state where the data of the peripheral pixel YA is latched by the latch 430a is shown, and the peripheral pixel column (represented by the pixel YC) is stored in the shift register 432a of the output stage and the other pixel column ( The pixel YD) is stored in the shift register 432b of the input unit. All the data in the area 438 is read from the frame memory 401. However, the search window data in one column or one row of the area 438 is shifted in and out in each evaluation value generation cycle.

With this configuration, the pixel data required for motion vector detection with fractional precision can be easily generated and given to the second arithmetic unit for detecting motion vector with fractional precision. Further, the element calculators 411a to 411
b may be arranged in a matrix (the data transfer direction may be substantially one direction).

[Embodiment 3] In both Embodiments 1 and 2 described above, a motion vector is detected for one template block. In this case, the motion vector detecting operation can be performed on the two template blocks in parallel. The configuration will be described below.

FIG. 58 shows the sizes of the search area and template block. In FIG. 58, the search area 4
5 has a size of 48 pixels × 48 pixels, and the template block 43 has a size of 16 pixels × 16 pixels.
Search range is +16 to -16 in the horizontal direction and +1 in the vertical direction
6 to -16.

Now, as shown in FIG. 59, consider the operation of detecting a motion vector using two adjacent macroblocks TB1 and TB2 in the current frame image 49 as template blocks. In this embodiment, the configuration of the processor array shown in FIGS. 1 and 4 is used. The pixel data of the search window 40 shown in FIG. 60 is stored in the processor array.

Now, let us consider a state in which the search window block 42 is stored in each element processor in the processor array as shown in FIG. At this time, the displacement vector for the template block TB1 is (0, -16), and for the template block TB2, the displacement vector (motion vector candidate) is (-16, -16). For the search window block 42a,
The displacement vector of the template block TB1 is (+1
6, -16), and the displacement vector for the template block TB2 is (0, -16). The calculation of the evaluation value for these two template blocks TB1 and TB2 is executed in parallel.

In the element processor PE of the processor array, a search window block 42 shown in FIG. 60 is stored. Similarly, the pixel data of the template blocks TB1 and TB2 are stored in the respective element elements in the processor array while maintaining the arrangement order on the screen. The structure of this element processor will be described later.
The basic operation of the element processor is the same as that described in the first and second embodiments.

First, as shown in FIG. 61, using the search window block 42, the displacement vectors (0, -16) and (-1) of the template blocks TB1 and TB2.
The evaluation value for 6, -16) is calculated.

When the calculation of the evaluation values for the displacement vectors (0, -16) and (-16, -16) is completed, the processor array executes the shift operation for one pixel.

In this state, as shown in FIG. 62, the search window block 4 in the search window 40 is searched.
2 is shifted downward in the one-row diagram (indicated by block 42a). In this state, the displacement vector of the template block TB1 with respect to the search window block 42a is (0, −15), and the displacement vector of the template block TB2 is (−16, −15).
Is. An evaluation value is calculated for each displacement vector.

This operation is repeated. When 33 cycles are completed, as shown in FIG. 63, the pixel data of the search window block 42b is stored in the element processor in the processor array. In this state, the template block T
The displacement vector of B1 is (0,16), and the displacement vector of the template block TB2 is (-16,16).
Becomes When the search window data is further shifted, the search window 40 shifts to the right in the one-column diagram, and the motion vector is evaluated using the new search window 40a.

That is, as shown in FIG. 64, the motion vector is evaluated using the uppermost search window block 42c in the new search window 40a. The displacement vector of the template block TB1 is (1, -15) for the search window block 42c, and the displacement vector of the template block TB2 is (-15, -16).

After this operation is repeated, when the evaluation of the motion vector for the lowermost search window block 42d of the final search window 40b is completed,
The motion vector determination cycle for template block TB1 is completed. Before the search window 40 is given, it is considered that 16 columns of horizontal components -16 to -1 have already been processed. In this state, the evaluation value can be calculated for the evaluation point 1089 indicating the motion vector candidate for the template block TB1, and the motion vector is calculated. By repeating this operation for template block TB2, the motion vector can be detected.

That is, as shown in FIG. 65, the motion vector evaluation operation of the template blocks TB1 and TB2 can be executed in a parallel manner by overlapping the half cycles of the motion vector detection cycles. . Thereby, it becomes possible to execute motion compensation of an image at high speed. Next, a configuration for parallelly evaluating motion vectors for these two template blocks will be described.

FIG. 66 is a diagram showing the structure of an element processor used in the third embodiment of the present invention. In FIG. 66, the element processor PE is a search window data register 505c for storing the search window data given from the adjacent element processor, and a right window for storing the pixel data of the template block on the right side given by the adjacent element processor. Template data register 50
5a, a left template data register 505b for storing pixel data of a template block given from an adjacent element processor, a selector 506 for selecting one of the outputs of the template data registers 505a and 505b, and a register 505c. The output and the output of the selector 506 are connected to signal lines 510 and 50, respectively.
9 includes a differential absolute value circuit 507 for receiving the differential absolute value and performing a differential absolute value calculation.

The output of the absolute difference circuit 507 is the signal line 51.
It is given to Sowabe via 1. The element processors PE shown in FIG. 66 are arranged in a two-dimensional array as shown in FIG. The template block data is updated after the motion vector evaluation is performed on 16 columns (16 columns in the search area) for the horizontal component. At this time,
Instead of updating the right side template block and the left side template block at the same time, only the data stored in one of the template block data registers may be updated. The selection timing of the selector 506 is switched accordingly. The order in which one template block is selected may be the same in any operation cycle.

As the configurations of the absolute difference circuit 507 and the summing unit, the same configurations as those described in the first and second embodiments are used. Since the operation of this element processor PE is the same, it will not be repeated in detail. Selector 506
Causes template data registers 505a and 505
05b are sequentially selected, and the absolute difference value from the search window block data stored in the search window data register 505c is obtained. Difference absolute value circuit 50
From 7, therefore, the absolute difference value for the right template block data and the absolute difference value for the left template block data are provided to the summing section in a time division manner.

67 and 68 are diagrams showing a structure for generating the right side template block data and the left side template block data. In FIG. 67, the right template block data is read directly from the current frame image frame memory 550, and the left template block data is read from the buffer memory 552. The buffer memory 552 sequentially stores the right template block data read from the current frame image frame memory 550. As the structure of the buffer memory 552, it is possible to use the memory described above with reference to FIG. 47, in which the write path and the read path are separate. Also FIFO
Type of memory may be used.

The buffer memory 552 requires a storage capacity for storing all pixel data of the template block. The current frame image frame memory 550 stores all pixel data of the current frame image. This FIG. 67
In the configuration shown in (1), both the right side template block and the left side template block are updated after the motion vector evaluation operation of 16 columns in the horizontal direction is completed in the processor array.

FIG. 68 shows a structure for updating only one template block data in the processor array. In FIG. 68, the template block data read from the current frame image frame memory 550 is output as the right template block data or the left template block data by the selector 554. The selector 554 transmits the template block data read from the current frame image frame memory 550 to the right template block data path or the left template block data path.

In this case, the element processor PE shown in FIG.
In, only the data stored in one of the right template data register 505a and the left template data register 505b is updated. In response to the switching of the selection mode of the selector 554, the selector 506 shown in FIG. 66.
The selection order of is switched.

FIG. 69 is a diagram showing another example of the configuration of the element processor. The element processor PE shown in FIG. 69 includes two difference absolute value circuits 507a and 507b. The absolute difference circuit 507a calculates the absolute difference between the data stored in the search window data register 505c and the data stored in the right template data register 505a. The absolute difference circuit 507b calculates the absolute difference between the data stored in the search window data register 505c and the data stored in the left template data register 505b.

The outputs of the absolute difference circuits 507a and 507b are transmitted to the summing unit via signal lines 511a and 511b, respectively. In the summing section, the absolute difference circuit 50
Two summing circuits may be provided corresponding to 7a and 507b, respectively. A configuration in which one summing circuit is driven in a time division manner via a selector may be used.

It has been described that template data is also transferred between adjacent element processors in the configuration of the above element processor. If this template block data is not directly transmitted to the motion vector detection unit with fractional accuracy, the template data is directly given to each element processor from the outside without shifting the template block data between adjacent element processors. May be. This is because the template block data is resident in this processor array during the motion vector evaluation operation (shift operation is not required).

70 and 71 are diagrams showing the structures of the summing unit and the comparing unit. In FIG. 70, the summation unit 560 is
The difference absolute value from the difference absolute value circuit included in the element processor PE is received in parallel, and the sum operation is executed. Sum Department 56
The output of 0 is given to the right comparing section 562 and the left comparing section 564. Right comparison unit 562 and left comparison unit 564 are activated in response to activation signals φ1 and φ2, respectively.
The right comparison unit 562 determines the motion vector for the right template block, and the left comparison unit 564 detects the motion vector for the left template block.

The structures of the summing unit 560 and the comparing units 562 and 564 can utilize those shown in the previous embodiment. That is, as the summation unit 560, the configuration shown in FIGS.
For 2 and 564, the configuration shown in FIG. 43 can be used. Activation control signals φ1 and φ2 are applied to control activation of a comparator (see FIG. 43) included in the comparison section and a latch operation of a register latch.

In the structure shown in FIG. 70, the summation unit 56
From 0, the evaluation value for the right template block and the evaluation value for the left template block are output in a time division manner. In this case, in order to surely perform the comparison operation, as shown in FIG. 71, the summation unit 560 and the comparison unit 562.
And 564 may be provided with selector 566 that switches its signal transmission path in response to control signal φC. The selector 566 switches the signal transmission path under the control of the control signal φC according to the evaluation value of the right template block and the evaluation value of the left template block,
The evaluation value output from the summing unit 560 is transmitted to the corresponding right comparing unit 562 or left comparing unit 564.

When the element processor includes two difference absolute value circuits as shown in FIG. 69, summation unit 560 may include two summation circuits. In this case, the summation unit 560 outputs evaluation values for the right side template block and the left side template block in parallel.

FIG. 72 is a diagram showing a structure for detecting a motion vector with fractional accuracy in parallel for two template blocks.

In FIG. 72, a device for detecting a motion vector with a fractional precision includes a motion vector detection with a fractional precision in search window data output from a processor array for detecting a motion vector with an integer precision. Buffers 580 and 582 for storing the search window data required for the search window data, and a fractional precision motion vector for receiving the search window data from the buffer memory 580 and the left side template block data to detect the fractional precision motion vector. An arithmetic unit 584 and a fractional precision motion vector arithmetic unit 586 for receiving the search window data and the right side template block data from the buffer memory 582 and detecting the motion vector with the fractional precision for the right side template block are included.

Buffer memories 580 and 582 execute writing of search window data in response to write control signals φA and φB, respectively. Control signals φA and φB are generated from comparing units 564 and 562 shown in FIGS. 70 and 77, respectively. Buffer memory 5
For 80 and 582, the same structure as that described in the second embodiment is used. Buffer memory 58
0 indicates that the storage data of the left template block is sequentially read when the motion vector is determined with integer precision,
The buffer memory 582 has its stored contents read when the motion vector for the right template block is determined.

The fractional precision motion vector arithmetic units 584 and 586 have the same structure as that described in the second embodiment. The operations of the fractional precision motion vector arithmetic units 584 and 586 are the same as those described in the second embodiment, and the details thereof will not be repeated.

Here, the right-side template block data and the left-side template block data each have a difference in output timing in the cycle period corresponding to 16 horizontal components. When both the right side template block data and the left side template block data are updated every 16 horizontal component cycles, buffer means is provided for each of the left side template block data and the right side template block data, and timing adjustment is executed. At this time, there is a time lag between the motion vector determination periods of the right template block and the left template block. A timing shift similarly occurs for the fractional precision motion vector calculation. In this case, the fractional precision motion vector calculation device can be commonly used for both the right side template block and the left side template block.

FIG. 73 is a diagram showing a modification of the fractional precision motion vector detection configuration shown in FIG. In FIG. 73, a configuration for detecting a motion vector with a fractional precision includes a buffer memory 590 for storing left side template block data and a buffer for storing search window data in response to control signals φA and φB, respectively. Memories 592 and 594, a right side template block data buffer memory 596, a selector 598 for selecting a set of template data and search window data from the read data of the buffer memories 590, 592, 594 and 596, and a selector 5
A second arithmetic unit 599 for detecting a motion vector with a fractional accuracy according to the template data and search window data output from 98 is included.

The selector 598 selects the data stored in the buffer memories 590 and 592 when the motion vector for the left side template block is determined with the fractional precision. When the motion vector is detected with the fractional accuracy for the right template block, the selector 598 selects the read data from the buffer memories 594 and 596. The second arithmetic unit 599 determines a motion vector with a fractional accuracy according to the given template data and search window data.

By using the buffer memories 590, 592, 594 and 596, it is possible to reliably detect the motion vector with the fractional accuracy for the left side template block and the right side template block. At this time, as shown in FIG. 74, in parallel with the motion vector determination operation with integer precision for each of the left template block and the right template block, the motion vector with fractional precision for the right template block and the left template block is pipelined in parallel. Can be detected. With this configuration, it is possible to obtain a more efficient motion vector detection device having a small circuit scale.

Here, the timing of reading data from the buffer memory in the structure shown in FIG. 73 is not strictly described. However, in the same manner as described in the second embodiment in which the motion vector detection is performed with the fractional accuracy described above, the template block data is converted into the template block data according to the motion vector determination signal from the comparison unit of the integer precision arithmetic unit. A configuration may be used in which writing is executed and data is read after writing of all data is completed.

By thus buffering the template block data with the buffer memory as well,
As shown in FIG. 74, a motion vector detection operation with integer precision and a motion vector detection operation with fractional precision can be pipelined and determined at high speed. Here, in FIG. 74, a sequence of motion vector detection with integer precision and motion vector detection with fractional precision for macro blocks # 1 to # 6 is shown as an example.

[Fourth Embodiment] In the storage area coding technique, since the image signal is stored in the storage device, the time axis is not restricted in the image processing. Image signal is CD-RO
This is because it is stored in a storage medium such as M. In the case of such moving image motion compensation for storage media, (i) forward motion compensation for predicting the present from the past, (ii) backward motion compensation for predicting the present from the future, and (iii) both past and future to the present Three types of motion compensation are possible: interpolating motion compensation (interpolation motion compensation) for predicting.

Since one reference frame and the current frame (image frame to be coded) are used in one-way prediction of forward and backward motion compensation (hereinafter, referred to as one-sided prediction), The configurations of the first to third embodiments can be used. Interpolation motion compensation (interpolation motion compensation) requires past and future reference frames and the current frame. In this interpolation motion compensation, these two reference frames are combined in consideration of the time distance between the two reference frames (past reference frame and future reference frame) and the current frame. Using this composite reference frame (or block), the motion-compensated prediction value of the pixel of the current frame is obtained. In order to obtain the motion vector for this combined reference frame (or block), the motion vector obtained by the macroblock of the past reference frame (the motion vector obtained based on the evaluation value calculation by block matching) and the future reference frame It is necessary to find the optimum motion vector from the motion vector found by the macroblock.

[0293] Such processing is, for example, MPEG
(Motion picture image codi
ng expert's group (Motion Picture Image)
Coding Standard for Store
This is performed for B pictures in the Age Media). Hereinafter, although not particularly limited to applications such as B pictures, a configuration for performing motion vector detection by interpolation prediction (interpolation prediction) will be described as a fourth embodiment.

FIG. 75 is a diagram schematically showing the overall structure of the motion vector detecting device according to the fourth embodiment of the present invention. In FIG. 75, the interpolation motion vector predictor detection apparatus includes a first search area data storage unit 1001 for storing pixel data of a first search area, and a template storing pixel data of a template block of the current frame. It includes a data storage unit 1000 and a second search area data storage unit 1002 for storing pixel data in the second search area.

The first and second search area data storage units 1001 and 1002 may be frame memories for storing pixel data of the first and second reference frames, respectively, and the template data storage unit 1000.
May be a frame memory that stores the pixel data of the current frame. One of the first reference frame and the second reference frame is a past frame, and the other is
It is the frame of the future. In a case where the motion compensation is performed by combining a plurality of frames in one direction with respect to the time axis, the first and second reference frames are arranged in the same direction on the time axis with respect to the current frame. May be.

The interpolated motion vector predictor further comprises:
A first one-sided predictive motion for obtaining the first motion vector mva by receiving the template block pixel data from the template data storage unit 1000 and the search area data (search window data) from the first search area data storage unit 1001. Detection unit 1003 and storage unit 1000
A second one-sided predictive motion detection unit 1004 that detects a second motion vector from the template block pixel data from the first search area data storage unit 1002 and the search area data read from the second search area data storage unit 1002.

The first one-sided predictive motion detector 1003 includes the element processors used in the first to third embodiments, and performs block matching processing between given search area data and template block data to perform motion. A first arithmetic processing circuit 1011 for obtaining a vector mva and an evaluation value eva, and a first arithmetic processing circuit 1011.
Includes a first buffer memory 1013 for storing search window block pixel data corresponding to the calculated motion vector from

The buffer memory 1013 has the same structure as that used for the motion vector detection with the detailed accuracy shown in the second embodiment. That is, the first
Of the first arithmetic processing circuit 10
The search window pixel data sequentially shifted out from 11 is stored. The first buffer memory 1013 may have a storage capacity for storing all the pixel data in the search area, or may have a storage capacity for storing one search window block pixel data. Writing and reading of pixel data to and from buffer memory 1013 is executed by using a control system shown in FIG. 46, for example. However, in order to detect a motion vector with integer precision, it is not necessary to use pixels around the search window block.

The second one-sided motion estimation / detection unit 1004 has the same configuration as the first one-sided motion estimation / detection unit 1003.
It includes a second arithmetic processing circuit 1012 and a second buffer memory 1014. The second arithmetic processing circuit 1012 obtains a motion vector mvb and its evaluation value evb by block matching processing from the given search area pixel data and template block pixel data.

The second buffer memory 1014 receives the search window pixel data from the second arithmetic processing circuit 1012 and stores the search window block pixel data corresponding to the motion vector mvb. The second buffer memory 1014 may also store all pixel data in the search area, or may be configured to store and output only the search window block pixel data corresponding to the motion vector mvb.

First and second buffer memories 1013
And 1014 from motion vectors mva and mvb
The search window block pixel data corresponding to is read as the partial reference image data RPa and RPb, and the motion vectors mva and mvb and the evaluation values eva and evb are read.
It is also given to the interpolated predicted motion detection unit 1005.

The first and second arithmetic processing circuits 1011 and 1012 have a processor array, a summation unit and a comparison unit, as in the configurations shown in the first to third embodiments. Evaluation values are calculated and motion vectors are detected in parallel in the same manner as in the embodiment.
First and second buffer memories 1013 and 101
Reference numeral 4 stores the search window pixel data shifted out from the first and second arithmetic processing circuits 1011 and 1012, respectively.

First and second buffer memories 1013
And 1014 are the first and second arithmetic processing circuits 101.
In response to the control signals from the comparators included in 1 and 1012, the search window block pixel data for the displacement vector which is the candidate of the motion vector is stored (when the storage capacity corresponds to the search window block). A signal generated when the comparison unit determines whether or not the displacement vector is updated is used as a data write control signal for the first and second buffer memories 1013 and 1014. Since the data that becomes the first pixel of the search window block is shifted out from the corresponding processing circuit, if the address signal is reset in response to the control signal from this comparison unit, the displacement that is a motion vector candidate will always be generated. Pixel data of a search window block corresponding to a vector can be stored.

At the time of data reading, after the motion vector detection cycle is completed, the data is read from the head address (reset address). This control method is the same as that described with reference to FIGS. 46 to 48 (FIG. 4).
The block 48 shown in 7 may be overlooked as a search window pixel block. No delay stage is needed for the surrounding pixels).

First and second buffer memories 1013
And 1014 store all pixel data in the search area, the value of the motion vector may be used as the start address when reading the data (when the motion vector is represented by the count value of the counter: see FIG. 43). ).
By performing the address jump operation, it is possible to prevent unnecessary reading of the side window pixel data.

First and second one-sided predictive motion detector 10
The operation of each of 03 and 1004 is similar to that described in the first to third embodiments, and detailed operation thereof will not be described. Next, the configuration and operation of the interpolated prediction motion detection unit 1005 will be described. The partial reference image data in the buffer memory is read when the interpolation motion vector is detected. The read partial reference image data is used when generating the reference image for generating the interpolated predicted value.

FIG. 76 is a diagram schematically showing the structure of the interpolative prediction motion detection unit shown in FIG. Referring to FIG. 76, interpolation prediction motion detection section 1005 determines partial reference image data (first motion vector corresponding to motion vectors mva and mvb) read from the first and second buffer memories (see FIG. 75).
And a search window block pixel data in the second search area) to generate a reference image (hereinafter referred to as a synthetic search window block) required for interpolation prediction. 1020, a buffer memory 1021 for storing template block pixel data TP, a block search matching between the synthetic search window block pixel data from the interpolation prediction reference image generation circuit 1020 and the template block pixel data read from the buffer memory 1021. (Calculation of evaluation value indicating degree of correlation between combined search window block and template block) is performed to generate interpolation prediction evaluation value evc, interpolation prediction motion vector detection calculation unit 1022, and interpolation prediction motion vector detection The interpolation prediction evaluation value evc from the arithmetic unit 1022 and the And a motion vector determination circuit 1024 for detecting an optimum motion vector from the first and second evaluation values eva and evb given from the second arithmetic processing circuit.

The buffer memory 1021 stores necessary template pixel data in parallel when the template data from the template data storage unit 1000 shown in FIG. 75 is loaded into the first and second arithmetic processing circuits 1011 and 1012. The reading of data from the buffer memory 1021 is performed by the first and second buffer memories 1013.
And 1014 (see FIG. 75), the data reading is performed in synchronization with the data reading.

The interpolation prediction reference image generation circuit 1020 is
A predetermined calculation is performed on the given pixel data RPa and RPb. This calculation is (RPa + RPb) / 2
It may be an arithmetic mean such as. In addition, (m ・ RPa
A weighted average such as + n · RPb) / (m + n) may be performed. The weights m and n are determined by the time distance between the current frame and each of the first and second reference frames (including the first and second search areas, respectively).
The weight is increased for reference frames with a small time distance. This is because the change from the current claim becomes smaller as the time distance becomes smaller.

Interpolation prediction motion vector detection calculation unit 1022
Is the sum of absolute differences between the synthetic search window pixel data RPc from the interpolation prediction reference image generation circuit 1020 and the template pixel data TP, and the evaluation value ev
produces c. As an alternative to the sum of absolute differences calculation, a calculation such as the sum of squared differences may be used. It may be any calculation as long as it can obtain an evaluation value indicating the degree of correlation of blocks. The synthetic reference image pixel data RPc from the interpolation prediction reference image generation circuit 1020 and the template block pixel data from the buffer memory 1021 are calculated pixel by pixel in the calculation unit 1022.
Is given to and a predetermined calculation is sequentially executed. At the end of this calculation, the evaluation value evc is generated.

The motion vector determination circuit 1024 compares the evaluation value evc from the calculation unit 1022 with the evaluation values eva and evb from the first and second processing circuits (see FIG. 75) to determine the minimum evaluation value. The motion vector corresponding to is determined and output as the motion vector MV for optimum interpolation prediction.

The determination circuit 1024 sequentially outputs the motion vectors mva and mvb in a predetermined order (or in parallel) when the evaluation value evc from the arithmetic unit 1022 is the minimum. The determination circuit 1024 may be configured to also output the evaluation value EV corresponding to the optimum motion vector MV.

With the above-described structure, it is possible to read out the reference frame image and detect the motion vector for interpolation prediction. Therefore, it is not necessary to access the frame memory for storing the reference image, and it is possible to perform interpolation prediction at high speed. The motion vector can be calculated. The partial reference images of the buffer memories 1013 and 1014 may be output together with the detection of the motion vector MV and used for predictive coding.

The pixel data in the first and second search areas are combined (interpolated) by the reference image generation circuit for interpolation prediction 1020, and the combined pixel data and the template block pixel data are combined in the processor array (first or first). 2 has the same configuration as the arithmetic processing circuit 2) to detect the motion vector. First one-sided prediction motion detection unit 100
3 is used for motion vector detection for forward prediction, and the second one-sided prediction motion detection unit 1004 is used for motion vector detection for backward prediction. Motion vector detection for interpolation prediction (bidirectional prediction) can be realized without increasing the device scale. Next, the configuration of each part will be described.

FIG. 77 is a diagram showing the structures of the interpolation prediction reference image generation circuit and the interpolation prediction motion vector detection calculation section shown in FIG. Reference image generation circuit 102 for interpolation prediction
0 is the pixel data P of the partial reference images RPa and RPb.
Averaging circuit 1030 for obtaining the average value of Xa and PXb
including. The averaging circuit 1030 calculates (v · PXa + w
-Execute PXb) / (v + w). v = w may be set, or v and w may be set according to the time distance of each reference image frame with respect to the current frame (template block). Averaging circuit 1030
May be composed of a multiplication circuit (multiplication of coefficients v and w), an addition circuit and a division circuit, and a ROM (data P
Xa and PXb are used as addresses).

The computing unit 1022 obtains the absolute difference value | TPa-PXc | between the composite pixel data PXc from the averaging circuit 1030 and the template block pixel data TPa, and the absolute difference circuit 1031.
Accumulator 1 that accumulates the outputs of 31 to generate the evaluation value evc
Including 032. The same configuration as that described in the first embodiment (see FIG. 26) can be used for the difference absolute value circuit 1031 used in the calculation unit 1022. The accumulator 1032 can use a structure including a normal register and an adder. This operation unit 1022
May be composed of a sum of squared differences circuit.

FIG. 78 shows a structure of motion vector determination unit 1024 shown in FIG. 76. In FIG. 78, the motion vector determination unit 1024 determines that the minimum value min {eva, evb, e of the evaluation values eva, evb, and evc.
vc} minimum value circuit 1035 and minimum value circuit 10
A selection circuit 1036 for selecting one or both of the motion vectors mva and mvb in response to the minimum value information of 35. When the minimum value circuit 1035 selects the evaluation value eva or evb, the selection circuit 1036 selects the corresponding motion vector mva or mvb, and the minimum value circuit 1036.
When 35 selects the evaluation value evc, the motion vector m
Select both va and mvb.

FIG. 79 shows a more detailed structure of the minimum value circuit and the selection circuit shown in FIG. 78. 79. In FIG. 79, the minimum value circuit 1035 has the evaluation values eva and evb.
Registers 1041 and 104 for temporarily storing
2 is compared with the evaluation values eva and evb stored in the registers 1041 and 1042.
43 and the register 10 in response to the output of the comparator 1043.
Evaluation values eva and e stored in 41 and 1042
It includes a selection circuit 1044 for passing one of vb.

Comparator 1043 outputs a signal of a first logic level (eg, "H") when evaluation value eva is larger than evaluation value evb, and a second logic level (eg, "H") otherwise. "L") signal is output. The selection circuit 1044 selects the comparison value evb from the register 1042 when receiving the signal of the first logic level, and the register 104 when receiving the signal of the second logic level.
An evaluation value eva from 1 is selected. Therefore, selection circuit 1044 outputs a smaller evaluation value MIN {eva, evb} of evaluation values eva and evb.

The minimum value circuit 1035 further has an evaluation value ev.
The register 1045 for temporarily storing c (evaluation value for interpolation prediction), the output of the selection circuit 1044, and the register 1
Comparator 1046 for comparing with the evaluation value evc from 045
And a selection circuit 1044 in response to the output of the comparator 1046.
And a selection circuit 1047 for passing one of the evaluation value evc stored in the register 1045.

Comparator 1046 outputs a signal of the first logic level when the output of selection circuit 1044 is larger than evaluation value evc, and outputs a signal of the second logic level otherwise. The selection circuit 1047 receives the signal of the first logic level from the comparator 1046 and then receives the signal from the register 1
The evaluation value evc from 045 is selected, and when the signal of the second logic level is given, the output of the selection circuit 1044 is selected. That is, MIN {ev
c, MIN (eva, evb)} = MIN (eva, e
The minimum evaluation value of vb, evc) is output as the evaluation value EV.

In comparators 1043 and 1046, a configuration may be used in which when the values of both inputs are equal, one of them is selected in accordance with a predetermined priority order.

The selection circuit 1036 uses the motion vector mva.
And a register 1050 for temporarily storing mvb and mvb respectively
And 1051 and the comparator 10 in the minimum value circuit 1035.
43 in response to the output of 43
A selection circuit 1052 for passing one of the stored data,
Select circuit 10 is selectively operated in response to the output of comparator 1046.
Gate circuit 1053 for passing the output of 52 and registers 1050 and 10 in response to the output of comparator 1046.
And a register 1054 for outputting the motion vectors mva and mvb from 51 sequentially or in parallel.

Select circuit 1052 performs the same operation as select circuit 1044, and passes the motion vector corresponding to the selected (smaller) evaluation value. Gate circuit 10
53 is a first value for the comparator 1046 to select the evaluation value eva.
When the signal of the logical level is output, the output becomes a high impedance state, and the signal of the second logical level is output from the comparator 104.
When it is given from 6, the output of the selection circuit 1052 is passed.

The register 1054 operates complementarily to the gate circuit 1053, and outputs the motion vectors mva and mvb from the registers 1050 and 1051 in parallel or in series when a signal of the first logic level is applied,
When the signal of the second logic level is applied, the output becomes in the high impedance state.

FIG. 80 is a diagram showing a modification of the interpolation prediction reference image generating circuit. The reference image generation circuit for interpolation prediction 1022 shown in FIG. 80 has the configuration shown in FIG. 77, and further, averaging for obtaining the average value of the motion vectors mva and mvb given from the first and second arithmetic processing circuits. A circuit 1060 is included. The averaging circuit 1060 has the same configuration as the averaging circuit for obtaining the average value of the pixel data shown in FIG. The motion vector is also weighted according to the reference image for interpolation prediction.

The selection circuit 1036 uses the motion vector mv.
A motion vector corresponding to the minimum evaluation value obtained by the minimum value circuit is selected from a, mvb, and mvc. The configuration of the selection circuit shown in FIG. 80 is the register 1 shown in FIG.
054 is selectively realized by the output of the comparator 1046.

FIG. 81 is a diagram schematically showing the configuration of a modification of the interpolated motion vector predictor detecting apparatus according to the fourth embodiment of the present invention. In FIG. 81, first and second buffer memories 1013 and 1014 shown in FIG. 75 correspond to motion vectors mva and mvb, and first and second search window blocks 1102 and 1104.
Each of the partial reference image data including is stored. The partial reference image blocks 1101 and 1103 are respectively the first and second search window blocks 1102.
And 1104 and its surrounding pixels. First and second
As the configuration for storing such partial reference pixel blocks 1102 and 1104 in the buffer memories 1013 and 1014 of the above, the configuration used for the fraction-precision motion vector calculation in the third embodiment can be used. .

In the interpolation prediction reference image generation circuit, the partial reference images 1103 and 1101 are averaged to generate an interpolation prediction reference image 1105, and the synthesized reference image 1105 is used as a search area in the template block 1107. Find the motion vector. That is, each synthetic search window block 1 in the synthetic reference image 1105.
An evaluation value is calculated by block matching for 106, and a motion vector for this template block 1017 is calculated based on the calculated evaluation value.

In this method, the buffer memory 10
Data may be read pixel by pixel from 13 and 1014 and 1021 to generate a synthetic search window and calculate an evaluation value. There is no need to access the frame memory for interpolation prediction. Therefore, the motion vector can be calculated in parallel with the prediction signal calculation operation by the interpolation prediction, and the high-speed interpolation motion compensation can be performed.

Instead of the configuration shown in FIG. 81, the evaluation value may be calculated by the processing device including the processor array shown in the first to third embodiments. The template block pixel data is stored in the processor array, and the first
And introducing the synthesized (interpolated) pixel data obtained by averaging the pixel data from the second buffer memories 1013 and 1014 into the processor array. When the motion vector and the evaluation value are obtained, the determination unit ev at the time of evaluation
c is the first and second processing devices 1003 and 1004
Are compared with the evaluation values eva and evb from, and the motion vector is determined according to the comparison result.

Further, as shown in FIG. 82, the template block pixel data is processed by the arithmetic processing circuit 1011 or 1012 of the one-sided prediction motion detecting unit 1003 or 1004.
What is shifted out from (the arithmetic processing circuit 1011 in FIG. 82) is as it is, the interpolated prediction motion detection unit 100.
May be given to 5. In the case of this configuration, as shown in FIG. 83, one-sided prediction motion detection and interpolation prediction motion detection can be executed in a pipeline manner.

In FIG. 83, interpolation prediction motion detection (i)
Then, the motion detection of the interpolative prediction is executed in parallel with the unloading (shift out) of the template blocks TP (TP1 and TP2) used for the one-sided motion estimation.
First and second buffer memories 1013 and 101
4 stores necessary search window block pixel data. Therefore, the pipeline operation shown in FIG. 83 can be realized by reading the data from buffer memories 1013 and 1014 in synchronization with the shift-out of the template block pixel data from this processing circuit.

With this configuration, the interpolated prediction motion detection unit 100
The buffer memory provided in 5 functions as a buffer for timing adjustment.

In the interpolation motion detection (ii) shown in FIG. 83, the interpolation prediction motion detection is executed in parallel with the processing of the template block in the one-sided prediction motion detection. The template block data is stored in the buffer memory and the process is executed. At the time of unloading the template block TP, the template block pixel data that has been unloaded (shifted out) from the one-sided prediction motion detection unit 1003 is loaded into the buffer memory of the interpolation prediction motion detection unit. After the loading is completed, the interpolation prediction motion detection process is performed. Even when the partial reference image for interpolation prediction includes peripheral pixels of the search window block, the processing can be executed at high speed.

FIG. 84 is a diagram schematically showing the overall structure of an apparatus using the motion vector obtained in the fourth embodiment of the present invention. FIG. 84 shows the configuration of a source encoding circuit used for encoding a moving image. 84, the source encoding circuit has a subtracter 1110 and an orthogonal transformer (DCT) 1 as in the configuration shown in FIG.
111, a quantizer 1112, an inverse quantizer 1113, an inverse orthogonal transformer (IDCT) 1114 and an adder 1115. The functions of these components are similar to those shown in FIG.

The source encoding circuit further includes an adder 111.
Frame memory 1116 that receives and stores the output of FIG. 5 via the switch SW3, frame memory 1117 that receives and stores the data stored in the frame memory 1116, and reverse motion compensation that uses the data stored in the frame memory 1116 Directional motion compensation circuit 1118, forward motion compensation circuit 1120 that performs forward motion compensation using the data stored in frame memory 1117, and interpolation that performs interpolation predictive motion compensation using the data stored in frame memories 1116 and 1117. A motion compensation circuit 1119 is included.

The forward motion compensation circuit 1118 uses the future frame stored in the frame memory 1116 as a reference image to perform block matching processing on the current frame to calculate a motion vector mva and a prediction signal for the current frame image. To generate.

The forward motion compensation circuit 1120 uses the past frame stored in the frame memory 1117 as a reference frame to generate a motion vector mvb for the current frame image and a prediction signal for this current frame.

The interpolation motion compensation circuit 1119 synthesizes the image data read from the frame memories 1116 and 1117 to generate a reference frame image and performs a block matching process to perform a motion vector MV for the current frame.
And a prediction signal for this current claim image.

In this embodiment, the one-side predictive motion detecting section is shared by the compensation circuits 1118 to 1120. Compensation circuits 1118-1120 are shown separately to clarify the functional configuration.

The outputs of the motion compensation circuits 1118 to 1120 are given to the subtractor 1110 via the switch SW4. The subtractor 1110 also includes a pixel rearrangement circuit 1124.
Receive the output of. One of the output of the subtractor 1110 and the output of the pixel rearrangement circuit 1124 is given to the orthogonal unit 1111 selected by the switch SW1. The output of the switch SW4 is also given to the adder 1115 via SW2. The control circuit 1 selects the terminals of the switches SW1 to SW4.
122. This allows backward motion compensation,
The error signal for the prediction signal generated in accordance with the forward motion compensation and the interpolation motion compensation can generate the reference image data for the new frame.

The pixel rearrangement circuit 1124 is provided because the order of frames to be processed for performing bi-prediction, that is, interpolation prediction needs to be different from the frame order of the current image (see MPEG standard). ).

In the configuration of the apparatus as shown in the figure, an image is an I picture for which intra-frame interpolation is performed, a P picture for which one-way prediction (inter-frame prediction) coding is performed, and interpolation prediction. Included B-pictures. In the encoding process, the I picture and the B picture after the B picture in the current frame sequence are processed, and then the B picture is processed using the past and future I and P pictures. This processing sequence is applied to the pixel rearrangement circuit 112.
This is achieved by rearranging the frames according to 4. Switch SW
1 to SW4 select the signal path according to the image to be processed. The output 1000 of the pixel rearrangement circuit 1124 of the switch SW1 is selected at the time of processing an I picture, and at this time, the switches SW2 and SW3 are in an open state.

In contrast to the source coding circuit shown in FIG. 84, the configuration of the fourth embodiment of the present invention is the motion vectors mva, m.
vb and MV can be generated by sharing the processor array (arithmetic processing circuit). That is, the interpolated prediction motion compensation circuit 1119 has the frame memories 1116 and 1
Reverse motion compensation circuit 11 without accessing 117
Interpolation motion compensation can be performed by directly receiving the partial reference image data from 18 and the forward motion compensation circuit 1120. As a result, not only the apparatus size can be reduced, but also the number of accesses to the frame memories 1116 and 1117 at the time of motion vector detection for interpolation prediction can be reduced, and high-speed image processing can be performed. Further, since the search window block (partial reference image) is generated in parallel with the detected motion vector, it is not necessary to access the frame memory newly for generating the prediction signal. Can be used as a prediction signal.

FIG. 85 is a diagram showing still another modification of the fourth embodiment of the present invention. In FIG. 85, the motion vector detection device is configured such that the first one-sided prediction motion detection unit 1150,
A second one-sided prediction motion detection unit 1160 and an interpolation prediction motion detection unit 1170 are included.

The first one-sided motion detector 1150 receives the first search window pixel data and the template block pixel data, and calculates a motion vector with integer precision and a corresponding evaluation value by block matching processing. Integer precision motion detection unit 1151, a first buffer memory 1152 for storing search window data Sa from the first integer precision motion detection unit 1151, and a motion vector mvai and evaluation value evai given from the motion detection unit 1151. And template block data TPa
Motion vector mva with fractional accuracy (detailed accuracy)
And the first detailed precision motion detection unit 115 for obtaining the evaluation value
Including 3.

The first memory 1152 stores the pixel data of the area including the search window block corresponding to the integer-precision motion vector mvai and its peripheral pixels. The first detailed precision motion detection unit 1153 uses the template block data TPa and the pixel data in the first buffer memory 1152 to generate a motion vector mva with detailed precision and the corresponding evaluation value eva. The configuration and operation of the first one-sided predictive motion detection unit 1150 are the same as the configuration and operation of the second embodiment described above with reference to FIGS. 44 to 57.

The second one-sided predictive motion detection section 1160 has the same configuration as the first one-sided predictive motion detection section 1150,
A second integer precision motion detection unit 1161 that receives the second search window data and the template data, a second buffer memory 1162 that stores the search window data Sb from this detection unit 1161, and a detection unit 1161.
It includes a second detailed precision motion detection unit 1163 which receives the template block data TPb from the second buffer memory 1162 and the search window data from the second buffer memory 1162 to obtain the motion vector mvb with the detailed precision and the corresponding evaluation value mvb. The operation of the second one-side predictive motion detection unit 1160 is also the same as that of the second embodiment described above.

The interpolation predictive motion detection unit 1170 uses the detailed precision motion vectors mva and mvb from the first and second one-sided motions 1150 and 1160, and the evaluation value eva.
And evb and the partial reference image data RPa and RPb, the optimum motion vector MV for the template block is detected. At this time, the corresponding evaluation value E
V may be output together with the motion vector MV. The block-level configuration of the interpolated motion prediction detector 1170 is the same as that described above with reference to FIG. However, since the motion vector is detected with detailed accuracy, the operation of its constituent elements is different. The operation for detecting the interpolated motion vector predictor with the detailed accuracy will be briefly described below with reference to FIG.

The interpolation prediction reference image generation circuit 1020 generates interpolation reference image data RPc from the partial reference image data RPa and RPb. This operation is similar to that at integer precision. The interpolation prediction motion vector detection calculation unit 1022 obtains the motion vector mvc and the corresponding evaluation value evc with high precision from the template block pixel data from the buffer memory 1021 and the interpolation reference image data from the circuit 1020. In order to perform the detection with this detailed accuracy, the detection calculation unit 1022 is provided with, for example, FIG.
3 is provided.

The motion vector determination circuit 1024 finds the smallest one of the evaluation values eva, evb and evc,
The motion vector corresponding to the smallest evaluation value is selected and output. The target evaluation value EV may be output together.

Buffer memories 1152 and 116 used for one-sided motion vector predictor detection with detailed accuracy
2 can also be used for interpolative motion estimation,
It is possible to perform interpolation prediction motion detection at high speed and with high precision, without increasing the number of accesses to the frame memory and the device scale.

Note that the template block data is stored in the one-sided predictive motion detection unit 11 as in the case of integer-precision interpolation motion detection.
It may be directly given to the detection unit 1170 from 50 or 1160. In this case, motion vector detection with integer precision,
It is possible to execute the motion vector detection and the interpolated prediction motion vector detection with a fine precision in a pipeline manner.

For the structure for the interpolative prediction motion detection with the detailed accuracy, the structure described in the interpolative predictive motion detection with the integer accuracy can be used.

[0356]

As described above, according to the present invention, the element processors are arranged in a two-dimensional array and the template block data is made resident in this processor array so that the evaluation values required for motion vector detection can be obtained. Since the calculation is performed, the motion vector can be detected with a small circuit scale and low power consumption.

Also, the element processors are arranged in an array,
Since the search window data and the template block data are shifted in one direction in this array, the data required for motion vector detection with fractional precision was used for this integer precision motion vector detection. The data can be used as it is, and the motion vector can be detected at high speed with fractional accuracy.

That is, according to the invention of claim 1,
A circuit required for data transfer because the element processors capable of storing the search window data and the template data are arranged in a two-dimensional array and the data is transferred only in one direction in the two-dimensional array. It is possible to obtain a motion vector detection device having a small scale and a small occupation area which operates with low power consumption.

According to the invention of claim 2, the search window data and the template block data used for motion vector detection with integer precision are used as they are for motion vector detection operation with fractional precision without passing through the frame memory. Therefore, the number of accesses to the frame memory is reduced, and the motion vector can be detected at high speed with fractional accuracy.

According to the third aspect of the present invention, the element processor can store a plurality of search window data and / or a plurality of template block data, so that the area occupied by the processor array can be reduced and the small occupied area can be obtained. The motion vector detection device of is obtained. Further, since the number of element processors is reduced, the number of constituent elements of the arithmetic circuit system required for calculating the evaluation value such as the absolute difference value can be reduced accordingly, and the motion vector detecting device with low power consumption can be reduced. can get.

According to the invention of claim 4, since the operation means for calculating the evaluation value of the motion vector is output by the combination of the sign bit and the size bit, the negative number in the two's complement display is represented. An incrementer for expressing is unnecessary, and an element processor with a small occupied area can be obtained. In addition, the power consumption required for the incrementer can be reduced accordingly.

According to the invention of claim 5, the summing circuit for generating the evaluation value is formed by a full adder circuit arranged in a tree shape, and the sign bit is given to the least significant bit of the full adder circuit stage. Therefore, it is possible to obtain a summing circuit that operates at a high speed with a small occupied area, and accordingly it is possible to detect a motion vector at a high speed.

According to the invention of claim 6, since the pixel data of the search window is stored in the processor array and the template block data is made resident in the processor array, the area occupied is small and the power consumption is low. An operating motion vector detection device can be obtained.

According to the invention of claim 7, since the search window data is transferred along the one direction in this processor array, the data which becomes unnecessary when the evaluation value is generated is shifted out from the processor array and The required search window data can be shifted into the processor array, the search window data can be efficiently stored in the processor array, and the small occupied area that operates at high speed and low power consumption It is possible to obtain the motion vector detecting device.

According to the eighth aspect of the present invention, the template block data transfer direction and the search window data transfer direction are orthogonal to each other in the processor array.
Since the template block data is arranged according to the raster scan in the frame memory, the data can be stored as it is in the processor array according to the storage mode of the template block data, and the template data can be loaded into the processor array at high speed. You can

According to the ninth aspect of the present invention, the transfer directions of the search window data and the template block data are parallel in the processor array. As a result, the wiring occupying area required for transmitting both data can be reduced, and a processor array having a small occupying area can be realized.

According to the tenth aspect of the invention, since the calculation is performed at a speed N times the transfer speed of the search window data, it is possible to efficiently generate the motion vector evaluation value.

According to the eleventh aspect of the invention, the template block data required for generating the evaluation value can be sub-sampled, and the motion vector can be accurately detected even for the image data of the high frame rate. It will be possible. At this time, the number of required element processors is also reduced accordingly, and the area occupied by the processor array can be reduced.

According to the invention of claim 12, two template block data are stored in each element processor, and evaluation values for two template blocks are generated using the same search window block data. There is. As a result, the frame memory can be efficiently accessed to read the search window data, and the motion vector can be detected at high speed.

According to the thirteenth aspect of the present invention, the motion vector is evaluated simultaneously for the two template blocks, and the number of accesses to the frame memory for reading the search window data is greatly reduced. It is possible to detect the motion vector efficiently and at high speed.

According to the fourteenth aspect of the present invention, the synthetic reference image data (interpolation reference image data) is generated by using the partial reference image data used by the one-sided prediction motion detection unit, and interpolation prediction motion detection is performed. Since this is performed, the number of accesses to the frame memory can be significantly reduced, and the interpolation prediction motion detection can be performed at high speed. According to the fifteenth aspect of the present invention, the synthetic reference image data is generated by using the partial reference image data stored in the buffer memory means used for the one-sided motion prediction of the detailed precision, and the detailed reference image data is generated. Since interpolative prediction detection is performed, there is no need to provide a new buffer memory to detect interpolative prediction with detailed accuracy, and it is possible to detect interpolative predictive motion with high accuracy at high speed without increasing the device size. Can be done.

According to the sixteenth aspect of the present invention, since all the necessary data are transferred from the one-sided predictive motion detecting means to the interpolative predictive motion detecting means, the processing at the time of this motion detection should be executed in a pipeline manner. It is possible to perform high speed processing.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a motion vector detection device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a search area and a search range of a template block used by the motion vector detection device in FIG.

FIG. 3 is a diagram showing a configuration of an element processor included in the processor array shown in FIG.

FIG. 4 is a diagram showing an overall configuration of the processor array shown in FIG.

5 is a diagram showing a modification of the processor array shown in FIG.

6 is a diagram showing a positional relationship of stored data in the processor array shown in FIG.

7 is a diagram showing a distribution of stored data in the processor array shown in FIG.

8 is a diagram showing a distribution of stored data in a linear processor array of one column in the processor array shown in FIG.

FIG. 9 is a diagram for explaining the operation of the motion vector detection device shown in FIG. 1.

FIG. 10 is a diagram showing movement and distribution of data in the processor array after completion of generation of one evaluation value.

11 is a diagram showing a relationship between stored data and displacement vectors in the processor array shown in FIG. 4 and a distribution of stored data at that time.

FIG. 12 is a diagram showing a positional relationship between a template block and a search window block and a distribution of stored data in a processor array at the time of completion of generation of an evaluation value for one search window.

FIG. 13 is a diagram showing a positional relationship between the template block and the search window at the time of loading the next search window data in the embodiment of the present invention.

14 is a diagram showing a positional relationship between a search window block and a template block when an evaluation value is generated using the search window shown in FIG.

FIG. 15 is a diagram showing a positional relationship between a search window block and a template block when the motion vector evaluation operation is completed.

16 is a diagram showing a distribution of stored data in the processor array at the time of the positional relationship between the search window block and the template block shown in FIG.

FIG. 17 is a diagram showing the arrangement of element processors in a processor array.

FIG. 18 is a diagram showing an arrangement of template data stored in the element processor shown in FIG. 17.

19 is a diagram showing an arrangement of pixel data in a search area with respect to the template block shown in FIG.

20 is a diagram showing a displacement vector change range (motion vector search range) in the search area shown in FIG. 19;

FIG. 21 is a diagram showing a distribution of search window pixel data in the processor array example in the starting state.

FIG. 22 is a diagram showing a change in the distribution of search window pixel data with the progress of processing in the processor array.

FIG. 23 is a diagram showing a change in the distribution of search window pixel data with the progress of processing in the processor array.

FIG. 24 is a diagram showing a scan direction of search window data in a search area.

25 is a diagram showing an example of a specific configuration of the element processor shown in FIG.

FIG. 26 is a diagram showing a specific configuration example of the differential absolute value circuit shown in FIG. 25.

FIG. 27 is a signal waveform diagram representing an operation when the element processor shown in FIG. 25 is generalized.

FIG. 28 is a diagram for explaining the operation of the element processor shown in FIG. 25.

29 is a signal waveform diagram representing another operation mode of the element processor shown in FIG.

30 is a diagram showing a distribution of pixel data giving an effective calculation result at the time of operation in the operation waveform diagram shown in FIG. 29.

31 is a diagram showing a specific configuration example of an element processor for realizing the operation shown in FIG. 30. FIG.

FIG. 32 is a diagram showing an example of a configuration of a data register used in the element processor.

FIG. 33 is a diagram showing still another configuration example of the element processor.

FIG. 34 is a diagram showing still another configuration example of the element processor.

FIG. 35 is a diagram showing another configuration example of the data register.

36 is a diagram showing a structure of a data register having the unit structure shown in FIG. 35. FIG.

37 is a diagram showing the structure of the data buffer shown in FIG. 4. FIG.

FIG. 38 is a diagram showing another configuration example of the difference absolute value circuit used in the element processor according to the present invention.

39 is a diagram showing a configuration of a summing unit when the absolute difference circuit shown in FIG. 38 is used.

FIG. 40 is a diagram showing a specific configuration example of the summing unit shown in FIG. 39.

41 is a diagram showing a configuration of the 4 to 2 compressor shown in FIG. 40. FIG.

42 is a diagram showing a specific configuration example of the summation unit shown in FIG. 40.

43 is a diagram illustrating a specific configuration example of a comparison unit illustrated in FIG.

FIG. 44 is a diagram showing a conceptual configuration of a motion vector detection device according to a second embodiment of the present invention.

FIG. 45 is a diagram showing a specific configuration example of the motion vector detection device shown in FIG. 44.

FIG. 46 is a diagram showing a specific configuration example of the buffer memory circuit shown in FIG. 45.

47 is a diagram showing a distribution of stored data in the buffer memory shown in FIG. 46.

48 is a diagram showing an operation of the buffer memory circuit shown in FIG. 46. FIG.

FIG. 49 is a diagram showing a specific configuration example of the second arithmetic unit shown in FIG. 44.

50 is a diagram showing a specific configuration example of the fractional accuracy predicted image generation circuit shown in FIG. 49.

51 is a diagram showing the configuration of the difference absolute value sum circuit shown in FIG. 49. FIG.

FIG. 52 is a diagram for explaining the operation of the second arithmetic device.

53 is a diagram showing a specific configuration example of the second arithmetic unit shown in FIG. 45.

FIG. 54 is a diagram showing a modified example of the motion vector detection device shown in FIG. 45.

55 is a diagram showing an operation of the motion vector detection device shown in FIG. 54.

FIG. 56 is a diagram showing still another configuration example of the motion vector detection device shown in FIG. 44.

FIG. 57 is a diagram showing a modification of the motion vector detecting device shown in FIG. 56.

FIG. 58 is a diagram showing a search area, template blocks, and a search range used in the third embodiment.

FIG. 59 is a diagram showing an arrangement of template blocks used in the third embodiment.

FIG. 60 is a diagram for explaining the operation of the third embodiment of the present invention.

FIG. 61 is a diagram for explaining the operation of the motion vector detecting device according to the third embodiment of the present invention.

FIG. 62 is a diagram showing an operation of the motion vector detection device according to the third embodiment of the present invention.

FIG. 63 is a diagram showing an operation of the motion vector detection device according to the third embodiment of the present invention.

FIG. 64 is a diagram showing an operation of the motion vector detection device according to the third embodiment of the present invention.

FIG. 65 is a diagram showing timing of motion vector generation in the motion vector detecting device according to the third embodiment of the present invention.

FIG. 66 is a diagram showing the structure of an element processor used in the third embodiment of the present invention.

67 is a diagram showing a configuration for generating data of two template blocks for the element processor shown in FIG. 66. FIG.

68 is a diagram showing another configuration for generating data of two template blocks for the element processor shown in FIG. 66. FIG.

69 is a diagram showing another configuration example of the element processor shown in FIG. 66. FIG.

[Fig. 70] Fig. 70 is a diagram illustrating a configuration example of a comparison unit in the motion vector detection device according to the third embodiment of the present invention.

[Fig. 71] Fig. 71 is a diagram illustrating a configuration example of a comparison unit in the motion vector detection device according to the third embodiment of the present invention.

FIG. 72 is a diagram showing a device configuration when a third embodiment of the present invention is combined with a fractional precision motion vector detection device.

[Fig. 73] Fig. 73 is a diagram illustrating another configuration example when the motion vector detection device according to the third embodiment of the present invention is combined with a fractional precision motion vector detection device.

FIG. 74 is a diagram showing an operation of the configuration of FIG. 73.

FIG. 75 is a diagram showing an overall configuration of a motion vector detection device which is a fourth embodiment of the present invention.

[Fig. 76] Fig. 76 is a diagram illustrating the configuration of the interpolated prediction motion detection unit illustrated in Fig. 75.

77 is a diagram showing the configurations of an interpolation prediction reference image generation circuit and an interpolation prediction motion vector detection calculation section shown in FIG. 76.

78 is a diagram showing a specific configuration of the motion vector determination circuit shown in FIG. 76. FIG.

79 is a diagram showing a detailed structure of the circuit shown in FIG. 78. FIG.

80 is a diagram showing a modification of the interpolation prediction reference image generation circuit shown in FIG. 76. FIG.

[Fig. 81] Fig. 81 is a diagram illustrating another configuration example of the interpolated prediction motion detection unit.

FIG. 82 is a diagram showing the configuration of a modification of the motion vector detection device according to the fourth embodiment of the present invention.

FIG. 83 is a diagram showing a data processing mode in the motion vector detection device according to the fourth embodiment of the present invention.

FIG. 84 is a diagram showing an example of application of the motion vector detection device according to the fourth embodiment of the present invention.

FIG. 85 is a diagram showing another configuration of the motion vector detection device according to the fourth embodiment of the present invention.

[Fig. 86] Fig. 86 is a diagram illustrating an overall configuration of a conventional image signal encoding circuit.

87 is a diagram showing the structure of the source encoding circuit shown in FIG. 86. FIG.

[Fig. 88] Fig. 88 is a diagram for describing an operation of image motion compensation.

[Fig. 89] Fig. 89 is a diagram illustrating an arrangement example of search areas and template blocks and a relationship between motion vectors when performing motion compensation by the block matching method.

FIG. 90 is a diagram showing an overall configuration of a conventional motion vector detection device.

91 is a diagram showing a configuration of an element processor included in the processor array shown in FIG. 90. FIG.

92 is a diagram showing a method of scanning a template block and a scan of a search window in the motion vector detecting device shown in FIG. 90.

FIG. 93 is a diagram showing an operation of the motion vector detection device shown in FIG. 90.

FIG. 94 is a diagram for explaining the operation of the conventional motion vector detection device.

[Fig. 95] Fig. 95 is a diagram illustrating another configuration example of the conventional motion vector detection device.

FIG. 96 is a diagram for explaining a method for generating a motion vector with a fractional precision.

FIG. 97 is a diagram for explaining a motion vector with a fractional accuracy.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Calculation part 2 Input part 3 Comparison part 10 Processor array 12 Summing part 25-1 to 25-M Data register 26-1 to 26-N Data register 35 Reference frame image 36 Current frame image 40 Search window 42 Search window block 52 Side Window Block 43 Template Block 64 Difference Absolute Value Circuit 70 Subtractor 72 ExOR Circuit 73 N Word Register File 75 M Word Register File DL Data Buffer 102 4 to 2 Compressor 104 Full Adder 110a to 110h Full Adder Circuit 130 Register Latch 132 Comparator 134 Counter 136 Register Latch 150 Frame Memory 154 Frame Memory 156 Controller 200 Motion Vector Detection Device 210 First Arithmetic Unit 250 Second Arithmetic Device 270 Buffer memory circuit 280 Buffer memory 282 Buffer memory 302 Fractional accuracy prediction image generation circuit 304 Difference absolute value sum circuit 306 Comparison unit 400 Processor array 417 Summation unit 418 Comparison unit 411a to 411w Element arithmetic unit 413a to 413w Registers 412a to 412w Difference Absolute value circuit 414a to 414w register 401 frame memory 402 frame memory 432a shift register 432b shift register 430a latch 430b latch 505a right template block data storage register 505b left template block data storage register 505c search window data storage register 506 selector 507 Difference absolute value circuit 560 Summing unit 562 Right comparing unit 564 Left comparing unit 580 bar Buffer memory 582 Buffer memory 584 Fractional precision motion vector computing device 586 Fractional precision motion vector computing device 590 Buffer memory 592 Buffer memory 594 Buffer memory 596 Buffer memory 598 Selector 599 Second computing device 1000 Template data storage unit 1001 First search area data Storage unit 1002 Second search area data storage unit 1003 First one-sided prediction motion detection unit 1004 Second one-sided prediction motion detection unit 1005 Interpolation prediction motion detection unit 1011 First arithmetic processing circuit 1012 Second arithmetic processing circuit 1013 First buffer memory 1014 Second buffer memory 1020 Interpolation prediction reference image generation circuit 1021 Buffer memory 1022 Interpolation prediction motion vector detection calculation unit 1024 Motion vector judgment Constant circuit

Claims (16)

[Claims] 1. An apparatus for obtaining a motion vector used in motion compensation predictive code processing by block matching processing between a reference frame image and a current frame image, each of which is data substantially along one direction. A plurality of processor means including a means for transferring the first frame in the reference frame image, and the processor means for storing the pixel data of the first block of the current frame image, A second storage means for storing pixel data of a second block related to the second block, and a calculation means for performing a predetermined calculation process on the data stored in the first and second storage means, Evaluation for generating an evaluation value indicating the degree of correlation between the image of the first block and the image of the second block in response to the output of each of the arithmetic means of the plurality of processor means. Comprises a value generating means, and determining means for determining a motion vector for the first block in accordance with the evaluation value from the evaluation value generation means, the motion vector detecting device. 2. The determining means determines a motion vector with integer precision, receives the reference frame image data and the current frame image data, and moves the first block with fractional precision finer than the integer precision. It further comprises arithmetic processing means for calculating a vector, and means for directly giving at least one of the reference frame image data and the current frame image data stored in the plurality of processor means to the arithmetic processing means as data to be processed. The motion vector detecting device according to claim 1. 3. In each of the processor means, the first storage means corresponds to pixels different from each other.
Storage means for storing a number of data, and the second storage means includes a storage means for storing a number N of data corresponding to different pixels, where M and N are positive integers. The motion vector detecting device according to claim 1, wherein N is larger than M. 4. The calculation means performs subtraction between the pixel data of the first block and the pixel data of the second block, and the subtraction result is a code bit indicating a sign and a size bit indicating a size. And a gate means for performing module 2 addition of each magnitude bit of the subtraction means and the sign bit and outputting a difference absolute value of the subtraction result. The output of is given by the set of the sign bit and the absolute difference value,
The motion vector detection device according to claim 1. 5. The evaluation value generation means includes a summation circuit for calculating a summation of outputs of the calculation means, and the summation circuit includes a plurality of stages arranged in a tree shape in which all outputs are transmitted to the next stage. 5. The motion vector detection device according to claim 4, further comprising an adder circuit, wherein the sign bit is applied to a carry input of a full adder circuit of the least significant bit of each of the full adder circuit stages. 6. A motion vector detecting device for obtaining a motion vector of a template block composed of pixels of Q rows and P columns of a current frame image by block matching processing with respect to a search area of a predetermined size of a reference frame image, wherein The region includes a search window having the same width as the template block, and includes linear arrays arranged in P columns, each of the linear arrays including Q / M cascaded element processors. Each of the first storage means stores M different data of the template,
Second storage means for storing N different data in the search window, and operation means for performing a predetermined operation on the storage data of the first storage means and the storage data of the second storage means. And M and N are integers, and N is an integer multiple of M, and are provided corresponding to each of the linear arrays and store R different data in the search area. A motion vector detection device, comprising: a third storage means, wherein the sum of the R and the Q is equal to the number of pixels arranged in one column in the search area. 7. Each of the linear arrays corresponds to each column of the template block, data of the search area is transmitted along one direction via the second storage means, and linear data of adjacent columns is transmitted. 7. A motion vector detection device according to claim 6, which is transmitted to the array via its corresponding third storage means. 8. The motion vector detecting device according to claim 6, wherein a direction in which the template block data is transmitted and a direction in which the search window data is transmitted are substantially orthogonal to each other. 9. The template block data is transferred along the same direction as the search window data,
7. The motion vector detection device according to claim 6, wherein the template data is transmitted only between element processors by bypassing the third storage means corresponding to the linear array. 10. The motion vector detection device according to claim 6, wherein in each of the element processors, the calculation means executes the predetermined calculation at a calculation speed that is N times the transfer speed of the search window data. 11. The motion vector detection device according to claim 6, wherein the calculation means executes the predetermined calculation at a speed M times as high as a transfer speed of the search window data. 12. The first storage means includes first storage means for storing pixel data of a first template block and second storage means for storing pixel data of a second template block. 7. The motion vector detecting device according to claim 6, wherein the arithmetic means executes the predetermined arithmetic operation on the stored data of the second storage means and the stored data of the first and second storage means. 13. An apparatus for obtaining a motion vector used in motion compensation predictive coding processing by block matching processing between a reference frame image and a current frame image, the first vector having a predetermined size in the current frame image. Storage means for storing the data of the template block of the first frame, second storage means for storing the data of the second template block of the predetermined size in the current frame image, the first and second in the reference frame image Storage means for storing the data of the search window block associated with both template blocks, the storage data of the first storage means, the storage data of the second storage means and the storage of the third storage means. By executing a predetermined operation for each of the data and Evaluation value generating means for deriving an evaluation value indicating the correlation degree between the rate block and the search window block and the correlation degree between the second template block and the search window block, and the output of the evaluation value generating means. And means for performing motion vector detection on the first and second template blocks in a parallel fashion in response to the motion vector detection apparatus. 14. A motion vector detection device for obtaining a motion vector used in motion compensation predictive code processing by block matching processing between a reference frame image and a current frame image, each of which is within the current frame image. Motion vectors for the template block image according to the template block image to be encoded and partial reference images in different reference frame images related to the template block image are detected according to a block matching evaluation value. An interpolating partial reference image is generated by an interpolating process of the detecting means and the partial reference image data used by the plurality of one-sided prediction motion detecting means,
An interpolation prediction motion detection unit that calculates a motion vector according to a block matching evaluation value for the template block image by block matching processing between the generated interpolation partial reference image and the template block image; and the one-sided prediction motion detection unit. A motion vector detecting device comprising: an output determining unit that determines and outputs a final motion vector of the template block image according to the calculated evaluation function value and the evaluation value calculated by the interpolation predicted motion detecting unit. 15. Each of the one-sided predictive motion detection means,
Integer precision motion vector detection means for detecting a motion vector with integer precision, buffer memory means for receiving and storing corresponding partial reference image data from the integer precision motion vector detection means, and partial reference image from the buffer memory means A fractional precision motion vector detecting means for detecting a motion vector with a fractional precision according to the data and the template block image data, and the interpolation predicted motion detecting means is provided corresponding to each of the one-sided predicted motion detecting means. 15. The motion vector detecting device according to claim 14, wherein the partial reference image data is input from a buffer memory means. 16. A transfer means for transferring the evaluation value, the motion vector, and the partial reference image data calculated by the one-sided prediction motion detection means from each one-sided prediction detection means to the interpolation prediction motion detection means, The motion vector detecting device according to claim 14.