JPH06113264A - Television signal decoder - Google Patents

Abstract

PURPOSE:To provide the decoder obtaining a signal compatible with a high definition television receiver, an existing television receiver and an existing VTR with an inexpensive means. CONSTITUTION:A MUSE signal of the 1125 system in the MUSE-NTSC conversion mode is subject to de-emphasis processing 703 and field interpolation processing 705 and converted into a signal of the 525 system by a scanning line conversion section 706 and converted into an NTSC signal compatible with an existing system at an NTSC encoder 709. In the simple MUSE processing mode, the MUSE signal is subject to interframe interpolation processing 606 and vertical direction band limit 609 and the result is inputted to a mixer circuit 610, in which an output of the field interpolation circuit 705 and an output of the inter-frame interpolation circuit are mixed by a motion detection signal and the result is outputted to a TCI decode circuit 611. The signal subject to TCI decoding therein is given to a D/A converter 612, in which the signal is converted into an analog signal and the signal is led out as a high definition television signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal decoding device for decoding a television signal which is band-compressed and transmitted.

[0002]

2. Description of the Related Art At present, a new high-definition television system, which is a new television system, is being developed with the aim of improving the definition of images. As a high-definition television system, the MUSE (MULTIPLE SUB-NYQUIST SAMPLINGE) has a signal band that is about five times that of conventional television signals and can be transmitted in the signal band for one channel of broadcasting satellite.
A band compression method called NCODING) has been developed. In the MUSE system, band compression is performed by offset subsampling a high-definition television signal between fields and frames. Therefore, the receiving side needs a MUSE decoder equipped with a large capacity memory such as a frame memory.

FIG. 5 is a structural example of a MUSE decoder. The MUSE signal is supplied to the terminal 501. This signal is digitized by the A / D converter 502 with a clock having a sampling frequency of 16.2 MHz. A / D
The output signal of the converter 502 is supplied to the frame memory 504, the motion detection circuit 503, the selector 507, the field interpolation filter 505, and the synchronous reproduction / control signal decoding circuit 506 (hereinafter referred to as the decoding circuit 506).

The decoding circuit 506 reproduces the sync signal from the MUSE signal and decodes and outputs the control signal multiplexed and transmitted during the blanking period from the image signal. The control signal includes an interframe offset subsampling phase (hereinafter referred to as FrOSS) and an interfield offset subsampling phase (hereinafter referred to as FiOSS) that are indispensable for decoding the MUSE signal.
Signals etc. are included.

The MUSE decoder performs a process suitable for each of the moving part and the still image part of the image. The processing of the still image portion will be described below. Selector 50
7, the output MUSE signal of the A / D converter 502 and the signal delayed by one frame period in the frame memory 504 are switched according to the FrOSS signal obtained from the decoding circuit 506, and the signal of 32.4 MHz rate is output. Is output as. This is called interframe interpolation.

The inter-frame interpolated output signal is input to the sampling frequency conversion section 510 via an LPF (low pass filter) 508 having a cutoff frequency of 12 MHz,
Here, the sampling rate is from 32.4 MHz to 48.
Converted to 6MHz. Here, the total frequency characteristic of the LPF 508 and the sampling frequency conversion unit 510 is MUSE.
It is specified by impulse response in the transmission standard.

This standard is shown in FIG. The inter-frame interpolation output signal defined by this characteristic is input to the sub-sampling circuit 511, and the FiO from the decoding circuit 506 is output.
It is subsampled according to the SS signal, and this output (24.
3 MHz) is supplied to the field memory 512, the 1H delay memory (H: horizontal period) 513, and the adder 515. The adder 515 calculates the average value of the output signal of the 1H delay memory 513 and the output signal of the sub-sampling circuit 511, and supplies it to the selector 516. The selector 516 outputs the output signal from the adder 515 and the field memory 512.
Output signal from the decoding circuit 506 to the FiOSS
The signal is switched and output according to the signal to obtain the original 48.6 MHz rate signal. This is called inter-field interpolation.

Next, in the moving part of the image, since the processing in the temporal direction (processing in the temporal direction) cannot be applied, the field interpolation circuit 505 interpolates the data in the field to obtain a data rate of 32.4 MHz. Output as a signal. In the process of interpolation, the FrOSS signal is used to perform phase compensation of interframe offset subsampling. This output signal is input to the sampling frequency conversion unit 509 and is 48.6 MH
It is input to the mixing circuit 517 as a z-rate signal. In the mixing circuit 517, the signal from the selector 516 and the signal from the sampling frequency conversion unit 509 are mixed and output at a ratio according to the motion detection signal from the motion detection circuit 503. The motion detection circuit 503 is controlled by a control signal of motion information such as a complete still image or a quasi still image decoded by the decoding circuit 506.

Further, in the MUSE method, when the camera pans, the subject is erroneously determined on the screen that the subject is moving and the moving part is processed to blur the screen even though the subject is stationary. Is being prevented. This method is called motion compensation, in which the encoder detects the motion vector of the image and transmits it as a control signal to the decoder. In the part that uses the signal of the previous frame during interpolation, only the size of this motion vector is used. Position correction is performed, and interframe interpolation is performed even if the screen is moving. This motion vector is extracted by the decoding circuit 506 and is given to the motion detection circuit 503 and the mixing circuit 517 as a braking signal.

As shown in FIG. 9F, for example, the MUSE signal transmits a still image portion in which the image changes stepwise, and FIG.
It is transmitted as shown in (A) and (B). In FIG. 8 and FIG. 9, black circles and white circles mean pixels, a solid line is an even field line, and a broken line is an odd field line. MU
The SE signal is composed of a signal having a 4-field cycle. When inter-frame interpolation is performed in the decoder, the result shown in FIG.
The signal has a rate of 32.4 MHz as shown in (C) (corresponding to the output of the selector 507). This signal is converted by the sampling frequency conversion unit 510 into a signal of 48.6 MHz rate as shown in FIG. Next, the sub-sampling circuit 511 produces the signal shown in FIG. 9 (E), and the interpolated portion is interpolated (corresponding to the output of the selector 516) and output as the signal shown in FIG. 9 (F). It Comparing FIG. 8D with FIG. 9F, the states of the contour portions are different even though the signals have the same 48.6 MHz rate. This is the difference between the inter-field interpolation processing.

By the way, since the MUSE decoder is a complicated and expensive device, an inexpensive device is demanded.
For this reason, recently, a simplified MUSE decoder has been developed. FIG. 6 shows an example of the configuration of a simplified MUSE decoder.

The MUSE signal is supplied to the input terminal 601. This MUSE signal is input to the A / D converter 602 and digitized by a 16.2 MHz clock. The digitized MUSE signal is decoded by the decoding circuit 604.
To the inter-frame interpolation circuit 606, the motion detection circuit 607, and the de-emphasis circuit 603.
It is input to the field interpolation circuit 608. The de-emphasis circuit 603 performs de-emphasis processing on the input MUSE signal. The decoding circuit 604 decodes the control signal and the like. The motion detection circuit 607 detects the motion of the image. Interframe interpolator 6
At 06, interframe interpolation processing is performed. The output of the inter-frame interpolation processing circuit 606 is the vertical low-pass filter 6
09 is input. The vertical low pass filter 609 is 1
The vertical frequency components of 125 TV lines are removed, and the aliasing component due to the inter-field offset is removed. The field interpolation circuit 608 performs field interpolation processing, and the output thereof is input to the mixing circuit 610. The output of the vertical low-pass filter 609 is also supplied to the mixing circuit 610, and both inputs are mixed according to the ratio of motion according to the motion detection signal from the motion detection circuit 607, and the output thereof is TCI (Time. -Compressed Integration) Supply to the decoding circuit 611. The TCI decoding circuit 611 is
The CI format decoding process is performed, and the output signal is input to the D / A converter 612. As a result, high-quality signals based on analog luminance and color difference signals are obtained at the output terminals 620, 621, and 622. Simple MUSE above
The decoder omits processing such as sub-sampling, and the output signal is deteriorated as compared with the normally decoded signal. Also, as a decoder for handling MUSE signals, M
A USE-NTSC converter is also being developed.

FIG. 7 shows a configuration example of the MUSE-NTSC converter. The MUSE signal is supplied to the input terminal 701, and is digitized by the A / D converter 702 at a clock of 16.2 MHz. The output of the A / D converter 702 is
The data is input to the decoding circuit 704, subjected to de-emphasis processing by the de-emphasis circuit 711, and then input to the field interpolation circuit 705. The field interpolation circuit 705 performs field interpolation, and the output is input to the scanning line conversion unit 706. Scan line conversion unit 706
Converts 1125 2: 1 interlaced signals to 525 2: 1 interlaced signals. The converted signal is input to the D / A converter 708, becomes an analog signal, and is input to the NTSC encoder 709. NT
The SC encoder 709 converts the signal into the current NTSC format and outputs it to the output terminal 710. The system is also provided with an S terminal 711.

Here, the VTR for recording / reproducing the output signal of the MUSE decoder is currently very complicated and expensive. Therefore, it is considered that it will take a long time to popularize, and a simple MUSE decoder is rather promising. On the other hand, it is considered that the MUSE-NTSC converter will be more prevalent for the owners of the current television receivers and VTRs.

[0015]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
If the E-decoders are arranged and the VTRs for recording the output signals of the MUSE decoder are arranged, it will be extremely expensive. Therefore, it takes a long time for the MUSE decoder and the MUSE signal recording VTR to become popular. Therefore,
It is considered that the simplified MUSE decoder will become popular.
On the other hand, the MUSE-NTSC converter may be popularized for users who own the current television receivers.

However, considering the case where the user purchases a high-definition television receiver after purchasing the MUSE-NTSC converter, a simplified MUSE decoder must be purchased, which is a concern for the future. . Furthermore, even if a simple MUSE decoder and a high-definition TV receiver are purchased, the current VTR and TV receiver currently owned are not expected to be utilized and there is concern about the future.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a television signal decoding device capable of supporting a high-definition television receiver, a current television receiver, and a current VTR by means of the cheapest possible means.

[0018]

According to the present invention, there is provided a first television including offset control sub-sampling between fields, offset sub-sampling between frames, band compression, and a control signal including a motion vector and motion information. In a television signal decoding device for converting a signal into a second television signal having a different number of scanning lines, a synchronization signal reproducing means for reproducing a synchronization signal of the first television signal and a control for decoding the control signal. Signal decoding means, first timing signal generating means for obtaining a first timing signal group for controlling the processing timing of the first television signal, and receiving a reference signal from the first timing signal generating means Controlling the second television signal based on this reference signal For synchronizing the timing of the control signal with the second timing signal group by using second timing signal generating means for obtaining a second timing signal group for output and a signal output from the second timing signal generating means. It is provided with timing adjusting means and signal processing means for performing signal processing of the second television signal using the output signal of the timing adjusting means.

[0019]

By the above means, the second television signal,
That is, it is possible to obtain a signal compatible with the current television receiver and VTR and a signal compatible with the high-definition television receiver.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. MUSE-
It is a configuration example in which an NTSC converter and a simplified MUSE decoder are combined. The MUSE signal is supplied to the input terminal 701, and is digitized by the A / D converter 702 at a clock of 16.2 MHz. The output of the A / D converter 702 is input to the decoding circuit 704, subjected to de-emphasis processing by the de-emphasis circuit 711, and then input to the field interpolation circuit 705. The field interpolation circuit 705 performs field interpolation, and the output is input to the scanning line conversion unit 706. The scanning line conversion unit 706 outputs 5 signals of 1125 2: 1 interlaces.
Convert to 25 2: 1 interlaced signals. The converted signal is input to the D / A converter 708, becomes an analog signal, and is input to the NTSC encoder 709. The NTSC encoder 709 converts the signal into the current NTSC format and outputs it to the output terminal 710.
The system is also provided with an S terminal 711.

Next, the output of the de-emphasis circuit 703 is input to the inter-frame interpolation circuit 606 and the motion detection circuit 607. The interframe interpolation circuit 606 performs interframe interpolation processing. Interframe interpolation processing circuit 606
Is output to the vertical low pass filter 609.
The vertical low-pass filter 609 removes 1125 TV vertical frequency components and removes aliasing components due to inter-field offset. Field interpolation circuit 6
At 08, field interpolation processing is performed, and its output is input to the mixing circuit 610. The output of the vertical low-pass filter 609 is also supplied to the mixing circuit 610, and both inputs are mixed according to the ratio of motion according to the motion detection signal from the motion detection circuit 607, and the output thereof is TCI (Time. -C
ompressed Integration) Decode circuit 611. The TCI decoding circuit 611 performs TCI format decoding processing and outputs the output signal to the D / A converter 6.
Enter in 12. Thereby, the output terminals 620, 62
High quality signals based on analog luminance and color difference signals are obtained at 1 and 622.

The above system can obtain a high definition television signal as well as an NTSC signal which can be handled by a current receiver and a current VTR. Here, the synchronous reproduction and control signal decoding circuit 70 is used depending on whether it is operated as a simplified MUSE decoder or operated as a NUSE-NTSC converter.
The operation mode of 4 is slightly different. This is a simplified MUSE
When operating as a decoder, the transmitted control signal may be decoded and the signal may be processed in synchronism with it, but when operating as a MUSE-NTSC converter, it may be converted to the signal of the current system. At 525
This is because it is necessary to create a control and timing signal (525 system signal) adapted to the 2: 1 interlaced signal.

Therefore, in this system, a decoding circuit 704 is provided so that control and timing signals (hereinafter referred to as 1125 system signals) corresponding to 1125 2: 1 interlace signals and 525 system signals can be obtained according to the operation mode.
Has been improved. FIG. 2 shows the decoding circuit 704 of this system.
The example of composition of is shown.

Digital MUS from A / D converter 702
The E signal is input to the synchronous reproduction circuit 750 and the control signal decoding unit 752. The sync reproduction circuit 750 reproduces the horizontal sync and frame sync signals and supplies them to the 1125 system timing generation circuit 751. Then, the 1125 system timing generation circuit 751
A timing signal of a signal processing system having 1125 scanning lines is created and output. Further, the 1125 system timing generation circuit 751 creates and gives the reference signal of the 525 system timing generation circuit 754. As a result, the 525 system timing generation circuit 754 creates a timing signal for the signal processing system having 525 scanning lines.

The vertical (V) blanking signal from the 1125 system timing generation circuit 751 and the vertical (V) blanking signal from the 525 system timing generation circuit 754 are input to the selector 764. Selector 764
Is a mode selection signal (MUSE
The V blanking signal according to the system operation mode is selected and derived by the decoder operation and the NTSC converter operation).

The 1125 system timing generation circuit 75
Clock from 1 and timing generation circuit 75 for 525 system
The clock from 4 is input to the selector 765. The selector 765 also selects and derives one of them by a mode selection signal (MUSE decoder operation, NTSC converter operation) given to the terminal 772. The clock corresponding to the operation mode output from the selector 765 is output to the output terminal 769 and is also applied as a conversion clock to the serial / parallel (P / S) converter 768 described later.

The decoding section 752 decodes the control signal transmitted by the expanded Hamming (8,4) code by the (8,4) Hamming decoding circuit 761,
Input to the majority decision circuit 762. Majority decision circuit 76
2 detects an error in the control signal and corrects the error if there is an error. Majority decision circuit 7
The control signal output from 62 is the compensation circuit 76.
Input to 3. For example, when there is an error in the inter-field offset sub-sampling phase (FiOSS) signal, the compensation circuit 763 compensates and uses the inverted data of the previous field and outputs it.

The control signal thus obtained is input to the selector 766. Selector 766 and flip-flop circuit 7 that latches the output of this selector
Reference numeral 67 is for selectively deriving a control signal in response to the V blanking signal output from the selector 764, and adjusts the timing with respect to the V blanking signal during system operation. The control signal (parallel data) output from the latch circuit 767 is output to the output terminal 771. The control signal is also input to the parallel / serial (P / S) converter 768. Then, it is converted into serial data by the clock corresponding to the operation mode and output to the output terminal 770.

FIG. 3 briefly shows an example of the timing and control signals of the above system. Figure 3 (a) shows MU
The SE signal, the figure (b) shows the V blanking signal, the figure (c) shows the control signal, and the figure (d) shows the state of the serial data.

Therefore, the 1125 system timing generation circuit 7
The various timing signals and control signals created by 51 are field interpolation circuit 705, interframe interpolation circuit 606, motion detection circuit 607, vertical low-pass filter 609, mixing circuit 610, TCI decoding circuit 6
11, the D / A converter 612, the scanning line conversion unit 706, and the like. The various timing signals and control signals generated by the 525-system timing generation circuit 754 are transferred to the scanning line conversion unit 706 and the D / A converter 70.
8, will be used in NTSC and the like.

According to the above-described embodiment, it is possible to operate as a simplified MUSE decoder or as a MUSE-NTSC converter according to the operation mode selection. Therefore, the current system of NTSC receiver,
The user who owns the VTR can easily accept the MUSE broadcasting, and there is no fear of acquiring a high-definition television receiver in the future. FIG. 4 shows still another embodiment of the present invention.

The above MUSE-NTSC converter is
The circuit of the moving image processing system in the MUSE decoder is taken out, and all the signal processing in the field is performed. For this reason, folding occurs in the high frequency region of the still image portion of the image, causing image deterioration. FIG. 10 is a diagram for explaining the problem. In the case of an image in which white and black are converted stepwise, the MUSE signal is as shown in FIG.
The signals of (A) and FIG. 8 (B) are alternately alternated for each frame. In the MUSE-NTSC converter,
Since processing is not performed between frames but only processing is performed within a field, the signals in FIGS. 8A and 8B are spatially crossed from surrounding pixels according to the inter-frame offset subsampling phase. Just interpolate. As a result, the signals in FIGS.
The signals of (G) and (H) are generated, and (B) and (C) of FIG. 10 are superimposed on the screen, and the interlaced scanning causes the contour portion to be jagged as shown in FIG. 10 (D). .

To improve this, Japanese Patent Application No. 3-241.
A device as shown in No. 18 is considered. This apparatus is provided with a sampling frequency conversion unit, a low frequency / high frequency separation unit, and a high frequency component processing unit between a scanning line conversion unit 705 and a D / A converter 706. This system is intended to remove the aliasing component by converting the sampling frequency of the scan line converted signal, dividing it into a low band component and a high band component, and averaging the high band component.

FIG. 4 shows an example in which the present invention is applied to the MUSE-NTSC converter disclosed in Japanese Patent Application No. 3-24118. The same parts as those in FIG. 1 are designated by the same reference numerals.
The difference from the previous circuit is that the following circuit is provided between the scanning line conversion unit 706 and the D / A converter 708. The 525 2: 1 interlace signal output from the scanning line conversion unit 706 is input to the sampling frequency conversion circuit 720. The sampling frequency conversion circuit 720 has the characteristics defined by the impulse response characteristics, multiplies the sampling frequency by 3/2, and converts the signal into a 48.6 MHz signal for output. The output of the sampling frequency conversion circuit 720 is input to the low pass filter 721 and the subtractor 722. The output of the low pass filter 721 is also supplied to the subtractor 721. A low-pass component is obtained from the low-pass filter 721, and a high-pass component is obtained from the subtractor 722.

The high frequency component output from the subtractor 722 is input to the sub-sampling circuit 723. The sub-sampling circuit 723 performs sub-sampling processing in accordance with the FiOSS signal from the decoding circuit 704, and converts it into a 24.3 MHz signal. This signal is supplied to one terminal of the field memory 724 and the selector 727. Further, the output of the field memory 724 is input to the 1H delay memory 725 and the adder 726. And in the adder 726,
The 1H delay memory 725 and the output of the field memory 724 are added and the average value thereof is taken. This adder 72
The output of 4 (interpolation signal) is input to the selector 725.
The selector 725 switches and outputs either the output of the adder 724 or the output of the sub-sampling circuit 721 according to the FiOSS signal. In other words, inter-field interpolation processing is applied to high frequency components. The signal obtained here is input to the adder 728, and the low-pass filter 721 is input.
Is added to the low frequency component from. The output of the adder 728 is
After being input to the D / A converter 708 and converted into an analog signal, it is input to the NTSC encoder 709. As a result, the television signal of the current system can be obtained at the output terminal 710. The NTSC encoder 709 is also provided with an S terminal 711. Since the other parts are the same as the circuit of FIG. 1, description thereof will be omitted.

[0036]

As described above, according to the present invention,
A signal compatible with a high-definition television receiver, a current television receiver, and a current VTR can be obtained by an inexpensive means.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of the decoding circuit in FIG.

FIG. 3 is a signal waveform diagram shown for explaining the operation of the circuit of FIG.

FIG. 4 is a circuit block diagram showing another embodiment of the present invention.

FIG. 5 is a circuit block diagram showing a MUSE decoder.

FIG. 6 is a circuit block diagram showing a simplified MUSE decoder.

FIG. 7 is a circuit block diagram showing a MUSE-NTSC converter.

FIG. 8 is a diagram shown for explaining the configuration and processing of a MUSE signal.

FIG. 9 is a diagram for explaining the configuration and processing of the MUSE signal.

FIG. 10 is a diagram for explaining problems of the NUSE-NTSC converter shown in FIG. 7.

FIG. 11 is a diagram showing an impulse response in the MUSE method.

[Explanation of symbols]

606 ... Inter-frame interpolation circuit, 607 ... Motion detection circuit,
609 ... Vertical low-pass filter, 610 ... Mixing circuit, 6
11 ... TCI encoder, 612 ... D / A converter, 70
2 ... A / D converter, 703 ... De-emphasis circuit, 7
04 ... Synchronous reproduction and control signal decoding circuit, 705
... field interpolating circuit, 706 ... scanning line converting section, 70
8 ... D / A converter, 709 ... NTSC encoder.

Claims (2)

[Claims] 1. A first television signal, which is offset subsampled between fields, band-compressed by offset subsampling between frames, and includes a control signal including a motion vector and motion information, having a different number of scanning lines. In a television signal decoding device for converting into a second television signal, a synchronization signal reproducing means for reproducing a synchronization signal of the first television signal, a control signal decoding means for decoding the control signal, the first First timing signal generating means for obtaining a first timing signal group for controlling the processing timing of the television signal of the above, and a reference signal from the first timing signal generating means, and based on this reference signal, A second timing signal for controlling the second television signal Second timing signal generating means for obtaining a group, timing adjusting means for synchronizing the timing of the control signal with the second timing signal group by using the output signal of the second timing signal generating means, and the timing The second signal is output by using the output signal of the adjusting means.
And a signal processing means for performing signal processing of the television signal of (1). 2. The timing adjusting means comprises:
Means for synchronizing the timing of the control signal with the second timing signal group using the output signal of the timing signal generating means, and further using the output signal of the timing adjusting means for the first television. 2. The television signal decoding device according to claim 1, further comprising a second signal processing means for performing signal processing of the signal.