JPH0610906B2 - Delay circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a delay circuit suitable for application to a video tape recorder (hereinafter referred to as VTR) for recording / reproducing a television signal or the like.

[Prior Art] When reproducing a magnetic tape recorded using the same VTR, reproduction tracking adjustment is not necessary.

However, when reproducing magnetic tapes recorded by different VTRs, it may be necessary to adjust reproduction tracking.

In particular, even if the VTRs have the same standard, if the manufacturers are different, this tracking adjustment problem occurs.

For this reason, the VTR is usually provided with means for adjusting this tracking externally.

The tracking adjustment means is provided with a delay circuit 10 as shown in FIG. 3, in which a tracking control signal is generated.

As shown in the figure, the delay circuit 10 has a variable resistor R0 and a capacitor C0 connected in series.
The delay time is changed by changing the value of.

The delay circuit 10 also includes a discharge circuit 11 for discharging the electric charge of the capacitor C0 and a charge recognition circuit 12 for recognizing that the capacitor C0 has been charged.

The discharge circuit 11 is composed of a transistor Tr1 and resistors R1 and R2. The mono-multi reset signal m is supplied to the base of the transistor Tr1, and the electric charge of the capacitor C0 is discharged when the mono-multi reset signal m becomes high level.

The charge recognition circuit 12 includes a transistor Tr2 and resistors R3 and R.
It is composed of 4 and R5. Since the transistor Tr2 is turned on when the charging of the capacitor C0 is completed, it is possible to recognize the completion of the charging of the capacitor C0 by detecting this ON state.

In the delay circuit 10 having such a configuration, as shown in FIG. 4A, when the activation signal a is in the low state, the monomulti-reset signal m is in the high state, and the transistor T of the discharge circuit 11 is
Turn on r1. As a result, the electric charge of the capacitor C0 is discharged.

At this time, the transistor Tr2 of the charge recognition circuit 12 is in the off state, and the off signal (high level) is output to the control signal terminal C via the inverter 13 connected to the collector side of the transistor Tr2.

Next, when the activation signal a is inverted to the high state, the mono-multi reset signal m goes to the low state and the transistor Tr1 of the charging circuit 11 is turned off.

Therefore, the charging of the capacitor C0 is started as shown in FIG. 4B.

When the charging of the capacitor C0 is completed, the charge recognition circuit 12
Transistor Tr2 is turned on, and an on signal is output to the control terminal C as shown in FIG. 4C.

Therefore, the control signal c is delayed from the start signal a by the delay time (charging time) T set by the time constant of the variable resistor R0 and the capacitor C0.

[Problems to be Solved by the Invention] By the way, in the above-described configuration, when reproducing a tape recorded by a VTR having a different recording pattern, the variable resistor R0 must be changed each time for tracking adjustment. There was a problem.

Therefore, every time the tracking adjustment is performed, it is necessary to rotate the tracking adjustment knob provided on the VTR main body, and for that purpose, the operator must always approach the VTR main body.

In view of the above, the present invention proposes a delay circuit in which such a conventional problem is simply solved and the delay time for tracking adjustment can be changed even by remote operation. is there.

[Technical Means for Solving Problems] In order to solve the problems described above, in the present invention, a time constant of a capacitor and a resistor in a delay circuit in a video tape recorder for recording and reproducing a television signal or the like. A reference time delay circuit for delaying a signal for a predetermined time, a count register for counting and storing a lock signal corresponding to a predetermined time, an addition register for storing external data as auxiliary data for tracking adjustment, and the count register And a delay time adjusting circuit for varying the delay time by external data based on the delay time of the reference time delay circuit, and an adder for adding the measured data and the external data of the addition register. The delay time adjusting circuit stores a delay time adjusted by the delay time adjusting circuit, and a start signal is input. A count circuit that starts counting, a comparison circuit that compares the data of the storage means with the output data of the count circuit, and outputs a data match signal when they match, and a system control circuit that drives and controls each circuit. The control signal is output by delaying the start signal by a delay time adjusted by external data.

[Operation] In this configuration, when the delay time is changed, the delay time adjusting circuit 3 receives the data from the outside based on the time t1 preset in the reference time delay circuit 2 before the activation signal a is input. The delay time is variable depending on T2.

The external data T2 is data for tracking adjustment set by being controlled remotely by a remote controller or the like.

The data T0 in consideration of the external data T2 is stored in the storage unit 4.

Next, when the activation signal a is input, the counter circuit 5 starts counting.

The data T0 of the storage means 4 and the output data of the counter circuit 5 are compared in the comparison circuit 6.

When the above-mentioned two data contents match in the comparison circuit 6, the data match signal d is output.

The control signal c is output based on the data coincidence signal d.

As a result, the control signal c is the time t0 corresponding to the data T0 changed by the external input after the activation signal a is input.
Is delayed and output.

Therefore, the delay time for tracking adjustment can be easily changed by remote control.

[Example] Next, a case where an example of the delay circuit according to the present invention is applied to a tracking adjustment circuit of a VTR will be described in detail with reference to FIG.

FIG. 1 is a diagram showing a specific configuration of the delay circuit according to the present invention.

In the figure, reference numeral 1 is a delay circuit, and this delay circuit 1 is composed of a reference time delay circuit 2, a delay time adjusting circuit 3, a register 4 as a storage means, a counter circuit 5, a comparison circuit 6 and a system control circuit 7. There is.

The reference time delay circuit 2 has substantially the same circuit configuration as the conventional delay circuit 10, and includes a discharge circuit 11, a charge recognition circuit 12, a variable resistor R0 and a capacitor C0.

The delay time adjustment circuit 3 includes an AND gate 31, a count register 32, an addition register 33, and an adder 34.

The counter circuit 5 has an AND gate 51 and a count register 52.

A case where the VTR tracking adjustment is performed using the delay circuit 1 having such a configuration will be described below in detail with reference to the timing chart of FIG.

Before the activation signal a shown in FIG. 2A is input to the system control circuit 7 (when it is in a low state), the reference time delay circuit 2 measures a preset delay time t1 (hereinafter referred to as reference time). .

In the discharge circuit 11, the mono-multi-reset signal m shown in FIG. 2B supplied from the system control circuit 7 is normally in the on state (low level), and the transistor Tr1 operates so that the electric charge of the capacitor C0 is discharged. There is no state.

When measuring the reference time, the system control circuit 7 first turns off the mono-multi reset signal and controls the transistor Tr1 of the discharge circuit 11 to be in the cut-off state.

As a result, charges are stored in the capacitor C0 as shown in FIG. 2C.

At this time, the charge completion signal e (high level signal) as shown in FIG. 2D is supplied to the AND gate 31 from the collector side of the transistor Tr2 provided in the charge recognition circuit 12.

The AND gate 31 is supplied with a high-level signal until the transistor Tr2 in the charge recognition circuit 12 is turned on (until charging is completed).

When the charging is completed, the low-state signal e is supplied to the system control circuit 7 and the AND-gate 31.

As described above, after the transistor Tr1 is turned on and discharged, only the period until the charging of the capacitor C0 is completed,
And gate 31 is opened.

On the other hand, the AND gate 31 has a counter clock terminal K.
Is supplied with a clock signal k (shown in FIG. 2E) having a constant period.

The system control circuit 7 sets the register clear signal r (shown in FIG. 2F) to the low state at the same time when the charging of the capacitor C0 is started (when the mono-multi-reset signal m is in the low state), and the count register 32 functions. Put in a state.

As a result, the count register 32 counts the clock signal k output from the AND gate 31 while the capacitor C0 is being charged. Therefore, as shown in FIG. 2G, the reference time t1 corresponding to this count value T1 can be measured from the count value T1 of the resist 32.

Next, data T2 (shown in FIG. 2H) to be adjusted based on the reference time t1 is supplied to the system control circuit 7 from the external input terminal 8, for example, the switches 8A and 8B.

This data T2 can be remotely controlled by a remote controller or the like, and acts as auxiliary data for tracking adjustment. The external data T2 is supplied to the addition register 33 as data corresponding to the adjustment time t2.

Next, the measured value T stored in the count register 32
1 and the data T2 of the addition register 33 are added by the adder 34, and the addition data T0 (shown in FIG. 2I) is stored in the register 4 which is a storage means.

After that, the activation signal a (high signal) is transmitted to the system control circuit 7
Input to the count register 52 from the system control circuit 7 to the register clear signal p as shown in FIG. 2J.
Is supplied.

As a result, the count register 52 outputs the clock signal k (second clock signal) output from the count clock terminal K at a constant cycle.
(Shown in FIG. E) and the count enable signal s (shown in FIG. 2J) supplied from the system control circuit 7 are AND gate 51.
And the output clock signal k is counted by the count register 52.

The count value of the count register 52 is supplied to the comparison circuit 6 and compared with the data T0 stored in the register 4.

As a result, when the data values match, the comparison circuit 6 supplies the data matching signal d as shown in FIG. 2K to the system control circuit 7.

When the data coincidence signal d is supplied, the system control circuit 7
Then, the control signal c as shown in FIG. 2L is output.

That is, since the delay time is counted using the same counter clock k, the count value T0 stored in the register 4 and the count value of the count register 52 match. In other words, the count values match. Therefore, the output of the control signal c is delayed from the input of the activation signal a by the time t0 corresponding to the data T0 stored in the register 4.

Therefore, the control signal c is output after being delayed by the delay time adjusted by the external input after the activation signal a is input.

Note that any external data T2 for tracking adjustment can also be obtained by manually operating the external switches 8A and 8B.

Of course, it is also possible to remotely operate the external input circuit 8 and input the adjustment data T2 to the addition register 33.

Further, in this embodiment, the delay circuit according to the present invention is used for tracking adjustment, but the present invention is not limited to this, and it is also possible to use it for the purpose of remotely adjusting other delay times.

The timing of the data T2 shown in FIG. 2H is supplied to the addition register 33 at the same time as the data T1 in this embodiment, but the timing is not limited to this and may be any time as long as the activation signal a becomes the high state.

Further, the count permission signal s is the start signal a in this embodiment.
Is in the high state at the time when is turned to the high state (see J in FIG. 2), the count enable signal s has only to be in the high state by the time the activation signal a becomes the high state, and is limited to this timing. Not a thing.

As described above, according to the present invention, in a delay circuit in a video tape recorder for recording and reproducing television signals and the like, a reference time delay circuit for delaying a signal for a predetermined time from a time constant of a capacitor and a resistor is provided. , A count register that counts and stores a clock signal corresponding to a predetermined time, an addition register that stores external data as auxiliary data for tracking adjustment, a measurement value stored in the count register, and external data of the addition register And a delay time adjusting circuit for varying the delay time by external data based on the delay time of the reference time delay circuit, and a delay time adjusted by the delay time adjusting circuit. Storage means for storing, a count circuit for starting counting by input of a start signal, The data of the storage means and the output data of the count circuit are compared with each other, and a comparison circuit for outputting a data coincidence signal when they coincide with each other and a system control circuit for driving and controlling each of the circuits are provided. The control signal is output after being delayed from the start signal by the adjusted delay time.

According to the configuration of the present invention, the delay time can be changed by the external input circuit capable of digital processing.
The delay time can be easily adjusted by remote control such as remote control. Further, the delay time can be adjusted by the external data with a very simple configuration of counting the clock signal.

Therefore, the delay circuit according to the present invention has the above-mentioned VT.
It is extremely suitable when applied to R and the like.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of a delay circuit according to the present invention,
FIG. 2 is a timing chart of a delay circuit according to the present invention, FIG. 3 is a system diagram showing an example of a conventional delay circuit, and FIG.
The figure is a timing chart of a conventional delay circuit. 1 ... Delay circuit 2 ... Reference time delay circuit 3 ... Delay time adjusting circuit 4 ... Storage means 5 ... Counter circuit 6 ... Comparison circuit 7 ... System control circuit a ... Start signal c ... Control signal d: Data match signal

Claims (1)

[Claims] 1. A delay circuit in a video tape recorder for recording and reproducing television signals and the like, comprising a reference time delay circuit for delaying a signal for a predetermined time from a time constant of a capacitor and a resistor, and a lock signal corresponding to the predetermined time. A count register for counting and storing, an addition register for storing external data as auxiliary data for tracking adjustment, and an adder for adding the measured value stored in the count register and the external data of the addition register. A delay time adjusting circuit for varying the delay time based on the data from the outside based on the delay time of the reference time delay circuit, storage means for storing the delay time adjusted in the delay time adjusting circuit, and a start signal Count circuit for starting counting by input, data in the storage means and the count The output signal of the path is compared and a comparison circuit that outputs a data coincidence signal when they match each other and a system control circuit that drives and controls each of the circuits are provided, and a start signal for a delay time adjusted by external data. A delay circuit, which further delays and outputs a control signal.