JPH06102533A - Thin film transistor matrix - Google Patents

Abstract

PURPOSE:To obtain the thin film transistor(TFT) matrix which provides high display luminance without decreasing the occupation area of a pixel electrode by a TFT by forming the TFT on an opening formed in a gate bus line. CONSTITUTION:In the gate bus line 1, the opening 10 which is thin and long is formed nearby one side along the extension direction of the gate bus line, and the part between the opening 10 and one side of the gate bus line 1 is utilized as a gate electrode 30. A gate insulating film 7 is formed on the gate bus line 1 provided with the opening 10 and an active layer 8 consisting of an amorphous silicon layer is formed on the gate electrode 30 across the gate insulating film 7. On the active layer 8, a source electrode 4 and a drain electrode 5 which is connected to a drain bus line 2 are formed. In this constitution, the arrangement and area of a pixel electrode 6 connected to the source electrode 4 can be set without restrictions of the structure of the TFT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor matrix in which transistors each having an amorphous silicon film as an active layer are arranged in a matrix on a substrate.

There is an increasing demand for liquid crystal display devices capable of color display on a large screen. Half-selection easily occurs due to the increase in the resistance and capacitance of the electrodes accompanying the expansion of the display screen, and as a result, the display quality deteriorates. Since an active matrix type liquid crystal display device having a transistor for each pixel can avoid the influence of half selection, high quality display is possible.

[0003]

2. Description of the Related Art A typical structure example of an electrode of a conventional active matrix type liquid crystal display incorporating a thin film transistor (TFT) using an amorphous silicon film is a plan view of FIG. 7 (a). And its XX cross section (b). On one surface of the substrate 9, for example, a plurality of gate bus lines 1 extending in the row direction and a plurality of drain bus lines 2 extending in the column direction are arranged. The gate bus line 1 and the drain bus line 2 are separated by a gate insulating film 7. Although only one gate bus line 1 and one drain bus line 2 are shown in FIG. 7, the gate electrode 3, the source electrode 4, and the drain electrode 5 are provided near the intersection of the plurality of bus lines.
And a TFT consisting of the active layer 8 and. The gate electrode 3 is connected to the gate bus line 1, and the drain electrode 5 is connected to the drain bus line 2. A light-transmissive pixel electrode 6 is connected to the source electrode 4.

In the conventional electrode structure shown in FIG. 7, the pixel electrode 6 is formed so as to avoid the TFT. That is, TF
The area occupied by the pixel electrode 6 must be reduced by the amount of T, and the display brightness is reduced. Although the display brightness can be improved by increasing the brightness of the backlight, an increase in power consumption cannot be avoided.

It is an object of the present invention to provide a TFT matrix having a structure in which the area occupied by the pixel electrode 6 by the TFT is not reduced.

[0006]

The above object is to provide a plurality of gate bus lines formed on one surface of an insulating substrate so as to extend in parallel to each other in the row direction, and to arrange the gate bus lines in the row direction. A plurality of openings formed on one side at regular intervals, a gate insulating film formed so as to cover the gate bus line, and the gate bus line between the one side in the row direction and each of the openings A plurality of island-shaped semiconductor layers formed on the above-mentioned portion through the gate insulating film,
A source electrode and a drain electrode, which form a plurality of electrode pairs formed in contact with the semiconductor layer and facing each other with a channel region defined so as to cross the semiconductor layer, and on the gate insulating film. And a plurality of drain bus lines connected to the drain electrodes, which are arranged on the same column, and a plurality of drain bus lines formed on the gate insulating film so as to be connected to the source electrodes, respectively. According to the present invention, characterized in that
Achieved by the TFT matrix.

[0007]

[Operation] FIG. 1 is an explanatory view of the principle structure of the present invention.
(a) is a plan view and (b) is a sectional view taken along line XX in (a).

As shown, the gate bus line 1 has
The opening 10 is formed in the vicinity of one side along the extending direction, and the portion of the gate bus line 1 between the opening 10 and the side is used as the gate electrode 30. Ie the opening
A gate insulating film 7 is formed as usual on the gate bus line 1 provided with 10, and an active layer 8 made of, for example, amorphous silicon is formed on the gate electrode 30 through the gate insulating film 7. . On the active layer 8
Similar to TFT, source electrode 4 and drain bus line 2
A drain electrode 5 connected to is formed.

In the present invention, as is apparent from FIG. 1, the arrangement and area of the pixel electrode 6 connected to the source electrode 4 are not affected by the TFT at all. That is, according to the present invention, the region in the vicinity of each intersection of the gate bus line 1 and the drain bus line 2 can be used substantially as the exclusive region of the pixel electrode 6. Therefore, the display brightness of the liquid crystal display device using the TFT matrix can be increased.

[0010]

2 to 4 are process explanatory views of an embodiment of the present invention, in which the left column is a plan view and the right column is a sectional view taken along line XX in the corresponding plan view.

Referring to FIGS. 2 (a1) and 2 (a2), a titanium (Ti) film having a thickness of 800 Å is deposited on one surface of a substrate 9 made of glass by, for example, a well-known sputtering method. The gate bus line 1 having a width of 40 μm is formed by patterning using a well-known lithographic technique. In this patterning, the opening 10 is formed in the gate bus line 1. The opening 10 is 12μ from one side of the gate bus line 1.
It is formed at the position of m, and the length along this side is about 50 μm.
A plurality of drain bus lines 2 are provided along this side at an array pitch of 110 μm, which will be described later.

Then, as shown in FIGS. 2 (b1) and 2 (b2), a thickness of about 400 made of Si ₃ N ₄ covering the gate bus line 1 is applied.
0 Å gate insulating film 7, 150 Å thick active layer 8 made of amorphous silicon and Si ₃ N ₄ thickness
A 1200Å protective layer 12 is sequentially formed. These may be formed by a well-known chemical vapor deposition method (CVD), particularly a plasma CVD method in which a plasma is generated in a raw material gas having a low pressure of about 100 Pa to cause a gas phase reaction. Then, as shown in FIG.
As shown in 1) and (c2), a resist mask 13 is formed on the gate electrode 30. This formation is performed by applying a positive resist on the protective layer 12 and irradiating light from the back surface of the substrate 9 in a manner self-aligned with the gate electrode 30 as in the case of manufacturing a normal TFT matrix. A method of forming the mask 13 is used. Then, the protective layer 12 exposed from the resist mask 13 is selectively etched. This etching may be performed using, for example, a buffered hydrofluoric acid solution.
After that, as shown in FIGS. 2D1 and 2D2, the resist mask 13 is removed.

Next, as shown in FIGS. 3 (e1) and (e2), a contact layer 14 made of, for example, n-type amorphous silicon and having a thickness of about 500 Å and a thickness of about 1000 Å made of Ti are formed on the active layer 8. The source / drain electrode layer 15 is sequentially deposited. The contact layer 14 made of amorphous silicon may be formed by the plasma CVD method, and the source / drain electrode layer 15 made of Ti may be formed by the sputtering method.

Then, as shown in FIGS. 3 (f1) and (f2),
In addition, using well-known lithographic technology,
Resist mask 17 on the electrode layer 15₁And 17₂To form
It Resist mask 17₁And 17₂Is the drain described later
It corresponds to the electrode and the source electrode, respectively. Figure 3 (g
As shown in 1) and (g2), resist mask 17₁and
17 ₂Exposed from the source / drain electrode layer 15,
Contact layer 14 and active layer 8 are selectively etched
To do. The etching of these layers is performed with chlorine (Cl₂) And boron trichloride
Elementary (BCl₃) Reactive gas with a mixed gas as an etchant
Etching (RIE) may be used. After that,
Gist Mask 17₁And 17₂To remove. Like this
Source electrode 4 and drain electrode 5 are formed,
In addition, the individual TFTs are separated.

Then, the entire thickness of the substrate 9 is, for example, about 20.
By depositing a 00Å molybdenum (Mo) layer by a sputtering method and patterning this Mo layer by using a well-known lithographic technique using phosphoric acid as an etchant, as shown in FIG.
As shown in 1) and (h2), the drain bus line 2 connected to the drain electrode 5 is formed.

Next, a transparent conductive film made of indium tin oxide (ITO) is deposited on the entire substrate 9 by using, for example, a sputtering method, and is patterned by using a well-known lithographic technique. As shown in i1) and (i2), the pixel electrode 6 connected to the source electrode 4 is formed. In this way, the TFT matrix of the present invention is completed.

FIG. 5 is an explanatory view of another embodiment of the present invention. As shown in FIG. 5 (a), the opening 10 provided in the gate bus line 1 and the side of the gate bus line 1 are connected. The notch 11 is provided, and the portions of the gate bus line 1 remaining on both sides of the notch 11 are used as gate electrodes.
That is, after forming a gate insulating film covering the gate bus line 1 shown in FIG. 5 (a) and forming an active layer (not shown) on each part on both sides of the notch 11,
As shown in (b), source electrodes 4 ₁ and 4 ₂ and drain electrodes 5 ₁ and 5 ₂ are formed. The source electrodes 4 ₁ and 4 ₂ are connected to the pixel electrode 6, and the drain electrodes 5 ₁ and 5 ₂ are connected to the drain bus line 2. Redundancy can be provided by forming a plurality of each TFT that constitutes the matrix in this way.

FIG. 6 is a view for explaining still another embodiment of the present invention, in which the gate bus line 1 is provided with two openings 10 ₁ and 10 ₂ which are parallel to each other, and the side of the opening 10 ₁ and the gate bus line 1. , And the portions between the openings 10 ₁ and 10 ₂ are used as gate electrodes to form two TFTs and provide redundancy.

In both cases of FIGS. 5 and 6, the pixel electrode 6
The occupied area of is not narrowed by TFT.

[0020]

According to the present invention, it is possible to obtain a high display brightness without reducing the area occupied by the pixel electrode in the display device using the TFT matrix because the gate of the TFT is provided. Become. As a result, it is not necessary to increase the brightness of the illumination light source such as the backlight, which contributes to lower power consumption.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle structure of the present invention.

FIG. 2 is a process explanatory view of the embodiment of the present invention (No. 1)

FIG. 3 is a process explanatory diagram of the embodiment of the present invention (No. 2)

FIG. 4 is a process explanatory diagram of the embodiment of the present invention (No. 3)

FIG. 5 is an explanatory view of another embodiment of the present invention.

FIG. 6 is an explanatory view of still another embodiment of the present invention.

FIG. 7 is an explanatory diagram of conventional problems

[Explanation of symbols]

1 Gate Bus Line 2 Drain Bus Line 3 Gate Electrode 4, 4 ₁ , 4 ₂ Source Electrode 5, 5 ₁ , 5 ₂ Drain Electrode 6 Pixel Electrode 7 Gate Insulating Film 8 Active Layer 9 Substrate 10, 10 ₁ , 10 ₂ Opening 12 Protective layer 13 Resist mask 14 Contact layer 15 Source / drain electrode layers 17 ₁ and 17 ₂ Resist mask 30 Gate electrode

Claims (3)

[Claims] 1. A plurality of parallel gate bus lines formed on one surface of an insulating substrate so as to extend in the row direction, and fixed to each of the gate bus lines along one side parallel to the row direction. A plurality of openings formed at intervals, a gate insulating film formed so as to cover the gate bus line,
A plurality of island-shaped semiconductor layers formed via the gate insulating film on a portion of the gate bus line between one side parallel to the row direction and each of the openings; A plurality of pairs of source electrodes and drain electrodes formed so as to face each other with a channel region defined across the semiconductor layer in between and in contact with the semiconductor layer respectively, and in a column direction on the gate insulating film. A plurality of drain bus lines each formed to extend and arranged on the same column and connected to the plurality of drain electrodes, and on the gate insulating film so as to connect to each of the source electrodes A thin film transistor matrix comprising a plurality of pixel electrodes formed on the substrate. 2. A second opening provided in the gate bus line in a region opposite to one side in the row direction with respect to each of the openings, and a portion between the opening and the second opening. A plurality of island-shaped second semiconductor layers formed on the gate insulating film so as to correspond to the gate bus lines;
A plurality of electrode pairs formed so as to respectively contact the second semiconductor layer and face each other with a channel region defined in the second semiconductor layer interposed therebetween, one of each pair being the above-mentioned. 2. The thin film transistor matrix according to claim 1, further comprising a plurality of pairs of a second source electrode and a drain electrode connected to the drain bus line and the other connected to the pixel electrode. 3. A plurality of cutouts provided in the gate bus line so as to connect each of the openings and one side extending in the row direction, and the cutouts remaining on both sides of each of the cutouts. A plurality of island-shaped semiconductor layers formed on the gate bus line via the gate insulating film, and contacting each of the semiconductor layers and facing each other with a channel region defined by the semiconductor layer interposed therebetween. A plurality of electrode pairs formed, one of each pair being connected to the drain bus line and the other being a plurality of pairs of source and drain electrodes connected to the pixel electrode. A thin film transistor matrix according to claim 1, characterized in that