JPH0590987A - Method for reducing interference in reception - Google Patents

Abstract

PURPOSE:To reduce interference in reception such as a high-order harmonic signal from a clock pulse oscillator or the like provided in a radio communication equipment. CONSTITUTION:A modulator 9 having an oscillating frequency is provided to a clock pulse generator generating a clock signal to control the CPU of the control circuit 4, and the modulation wave is spread to reduce the reception interference in by adding a modulation signal to be modulated to a frequency range controlled by the CPU to make modulation. Moreover, the output of a noise amplifier 11 in a reception circuit 2 is utilized for the modulation signal, then an average harmonic level is decreased by moving the harmonic along with a time function is a maximum modulation frequency range to reduce the reception disturbance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reducing reception interference due to harmonics of an oscillator provided in a control circuit of a wireless communication device.

[0002]

2. Description of the Related Art In a radio communication device controlled by a CPU or the like, reception interference may be caused by a high-order harmonic generated simultaneously with a control frequency from a clock oscillator provided in a control circuit. Therefore, various measures have been taken to prevent high-order harmonics from being mixed into the receiving circuit system. Figure 4
Shows a conventional example of a circuit for reducing harmonics radiated from an internal circuit of a wireless communication device.

In FIG. 4, 1 is an antenna, 2 is a receiving circuit, 3 is a local oscillation circuit, and 4 is a control circuit. The control circuit 4 is shielded 7 to prevent the harmonics of the clock oscillator of the control circuit 4 from leaking into the receiving circuit. Further, a decoupling 8 is provided on the power supply line 6 so that the power supply line 6 does not enter harmonics into the receiving circuit 2. Further, the CPU of the control circuit 4 is also configured to output to the control signal 5 through the decoupling 8 so that the harmonics are not output on the control signal 5 by the CPU of the control circuit 4. Was being reduced.

[0004]

In the conventional method as described above, the distance between the control circuit of the interference source and the receiving circuit cannot be sufficiently secured or the shielding cannot be performed depending on the size of the equipment and the arrangement of parts. I couldn't take sufficient measures.
In addition, the implementation of these measures inevitably made the device larger, which constrained the design. Furthermore, by separating, strengthening, and adding decoupling of the power supply line and ground line, the number of wiring lines, the number of parts, etc. is increased, the wiring width is expanded, etc. Due to the increase, etc., it has been a hindrance to price reduction, weight reduction, miniaturization, and design.

Functionally, in the method of reducing the above-mentioned reception interference, the reception sensitivity is practically limited to -10 dB. Technological innovation enables even higher sensitivity reception, nominally -12 dB, real -20 d
When it comes to B, the conventional method cannot handle it. The present invention has been made to solve the above problems.

[0006]

A clock oscillator for a clock signal input to a CPU of a control circuit normally uses a ceramic oscillator having an oscillation frequency less stable than a crystal oscillator to generate the clock signal. Assuming that the clock signal input to the CPU is 200 kHz, fluctuations of ± 20 kHz will not hinder the CPU operation. By utilizing the stable operation area of the CPU with respect to the change of the clock signal, reception interference is reduced.

As a means for this, a modulator for modulating the oscillation frequency is connected to the clock oscillator, and the modulation frequency within the range in which the CPU operates stably is supplied to the modulator for frequency modulation. The CPU is controlled by the signal of the frequency-modulated clock oscillator, but the harmonics generated at the same time as the modulated frequency are further modulated by the harmonics of the modulation frequency for each harmonic, resulting in frequency spreading. By reducing the signal level by the seed Bessel function, reception interference due to harmonics is reduced. Further, the modulated signal is used as a noise amplifier output for generating a squelch signal of the receiving circuit, whereby the harmonic moves in the modulation frequency band as a function of time, thereby reducing the average level of the harmonic.

[0008]

[Operation] The oscillation frequency of the clock oscillator of the control circuit is set to CP
U harmonics that are simultaneously generated by applying modulation in a range that does not hinder operation are spread by increasing the harmonics of the modulated signal, and thus the signal level value obtained by the first Bessel function is reduced. it can.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is not intended for the operation and signal flow related to a normal circuit, but for the measures against unnecessary radio waves generated from the circuit configuration. Therefore, only the circuit used in the invention will be described. Not enough. Therefore, it is necessary to explain it in comparison with a normal circuit.

FIG. 3 is a circuit diagram of a basic configuration of a receiver to be compared with the present invention. 3 will be described. Reference numeral 1 is an antenna, 2 is a receiving circuit, 3 is a local oscillation circuit, and 4 is a control circuit. The harmonics of the operating clock of the control circuit, which is a problem here, are mixed into the receiving circuit and generate reception interference. Therefore, this receiver is an amateur radio 144
Considering the MHz band F ₃ communication device, if the local oscillator is set to receive 145 MHz, the reception selection bandwidth is 15
Actually 144.925 MHz to 145.00 because the frequency is kHz.
It will receive 15 kHz between 75 MHz. The clock signal for operating the CPU of the control circuit 4 is a 200 kHz signal oscillated by the clock oscillator. This 200k
Of the harmonics of the Hz oscillation, the reception band 144.9925MHz ~ 14
For the harmonics lying between 5.0075 MHz, the 725th harmonic will fall within this reception selection band. That is, the harmonic interference signal 10 radiated from the control circuit 4 is input to the antenna 1, is mixed with the local oscillator circuit or the receiver system through the control signal line 5, or is received by the power line. There are things that get mixed into the circuit, and even if there is no signal, it shows the circuit operating state as if the received signal entered and causes reception interference. In addition to the 725th harmonic, the 720th to 730th harmonics are in the reception band, so that reception interference occurs at the corresponding reception point according to the same reception frequency setting.

The receiving circuit of the present invention will be described with reference to FIG. In the figure, 1 is an antenna, 2 is a receiving circuit, 3 is a local oscillation circuit, 4 is a control circuit, and the control circuit 4 has a modulator 9 for modulating the oscillation frequency of a clock oscillator. The modulation signal of the modulator 9 is an oscillator 12 (not an independent oscillator but may be, for example, a signal obtained by dividing a clock oscillator), or noise that generates a control signal of the squelch circuit from the output side of the demodulation signal of the reception circuit. The noise signal from the amplifier 11 is taken out, and one of the signals is supplied to the modulator 9 for modulation.

Next, the modulator 9 will be described with reference to FIGS. 2 (a) and 2 (b). 2 (a) and 2 (b) have the same oscillator circuit. This clock oscillator is a ceramic oscillator X
A circuit using a C-MOS Q ₂ inverter IC and a normal CPU
Widely used as a clock oscillator. The oscillation frequency of this clock oscillator is determined by the ceramic oscillator X, but can be changed by the capacitors C ₂ and C ₃ . The modulator 9 shown in FIG. 2A has a resistor R ₁ and a capacitor C from the modulation signal input terminal INPUT.
_The power supply V _CC 5V is connected to the connection point of the voltage divided by the resistors R ₃ and R ₂ via ₄ and the variable capacitance diode VC and the capacitor C ₁ whose other end is grounded, and the other end of the capacitor C ₁ is It is connected to the input side of the capacitor C ₂ and C-MOS Q ₂ . With the above configuration, the capacitance of the variable capacitance diode VC and the capacitance of the capacitor C _{1 connected} in series are added in parallel to the capacitor C ₂ at a voltage according to the modulation signal. Therefore, the oscillation frequency of the clock oscillator is modulated according to the change of the variable capacitance diode.

[0013] FIG. 2 (b) to the modulator is connected to the base of the modulation signal resistor R ₁ has one end grounded from the input terminal INPOT through the resistor R ₁ and a grounded emitter switching transistor Q _1. This collector is connected from a power source V _CC 5V through a resistor R _3, and the collector is a capacitor C ₁
It is configured to be connected to the capacitor C ₂ via. When a modulation signal is input from the modulation signal input terminal INPUT, the switching transistor Q ₁ becomes conductive, the capacitor C ₁ is connected in parallel with the capacitor C _2, and the oscillation frequency of the clock oscillator is modulated.

When the oscillating frequency of the clock oscillator is modulated by the receiving circuit of FIG. 1, the 145 MHz interference signal 10 which is the 725th harmonic of this clock is also frequency-modulated. In the same way, all harmonics are also modulated and get into the reception frequency band of the amateur radio 7
The harmonics from the 20th to 730 hours are also modulated. Here, when the clock oscillator is modulated such that the modulation frequency is 20 kHz and the occupied bandwidth is 200 kHz, the interference signal has sidebands every 20 kHz and spreads the interference signal 10 over about 200 kHz.
According to the well-known frequency modulation theory, when this frequency component of a sine wave signal is modulated, the carrier at the original frequency produces countless sidebands in the modulation frequency interval, and the individual signal strengths of this carrier and sidebands are generated. Is obtained by the Bessel function of the first kind, and it is known that the signal strength is always lower than the original sine wave signal.

FIG. 5 is a chart comparing harmonics.
3A shows harmonics generated from the basic circuit of the receiver shown in FIG. mf is a harmonic in the reception interference area.
2B shows a signal distribution which is modulated by the modulation signal 12a and spread in FIG. 1, and the clock signal f _O is the circuit of FIG. 2A or 2B when there is no modulation signal. Is the frequency of. That is, it is for n = 0 when mf ± (o to n) d and the modulation frequency is dkHz. the dkHz interval for each harmonic of f _o are shown ± n pieces of modulated spread signal. In the diagram (C), the squelch signal of the receiving circuit is taken out from the noise amplifier 11 and supplied to the modulator 9 as the modulation signal 11a to modulate the oscillation frequency of the clock oscillator. In this case, the modulation frequency is not constant and freely changes between 0 kHz and dkHz due to noise. Therefore, the modulated signal does not appear at a fixed frequency position like the converted signal of FIG. (B) like mf ± (0-n) (0-d), but the frequency conversion position is fluidly changed according to the converted signal. It is a change that has the effect of lowering the interference level at the same position.

As described above, by converting the oscillation frequency of the clock oscillator to spread the harmonics, it is possible to maintain the receiving state with higher sensitivity. That is, conventionally M
Although the receiving sensitivity was about AX-10 dB, it was nominally -12.
There is an effect that it is possible to receive up to dB, substantially -20 dB. In an actual circuit, a shield or the like is used, but it is indispensable for coping with leakage of a transmission signal at the time of transmission.

[0017]

By simply adding a modulator to the clock oscillator provided in the control circuit in the wireless communication device according to the present invention,
Since it is a method of diffusing harmonics and lowering the harmonic level by performing frequency modulation within the operable range of the CPU,
The manufacturing cost is reduced, and the effect of enabling weight reduction and size reduction is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a receiver circuit of the present invention.

2A and 2B are circuit diagrams of a first embodiment in which a modulator is connected to a clock oscillator, and FIG. 2B is a circuit diagram of another embodiment.

FIG. 3 is a block diagram of a basic configuration of a receiving circuit.

FIG. 4 is a block diagram of a conventional receiver circuit.

FIG. 5 is a comparative distribution diagram of harmonic signals.

[Explanation of symbols]

 1 Antenna 2 Reception Circuit 3 Local Oscillator 4 Control Circuit 5 Control Signal Line 6 Power Supply Line 7 Shielding 8 Decoupling 9 Modulator 10 Interfering Signal 11 Noise Amplifier 12 Oscillator

Claims (2)

[Claims] 1. In an oscillator provided in a wireless communication device, a high-order harmonic generated at the same time as an oscillation frequency of a clock oscillator such as a CPU control circuit that is not directly involved in a reception operation enters a reception circuit to prevent reception interference. In the mitigation method, a modulator that modulates an oscillation frequency is connected to the clock oscillator, and a modulation signal that performs frequency modulation within a range that does not affect the CPU operation even if a clock signal changes is supplied to the modulator. The oscillation frequency of the clock oscillator is frequency-modulated, and each harmonic generated at the same time as the oscillation frequency is spread to the modulated signal and the harmonic frequency modulated for each harmonic of the modulated signal, and inversely proportional to the frequency spread. A method of mitigating reception interference, characterized in that the harmonic level is reduced to reduce reception interference. 2. A noise amplifier output for generating a squelch signal of a receiving circuit is supplied as a modulation signal as the modulation signal to be supplied to the modulator of claim 1, and the oscillation frequency of the clock oscillator is modulated. 2. The reception interference mitigation according to claim 1, wherein the frequency-spread harmonic changes the harmonic frequency according to the frequency and the signal level of the modulation signal that change irregularly to reduce the average value of the harmonic level. Method.