JPH0590912A - Setup and hold time correcting device - Google Patents

Abstract

PURPOSE:To obtain a setup and hold time correcting device in which timing adjustment between an inputted data signal and a clock signal is implemented quickly and smoothly. CONSTITUTION:In the setup and hold time correcting device provided with setup and hold time correction circuit provided on the input stage of a flip-flop 200 and adjusting a timing between a data signal and a clock signal inputted to the flip-flop 200, the setup and hold time correction circuit 100 is provided with a clock delay output function delaying and outputting the rise of the clock signal by a prescribed time with respect to the data signal and with a clock signal rise correcting function setting the falling timing of the data signal relatively after the lapse of the prescribed time after the rise of the clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a setup and hold time correction circuit, and more particularly to a setup and hold time correction circuit between a data signal and a clock signal in a flip-flop inside an LSI.

[0002]

2. Description of the Related Art Generally, a flip-flop operates correctly unless a time difference between a rising time of a clock signal input to a clock terminal and a time when data input to a data terminal changes, that is, a setup time or a hold time is satisfied. Can not do it.

Conventionally, as shown in FIG. 3, data and clock signals from other gates are directly input to the data terminal and clock terminal of the flip-flop. Therefore, as shown in the timing chart of FIG. 4, when the data changes near the rising edge of the clock signal,
The verification of whether the setup time or the hold time is satisfied is performed by the timing simulation, and if not satisfied, the simulation result shows the test pattern number, the gate name, and the rising edge of the clock signal. And the time difference of data change was displayed.

[0004]

However, in the above-mentioned conventional example, there is a flip-flop which causes a problem by verifying the setup and hold time between the data and the clock signal by the timing simulation and checking the simulation result. In this case, the timing correction between the data and the clock signal input thereto is manually corrected by reviewing the circuit configuration in front of the flip-flop, so that the timing is defective due to the large scale and complexity of the LSI. The number of flip-flops in which the problem occurs also increases, and it takes a very long time to check the simulation result and modify the circuits in front of each of those flip-flops, which delays the development.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a setup and hold time correction circuit which can improve the inconvenience of the conventional example and can easily and quickly correct the timing between input data and a clock signal. To provide.

[0006]

A setup and hold time correction circuit provided with an input stage of a flip flop and provided with a setup and hold time correction circuit for adjusting timings of a data signal and a clock signal input to the flip flop. In the device, the setup and hold time correction circuit delays the rising edge of the clock signal with respect to the data signal by a certain time and outputs the delayed signal, and the falling timing of the data signal relative to the rising edge of the clock signal. It is configured to have a clock signal rising correction function that is set after the elapse of a predetermined time. This aims to achieve the above-mentioned object.

[0007]

(1) Correction of setup time: When data rises from "low level" to "high level", the Q output of the first flip-flop and the Q output of the second flip-flop remain "low level". Is. The output of the first OR gate falls from "high level" to "low level". The output of the second OR gate rises from "low level" to "high level". The output of the AND gate remains "low level" because the output of the first OR gate and the output of the second OR gate are opposite. The output of the hold time correction buffer is "high level" with a delay of the hold time.
Stand up. The output from the first data selector is AN
Since the output of the D gate remains "low level", the data itself is selected and rises to "high level". Second
In the data selector, since the output of the AND gate remains "low level", the output of the setup time correction buffer is selected, and the clock signal delayed by the setup time is output. Then, since the data itself is input to the data terminal of the third flip-flop and the clock signal delayed by the setup time is input to the clock terminal, the setup time becomes long. That is, the data and the clock signal are input to the data terminal and the clock terminal of the conventional flip-flop in a state where the setup time is sufficiently corrected and corrected.

(2) Hold time correction: When the data further falls from "high level" to "low level",
The Q output of the first flip-flop remains "low level". The Q output of the second flip-flop rises from "low level" to "high level". The output of the first OR gate rises from "low level" to "high level". The output of the second OR gate remains "high level". The output of the AND gate rises from "low level" to "high level" because the output of the first OR gate is the same as the output of the second OR gate. The output of the hold time correction buffer falls to "low level" after a delay of the hold time.

The output from the first data selector is AND
Since the output of the gate is "high level", the output of the hold time correction buffer is selected and falls to "low level" at the same time as the output of the hold time correction buffer. Second
In the data selector, since the output of the AND gate is "high level", the clock signal is selected from the clock signal input terminal, and the clock signal is output as it is without delay. Then, the data delayed by the hold time is input to the data terminal of the third flip-flop, and the clock signal is directly input to the clock terminal, so that the hold time becomes long. That is, the data and the clock signal are input to the data terminal and the clock terminal of the conventional flip-flop in a state where the hold time is corrected to a timing that is sufficiently satisfied.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

In FIG. 1, reference numeral 100 designates a data input terminal DAT, a clock signal input terminal CLK, and a reset signal input terminal RST as inputs, and sets up between the data and the clock signal input to the third flip-flop 200. 7 shows a setup and hold time correction circuit for correcting time and hold time.

The setup and hold time correction circuit 100 uses the data input from the data input terminal DAT as a clock terminal input and a clock signal input terminal C.
A first flip-flop 1 having a clock signal input from LK as a data terminal input and a reset signal input from a reset signal input terminal RST as a reset terminal input
01, data inputted from the data input terminal DAT as a clock terminal input through the inverter 103, a clock signal inputted from the clock signal input terminal CLK as a data terminal input, and a reset signal inputted from the reset signal input terminal RST. The second flip-flop 102 and the first flip-flop 10 which are input to the reset terminal
The first OR gate 104 that takes the logical sum of the Q output of 1 and the output of the inverter 103, and the second flip-flop 1
02 and the data input from the data input terminal DAT, the second OR gate 105, and the AND gate that takes the logical product of the output of the first OR gate 104 and the output of the second OR gate 105. 106 and the data input terminal D
Data input from the AT is input to the A terminal, data input from the data input terminal DAT is delayed by the hold time via the hold time correction buffer 107 and is input to the B terminal, and the output of the AND gate 106 is used as the select terminal S.
The clock signal input from the first data selector 109 to be input and the clock signal input terminal CLK is delayed by the setup time via the setup time correction buffer 108 and is input as the A terminal input from the clock signal input terminal CLK. A clock signal is input to terminal B
The second data selector 110 has the output of the ND gate 106 as the input of the select terminal S.

The output from the first data selector 109 is connected to the data terminal input of the third flip-flop 200, and the output from the second data selector 110 is the clock terminal of the third flip-flop 200. Connected to input.

In addition, the first data selector 109 and the second data selector 109
In the data selector 110, the A terminal input is selected when the select terminal S input is "low level", and the B terminal input is selected when the select terminal S input is "high level".

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

Initialization processing: reset signal input terminal RS
The reset signal 20 is input from T, and the Q outputs of the first flip-flop 101, the second flip-flop 102, and the third flip-flop 200 are set to “low level”.

Data is input from the data input terminal DAT and a clock signal is input from the clock signal input terminal CLK. The data at this time is assumed to be "low level".
The Q output of the first flip-flop 101 and the Q output of the second flip-flop 102 remain "low level". Further, the output of the first OR gate 104 is “high level” and the output of the second OR gate 105 is “low level”, so the output of the AND gate 106 is “low level”. Then, the hold time correction buffer 10
The output of 7 is "low level" because the data remains "low level", and the setup time correction buffer 10
The output of 8 is a clock signal delayed by the setup time. Further, since the output of the AND gate 106 is "low level", the A terminal input is selected by the first data selector 109 and the output is the data from the data input terminal DAT, that is, "low level". Second data selector 11
At 0, since the output of the AND gate 106 is "low level", the A terminal input is selected and the output of the setup time correction buffer 108, that is, the clock signal delayed by the setup time is output. Therefore, since the input data is "low level" in the third flip-flop 200,
The Q output is "low level".

Correction of setup time: Next, when the data rises from "low level" to "high level",
The setup time correction process is performed by the operation described below. The Q output of the first flip-flop 101 and the Q output of the second flip-flop 102 remain "low level", but the output of the first OR gate 104 rises from "high level" to "low level". Go down. The output of the second OR gate 105 rises from "low level" to "high level". Therefore, the output of the AND gate 106 remains "low level" because the output of the first OR gate 104 and the output of the second OR gate 105 are opposite.

Then, the hold time correction buffer 10
The output of 7 rises to "high level" with a delay of the hold time. The output from the first data selector 109 is AN
Since the output of the D gate 106 remains "low level",
The A terminal input, that is, the data itself is selected and rises to "high level". In the second data selector 110, since the output of the AND gate 106 remains "low level", the A terminal input, that is, the output of the setup time correction buffer 108 is selected, and the clock signal delayed by the setup time is output. Therefore, since the data itself is input to the data terminal of the third flip-flop 200 and the clock signal delayed by the setup time is input to the clock terminal, the setup time becomes long. That is, the data and the clock signal are input to the data terminal and the clock terminal of the conventional flip-flop 200 in a state in which the setup time is sufficiently corrected and corrected.

Correction of hold time: Further, when the data falls from "high level" to "low level", the hold time is corrected by the operation described below. First
The Q output of the second flip-flop 101 remains "low level", but the Q output of the second flip-flop 102 rises from "low level" to "high level". The output of the first OR gate 104 rises from "low level" to "high level". The output of the second OR gate 105 remains “high level”. Therefore, the output of the AND gate 106 and the output of the first OR gate 104 and the second
The output of OR gate 105 is the same, so "low level"
To rise to "high level". The output of the hold time correction buffer 107 falls to "low level" after a delay of the hold time.

The output from the first data selector 109 is B because the output of the AND gate 106 is "high level".
The terminal input, that is, the output of the hold time correction buffer 107 is selected and falls to "low level" at the same time as the output of the hold time correction buffer 107. In the second data selector 110, since the output of the AND gate 106 is "high level", the clock signal from the B terminal input, that is, the clock signal input terminal CLK is selected and the clock signal is output as it is without delay. Therefore, the data delayed by the hold time is input to the data terminal of the third flip-flop 200, and the clock signal is directly input to the clock terminal, so that the hold time becomes long. That is, the data and the clock signal are input to the data terminal and the clock terminal of the conventional flip-flop 200 in a state where the hold time is corrected to a timing that is sufficiently satisfied.

[0022]

Since the present invention is constructed and functions as described above, according to the present invention, the setup time and the hold time between the data and the clock signal can be easily corrected. It is possible to provide an unprecedented excellent setup and hold time correction circuit that can reduce the number of steps and shorten the development period and delivery time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of output signals of each gate of FIG.

FIG. 3 is a conventional flip-flop diagram.

FIG. 4 is a conventional input timing chart between data and clock signals.

[Explanation of symbols]

 100 setup and hold time correction circuit 101 first flip-flop 102 second flip-flop 103 inverter 104 first OR gate 105 second OR gate 106 AND gate 107 hold time correction buffer 108 setup time correction buffer 109 1 data selector 110 2nd data selector 200 3rd flip-flop

Claims (2)

[Claims] 1. The input stage of a flip-flop is equipped with,
In a setup and hold time correction device including a setup and hold time correction circuit that adjusts the timing of a data signal and a clock signal input to the flip-flop, the setup and hold time correction circuit includes a clock signal for the data signal. Is provided with a clock delay output function of delaying the rising edge of the clock signal for a fixed time and outputting the falling edge of the data signal, and a clock signal rising edge correction function of setting the falling edge timing of the data signal relatively after a predetermined time has elapsed after the rising edge of the clock signal A setup and hold time correction device characterized in that 2. Data input from a data input terminal is used as a clock terminal input, a clock signal input from a clock signal input terminal is used as a data terminal input, and a reset signal input from a reset signal input terminal is used as a reset terminal input. The data input from the first flip-flop and the data input terminal are input to the clock terminal via the inverter, and the clock signal input from the clock signal input terminal is input to the reset signal input terminal. A second flip-flop that receives the reset signal as a reset terminal input, and a first OR that takes the logical sum of the Q output of the first flip-flop and the output of the inverter
A gate, a second OR gate that ORs the data input from the second flip-flop and the data input terminal, and the logical product of the output of the first OR gate and the output of the second OR gate. AND gate, and the data input from the data input terminal is input to the A terminal, and the data input from the data input terminal is delayed by the hold time via the hold time correction buffer to be input to the B terminal to output the AND gate. Select pin input. The clock signal input from the first data selector and the clock signal input terminal is delayed by the setup time through the setup time correction buffer to be the A terminal input, and the clock signal input from the clock signal input terminal is input to the B terminal. Toshi A
The output of the ND gate is used as the select terminal input. A setup and hold time correction circuit comprising a second data selector.