JPH0590897A - Oversampling filter circuit - Google Patents

Abstract

PURPOSE:To make it possible to enhance the oversampling processing speed by making the operating speed of each adder, multiplier, and so on constituting the digital filter circuit equal to input data speed. CONSTITUTION:A sample number converting circuit 1 in the over-sampling circuit carries out sample number conversion on input data, while the interpolation points that is obtained by the sample number conversion processing are provided with temporary reference value 0. Further, the data processing section at the even side of the digital filter circuit and the data processing section at the odd side thereof carry out the convolution arithmetic operation on each data obtained from a circuit 1, the DC correction is carried out on resulatant data using the correcting value corresponding to the essential reference value, and the output from the data processing section at the even side and the output from the data processing section at the odd side are alternately selected and output. With this constitution, the operation speed of each adder and multiplier in the data processing section at the even side and the operation speed of each adder and multiplier in the data processing section at the odd side are made equal to the input data speed, thereby carrying out the oversampling processing at doubled high speed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to oversampling filter circuits.

[0002]

2. Description of the Related Art In an oversampling filter circuit that multiplies the sampling frequency of input data by n times, it is considered that there are "n-1" sample points having a constant value between the actual input sample points. Oversampling processing by the method of obtaining the sampling frequency n times as high as the input data by filtering the input data with the conversion speed n times by the low-pass digital filter whose passband is "π / n" Are doing.

FIG. 6 is a block diagram showing an example of oversampling processing by such a method. As shown in this figure, in this oversampling circuit, input data is supplied to a sample number conversion circuit 101, the sample number conversion circuit 101 performs sample number conversion to insert interpolation points between input sample points, and After the reference value C is given to the point, the digital filter circuit 102
The output data is obtained by band limiting the input data by. In this case, when the input data is a video signal and the double oversampling is performed, the reference level of the input data becomes the pedestal level, so that the pedestal level is given to the interpolation point at the first sampling number conversion.

The digital filter circuit 102 used in such oversampling processing has a clock signal having a frequency twice as high as the frequency of the input data input to the sample number conversion circuit 101 as shown in FIG. A plurality of registers 103 that take in data and shift each time fs ₂ is supplied, and these registers 103
Of a plurality of adders 106 that selectively add the data output from the respective taps, and the coefficients h _{0 to} h _n preset for the respective data obtained by the addition operation of the respective adders 106. Multiple multipliers 108 multiplying either
And a plurality of adders 110 for adding the data output from each of the multipliers 108, and the input data is added each time the clock signal fs ₂ having a frequency n times the input data rate is supplied. While importing, shift processing, addition processing, coefficient multiplication processing,
The input data is processed according to the digital filter characteristic shown in FIG. 8 by performing addition processing and the processing result is output as output data. As a result, when the input data input to the sample number conversion circuit 101 has the characteristic shown in FIG. 9A, the output data having the characteristic shown in FIG. 9B is output.

[0005]

However, in the digital filter circuit 102 used in the above-described conventional oversampling processing, when performing n-times oversampling processing, a clock having a frequency n times the input data rate is used. Each register 1 using signal fs ₂
03, each adder 106, 110, and each multiplier 108 must be operated at a frequency n times as high as the input data rate.
0, the multiple of oversampling is determined by the operating speed of each multiplier 108, and there is a problem that it is difficult to operate at high speed.

In view of the above circumstances, the present invention can carry out oversampling processing while making the operating speed of each adder, each multiplier and the like which compose the digital filter circuit the same as the input data speed of the input data. An object of the present invention is to provide an oversampling filter circuit that can achieve high speed of oversampling processing.

[0007]

In order to achieve the above object, an oversampling filter circuit according to the present invention performs sample number conversion on input data, and "0" as a temporary reference value for an interpolation point. And a DC correction based on a correction value corresponding to the original reference value for the data obtained by this convolution operation by performing a convolution operation based on the data obtained by this sample number conversion section. It is characterized by comprising a plurality of data processing units for performing the above, and a selection unit for sequentially selecting each data obtained by each of these data processing units to generate output data.

[0008]

In the above structure, after the sample number conversion unit performs the sample number conversion on the input data and "0" is given as a provisional reference value to the interpolation point obtained by this sample number conversion processing. A convolution operation is performed by each data processing unit based on the data obtained by the sample number conversion unit, and a DC correction based on a correction value corresponding to the original reference value is performed on the data obtained by this operation processing. Then, the selection section sequentially selects the respective data obtained by the respective data processing sections to generate output data.

[0009]

First, the basic principle of the present invention will be described prior to the detailed description of the embodiments. The present invention is basically based on a commonly used oversampling processing method, for example, the processing method shown in FIG.
When "0" is always given instead of giving "0", the multiplication result is always "0" even if this value is multiplied by the coefficient hi, which does not contribute to the operation result. By utilizing the fact that only the even taps at some times and only the odd taps at some times contribute to the calculation, the correction values corresponding to the original reference value C are applied to the data obtained at these even taps and odd taps. By adding D ₁ (or the correction value D ₂ ) and alternately selecting the calculation result on the even tap side and the calculation result on the odd tap side, a double oversampling process with respect to the input data rate is performed. You get the same output data as you did.

FIG. 1 is a block diagram showing an embodiment of a circuit for performing a linear phase double oversampling process in the oversampling filter circuit according to the present invention based on such a basic principle.

The oversampling filter circuit shown in this figure comprises a sample number conversion circuit 1 and a digital filter circuit 2, and is obtained by first converting the sample number of input data and then performing the sample number conversion process. After giving "0" as a temporary reference value to each interpolation point,
The digital filter circuit 2 performs a DC correction based on the correction value D1 (or the correction value D2) corresponding to the original reference value C while band limiting the data output from the sample number conversion circuit 1. Get output data.

The sample number conversion circuit 1 performs sample number conversion processing on input data to insert interpolation points between input sample points, and always gives "0" as a temporary reference value for each interpolation point. The data obtained by the processing is supplied to the digital filter circuit 2.

As shown in FIG. 2, the digital filter circuit 2 comprises a register section 5, an even side data processing section 6, an odd side data processing section 7, and a multiplexer circuit 8.
The data output from the sample number conversion circuit 1 is subjected to direct current correction on the data on the even tap side and the data on the odd tap side while band limiting is performed, and the data thus obtained is alternately selected. And output data is generated.

The register unit 5 comprises a plurality of registers 10 connected in series, and each time a clock signal having the same frequency as the input data speed of the input data input to the sample number conversion circuit 1 is supplied. , The data output from the sample number conversion circuit 1 is shifted while the data output from the sample number conversion circuit 1 is shifted and supplied to the even number side data processing unit 6, and the data obtained in each odd number tap is odd numbered. It is supplied to the side data processing unit 7.

The even-numbered side data processing unit 6 includes the registers 1
A plurality of even-side adders 12 that select and add two pieces of data obtained at the even-numbered taps of 0, and preset for each data obtained by the addition operation of each of these even-side adders 12 A plurality of even side multipliers 13 for multiplying the respective coefficients h ₁ , h ₃ , h ₅ , h ₇ and the even side multipliers 1
3 is obtained by adding the data obtained by the multiplication operation of FIG.
Corresponding to the original reference value C for a plurality of even-numbered-side adders 14 that generate impulse response data as shown in (a) and one data obtained by the addition operation of these even-numbered-side adders 14. Even side adder ₁ for adding correction value D 1
5 and performs an addition process, a coefficient multiplication process, and the like on a plurality of even-numbered data output from the register unit 5, and then applies an original reference value C to the data obtained by these processes. The correction value D ₁ corresponding to is added to perform DC correction, and the corrected data is supplied to the multiplexer circuit 8 as an impulse response at the interpolation point. In this case, since the correction value D ₁ is the response of the even number tap to the fixed value C, it is always a constant value as shown in the following equation.

[Equation 1]

The odd-numbered data processing unit 7 selects a plurality of two data obtained at the odd-numbered taps of each register 10 and adds them, and the odd-numbered adders 16 of the odd-numbered adders 16. Coefficients h ₀ , h ₂ , h ₄ , h ₆ , h ₈ preset for each data obtained by the addition operation
A plurality of odd-number side multipliers 17 and a plurality of odd-side multipliers 17 that add the respective data obtained by the multiplication operations of the odd-number side multipliers 17 to generate the impulse response data shown in FIG. The adder 18 and the odd-numbered adder 19 for adding the correction value D ₂ corresponding to the original reference value C to one data obtained by the addition operation of each odd-numbered adder 18 are provided. , The correction value D corresponding to the original reference value C is applied to the data obtained by the addition processing and the coefficient multiplication processing on the plurality of odd-numbered data output from the register unit 5. ₂ is added and this is DC corrected, and the corrected data is supplied to the multiplexer circuit 8 as an impulse response at the input sampling point. In this case, since the correction value D ₂ is the response of the odd number tap to the fixed value C, it is always a constant value as shown in the following equation.

[Equation 2] In this case, the correction value D ₂ is equal to the DC correction value D _{1 in} the normal oversampling process.

The multiplexer circuit 8 has an input data rate of 2 of the input data input to the sample number conversion circuit 1.
Each time a clock signal having a doubled frequency is supplied, the data output from the even-numbered side data processing unit 6 and the data output from the odd-numbered side data processing unit 7 are alternately selected to select the data shown in FIG. The data shown in is generated and is output as the output data that has been subjected to oversampling processing.

As described above, in this embodiment, when "0" is always given to the interpolation point instead of giving the reference level C, the multiplication result is always "0" even if this value is multiplied by the coefficient ki. , Even if only even-numbered taps and at other times only odd-numbered taps contribute to the calculation by utilizing the fact that they do not contribute to the calculation result, these even-numbered taps and odd-numbered taps are used. The correction value D ₁ (or the correction value D ₂ ) corresponding to the original reference value C is added to the obtained data, and the calculation result on the even tap side and the calculation result on the odd tap side are alternately set. By selecting the output data, the same output data as when the oversampling process that is twice the input data speed is performed is obtained. Therefore, the register unit 5 forming the digital filter circuit 2 can be obtained. It is possible to perform oversampling processing while making the operating speeds of the even-numbered side data processing section 6 and the odd-sided data processing section 7 the same as the input data rate of the input data. You can

FIG. 4 is a block diagram showing an embodiment of a circuit for performing n times oversampling processing in the oversampling filter circuit according to the present invention. The oversampling filter circuit shown in this figure includes a sample number conversion circuit 20 and a digital filter circuit 21, and first performs sample number conversion on the input data and then performs each interpolation obtained by this sample number conversion processing. after giving the "0" as a reference value for tentative point, the output data by performing direct current corrected based on the correction value D ₁ to D _n corresponding to the original reference value C while subjected to band limiting by the digital filter circuit 21 To get

The sample number conversion circuit 20 performs sample number conversion processing on the input data to insert interpolation points between input sample points, and always gives "0" as a temporary reference value for each interpolation point. The data obtained by the processing is supplied to the digital filter circuit 21.

As shown in FIG. 5, the digital filter circuit 21 is provided with a register section 22, a plurality of data processing sections 23, and a multiplexer circuit 24. The digital filter circuit 21 has a bandwidth for the data output from the sample number conversion circuit 20. DC data is corrected and output data is generated while limiting.

The register unit 22 is provided with a plurality of registers 25 connected in series, each time a clock signal having the same frequency as the input data speed of the input data input to the sample number conversion circuit 20 is supplied. , The data output from the sample number conversion circuit 20 is taken in and shifted, and the data obtained at each tap is supplied to each data processing unit 23.

[0023] Each respective data processing unit 23, the plurality of multipliers 26 for multiplying the coefficients h _e ~h _{e-n + 1} that is set in advance for the resultant data to each tap of each register 25
And a plurality of adders 27 for adding the data obtained by the multiplication operation of each of the multipliers 26, and a correction value D corresponding to the reference value C for one data obtained by each of the adders 27. ₁ (or a corresponding value among the correction values D ₂ to D _m ) is added to correct the data with a direct current, and an adder 28 is provided. Are subjected to coefficient multiplication processing, addition processing, etc., and then the correction value D ₁ (or correction value D ₂ to correction value D _m corresponding to the original reference value C is applied to the data obtained by these processing. (Corresponding value) is added to correct the DC, and the corrected data is supplied to the multiplexer circuit 24.

The multiplexer circuit 24 supplies a clock signal having a frequency n times the input data rate of the input data input to the sample number conversion circuit 20, each time the clock signal is supplied.
The data output from each of the data processing units 23 is sequentially
The data obtained by this selection operation is cyclically selected and output as output data that has been oversampled.

As described above, in this embodiment, instead of giving the reference level C to each interpolation point, "0" is always given, and the original reference value C in each data processing unit 23 is given.
Since the correction values D ₁ to D _m corresponding to are added and selected, the same output data as when the oversampling process of n times the input data speed is performed is obtained. , Digital filter circuit 21
While making the operating speed of the register unit 22 and each data processing unit 23 constituting the same as the input data speed of input data,
The oversampling process can be performed, and the oversampling process can be speeded up.

In each of the embodiments described above, the correction values D ₁ and D ₂ (or the correction values D ₁ and D ₂ (or the data processing units 23) and the odd-side data processing units 6 and 7 (or the respective data processing units 23) are individually calculated.
The correction values D _{1 to} D _n ) are added to correct the impulse response to the correction interpoint and the impulse response to the input sampling point, but such correction is performed by the multiplexer circuit 8 (or the multiplexer circuit 24). You may do it collectively. However, in this case, the output data rate of the multiplexer circuits 8 and 24 is 2 times the input data.
Since it is doubled (or n times), it is necessary to double the calculation speed (or n times).

Further, in each of the above-described embodiments, the present invention has been described by exemplifying the case where the direct current correction is required. However, when the direct current correction amount becomes "0" like the voice signal, such direct current correction is performed. The processing may be omitted.

[0028]

As described above, according to the present invention, the oversampling process is performed while the operating speed of each adder, each multiplier, and the like that composes the digital filter circuit is made the same as the input data speed of the input data. Therefore, the oversampling process can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a circuit that performs a linear phase double oversampling process in an oversampling filter circuit according to the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration example of the digital filter circuit shown in FIG.

FIG. 3 is a schematic diagram showing an example of filter characteristics of the digital filter circuit shown in FIG.

FIG. 4 is a block diagram showing an embodiment of a circuit that performs n times oversampling processing in the oversampling filter circuit according to the present invention.

5 is a circuit diagram showing a detailed configuration example of the digital filter circuit shown in FIG.

FIG. 6 is a block diagram for explaining an example of conventionally known oversampling processing.

7 is a circuit diagram showing a detailed configuration example of the digital filter circuit shown in FIG.

8 is a schematic diagram showing an example of filter characteristics of the digital filter circuit shown in FIG.

9 is a schematic diagram showing frequency characteristics of input data processed by the oversampling processing shown in FIG. 6 and frequency characteristics of output data.

[Explanation of symbols]

 1 sample number conversion circuit (sample number conversion unit) 2 digital filter circuit 5 register unit 6 data processing unit (even side data processing unit) 7 data processing unit (odd side data processing unit) 8 multiplexer circuit (selection unit)

Claims (1)

[Claims] 1. A sample number conversion unit that performs sample number conversion on input data and gives "0" as a temporary reference value to an interpolation point, and based on the data obtained by this sample number conversion unit. A plurality of data processing units that perform a convolution calculation and perform DC correction on the data obtained by this calculation processing based on the correction value corresponding to the original reference value, and each data obtained by these data processing units An oversampling filter circuit comprising: a selection unit that sequentially selects and generates output data.