JPH0590529A - Manufacture of dynamic type random access memory - Google Patents
Manufacture of dynamic type random access memoryInfo
- Publication number
- JPH0590529A JPH0590529A JP3248656A JP24865691A JPH0590529A JP H0590529 A JPH0590529 A JP H0590529A JP 3248656 A JP3248656 A JP 3248656A JP 24865691 A JP24865691 A JP 24865691A JP H0590529 A JPH0590529 A JP H0590529A
- Authority
- JP
- Japan
- Prior art keywords
- charge storage
- silicon film
- cell
- mixed solution
- poly silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000011259 mixed solution Substances 0.000 claims abstract description 7
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 claims 2
- 239000007788 liquid Substances 0.000 claims 2
- 238000003860 storage Methods 0.000 abstract description 15
- 238000004140 cleaning Methods 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 230000002159 abnormal effect Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、スタック型キャパシタ
を用いたダイナミック型ランダムアクセスメモリ（ＤＲ
ＡＭ）の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (DR) using a stack type capacitor.
AM).
【０００２】[0002]
【従来の技術】スタック型キャパシタを用いたＤＲＡＭ
メモリセルの従来の製造方法は、図２に示される様に、
通常のＭＯＳトランジスタと同構造となる、ワード線を
構成するゲート電極４、ビット線と接続するソース・ド
レイン（以下ＳＤと記す）の一方の拡散層５，他方の電
荷蓄積側ＳＤ部６を有する伝達トランジスタを形成した
後、蓄積側ＳＤ部６上の要領コンタクト孔７を介してキ
ャパシタの電荷蓄積電極８を形成する。すなわちポリシ
リコン膜をＣＶＤ法により形成し、パターニングするの
であるが、従来はこのパターニングされたポリシリコン
膜（電荷蓄積電極）を、純水を用いて洗浄し、表面を滑
らかにしている。この後、熱酸化及び窒素処理によりポ
リシリコン膜表面に窒化シリコン膜９を容量絶縁膜とし
て形成した後、固定電極となるキャパシタの対向電極１
０をポリシリコン膜のパターニングにより形成する。次
に、ＢＰＳＧよりなる層間絶縁膜１１を形成し、ビット
線を接続するＳＤ部５上にコンタクト孔１２を開口した
のち、ビット線用配線１３を形成する。DRAM using a stack type capacitor
A conventional method of manufacturing a memory cell is as shown in FIG.
It has a gate electrode 4 forming a word line, a diffusion layer 5 on one side of a source / drain (hereinafter referred to as SD) connected to a bit line 5, and an SD section 6 on the other charge storage side, which has the same structure as a normal MOS transistor. After the transfer transistor is formed, the charge storage electrode 8 of the capacitor is formed through the contact hole 7 on the storage side SD section 6. That is, a polysilicon film is formed by the CVD method and patterned, but conventionally, the patterned polysilicon film (charge storage electrode) is washed with pure water to smooth the surface. After that, a silicon nitride film 9 is formed as a capacitive insulating film on the surface of the polysilicon film by thermal oxidation and nitrogen treatment, and then the counter electrode 1 of the capacitor which becomes the fixed electrode.
0 is formed by patterning the polysilicon film. Next, the interlayer insulating film 11 made of BPSG is formed, the contact hole 12 is opened on the SD portion 5 connecting the bit line, and then the bit line wiring 13 is formed.
【０００３】[0003]
【発明が解決しようとする課題】ＤＡＲＭの大容量化高
集積化にともない、セル面積も益々縮小化が進んできて
おり、上述したスタック型キャパシタではセル容量ＣS
の確保が困難になってきている。そのため、各研究機関
においては、セル容量増大のための各種のスタック構造
が提案されている。例えば、ポリシリコン膜で構成され
た電荷蓄積電極の表面を凹凸状にして表面積をかせぎ、
容量値が従来の平坦型容量の２倍にする技術が、ソリッ
ド・ステート・デバイシス・アンド・マテリアルズ誌
（ＳＳＤＭ），１９９０年，第８７３頁−第８７６頁に
発表されている。この技術はアモルファスシリコンから
ポリシリコンへ転移する温度（約５５０℃）でポリシコ
ン膜を形成するのであるが、温度制限が厳しく、成長炉
管内温度分布のため、炉の中心部しか使用できず、量産
性に欠けるという問題点があった。The cell area is becoming smaller and smaller with the increase in capacity and integration of DARM, and in the above-mentioned stack type capacitor, the cell capacity C S
Is becoming difficult to secure. Therefore, various research institutions have proposed various stack structures for increasing the cell capacity. For example, the surface of the charge storage electrode composed of a polysilicon film is made uneven to increase the surface area,
A technique for doubling the capacitance value of the conventional flat type capacitor is disclosed in Solid State Devices and Materials (SSDM), 1990, pp. 873 to 876. This technology forms a polysilicon film at a temperature (about 550 ° C) at which amorphous silicon is transformed into polysilicon, but the temperature is severely limited and only the central part of the furnace can be used because of the temperature distribution inside the growth furnace tube. There was a problem of lack of sex.
【０００４】[0004]
【課題を解決するための手段】本発明のスタック型キャ
パシタを用いたダイナミック型ランダムアクセスメモリ
の製造方法は、伝達トランジスタを形成した半導体チッ
プの表面にポリシリコン膜を形成しパターニングして電
荷蓄積用電極を形成し、Ｎ−Ｈ基を含む混合液により前
記電荷蓄積用電極を洗浄し、容量絶縁膜を形成し、対向
電極を形成してスタック型キャパシタを形成する工程を
有するというものである。A method of manufacturing a dynamic random access memory using a stack type capacitor according to the present invention comprises a polysilicon film formed on the surface of a semiconductor chip on which a transfer transistor is formed and patterned to store a charge. The method includes forming an electrode, cleaning the charge storage electrode with a mixed solution containing an N—H group, forming a capacitive insulating film, and forming a counter electrode to form a stack type capacitor.
【０００５】[0005]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００６】図１は本発明によるスタック型キャパシタ
セルを使用したＤＲＡＭのメモリセルを示す半導体チッ
プの断面図である。FIG. 1 is a sectional view of a semiconductor chip showing a memory cell of a DRAM using a stack type capacitor cell according to the present invention.
【０００７】本発明のメモリセルは従来と同様なプロセ
スにてワード線となるゲート電極４、ビット線１３と接
続するＳＤ５、電荷蓄積側ＳＤ６よりなる伝達トランジ
スタを形成し、ＳＤ６上の容量コンタクト孔７を介し
て、電荷蓄積用電極８ａを形成するためのポリシリコン
膜９をＣＶＤ法により堆積する。次に、パターニングさ
れたポリシリコン膜をＮ−Ｈ基を含む物質の混合液、例
えばアンモニア混合液（ＮＨ3 ＯＨ＋Ｈ2 Ｏ2 ＋Ｈ
2 Ｏ）を使用して洗浄すると、ポリシリコン膜の結晶グ
レインが異常成長し、表面が凹凸状になる。その後の容
量絶縁膜１０ａを形成する工程以降は従来技術と同じで
ある。このようにすると、電荷蓄積用電極８ａの面積
は、平坦の場合の約２倍位まで増大し、セル面積を増大
させることなくセルキャパシタの容量ＣS の増大が実現
できる。In the memory cell of the present invention, a transfer transistor including a gate electrode 4 serving as a word line, an SD5 connected to the bit line 13, and a charge storage side SD6 is formed by a process similar to the conventional process, and a capacitance contact hole on SD6 is formed. Via 7, the polysilicon film 9 for forming the charge storage electrode 8a is deposited by the CVD method. Then, the patterned polysilicon film is mixed with a mixture of substances containing N—H groups, for example, a mixture of ammonia (NH 3 OH + H 2 O 2 + H).
When cleaning is performed using ( 2 O), the crystal grains of the polysilicon film grow abnormally and the surface becomes uneven. The subsequent processes after forming the capacitive insulating film 10a are the same as those in the conventional technique. By doing so, the area of the charge storage electrode 8a is increased to about twice as large as that in the case of being flat, and the capacitance C S of the cell capacitor can be increased without increasing the cell area.
【０００８】[0008]
【発明の効果】以上説明したように、本発明はＤＲＡＭ
のスタック型キャパシタセルを形成する際に、ポリシリ
コン膜のパターニング後の洗浄を従来の水洗よりＮ−Ｈ
基を含む混合液、例えばアンモニア混合液に変えるだけ
で電荷蓄積用電極の表面積を増大させることができるの
で、厳しい温度制御の必要な特殊なＣＶＤ装置を使用せ
ずに、高集積化に対応できるセルキャパシタ容量ＣS を
実現することができるという効果を有する。As described above, the present invention is a DRAM.
When forming the stacked type capacitor cell, the cleaning after patterning the polysilicon film is performed by NH instead of the conventional water cleaning.
Since the surface area of the charge storage electrode can be increased simply by changing to a mixed solution containing a group, for example, an ammonia mixed solution, it is possible to cope with high integration without using a special CVD apparatus that requires strict temperature control. It has an effect that the cell capacitor capacitance C S can be realized.
【図１】本発明の一実施例によるスタック型キャパシタ
を用いたメモリセルの断面図である。FIG. 1 is a cross-sectional view of a memory cell using a stack type capacitor according to an exemplary embodiment of the present invention.
【図２】従来のスタック型キャパシタを用いたメモリセ
ルの断面図である。FIG. 2 is a cross-sectional view of a memory cell using a conventional stack type capacitor.
１ Ｐ型半導体基板 ２−１ フィールド酸化膜 ２−２ 層間絶縁膜 ３ ゲート絶縁膜 ４ ゲート電極 ５，６ Ｎ型のソース・ドレイン（ＳＤ） ７ 容量用のコンタクト孔 ８，８ａ 電荷蓄積用電極 ９，９ａ 容量絶縁膜 １０，１０ａ 対向電極 １１ 層間絶縁膜 １２ ビット線用のコンタクト孔 １３ ビット線 DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2-1 Field oxide film 2-2 Interlayer insulating film 3 Gate insulating film 4 Gate electrode 5,6 N-type source / drain (SD) 7 Contact hole 8 for capacitance 8a Charge storage electrode 9 , 9a Capacitance insulating film 10, 10a Counter electrode 11 Interlayer insulating film 12 Contact hole for bit line 13 Bit line
Claims (2)
プの表面にポリシリコン膜を形成しパターニングして電
荷蓄積用電極を形成し、Ｎ−Ｈ基を含む混合液により前
記電荷蓄積用電極を洗浄し、容量絶縁膜を形成し、対向
電極を形成してスタック型キャパシタを形成する工程を
有すことを特徴とするダイナミック型ランダムアクセス
メモリの製造方法。1. A charge accumulation electrode is formed by forming and patterning a polysilicon film on the surface of a semiconductor chip having a transfer transistor formed thereon, and the charge accumulation electrode is washed with a mixed solution containing an N—H group, A method of manufacturing a dynamic random access memory, comprising a step of forming a capacitive insulating film and forming a counter electrode to form a stack type capacitor.
ア混合液（ＮＨ3 ＯＨ＋Ｈ2 Ｏ2 ＋Ｈ2 Ｏ）を使用する
請求項１記載のダイナミック型ランダムアクセスメモリ
の製造方法。2. The method for manufacturing a dynamic random access memory according to claim 1, wherein an ammonia mixed liquid (NH 3 OH + H 2 O 2 + H 2 O) is used as the mixed liquid containing N—H groups.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3248656A JPH0590529A (en) | 1991-09-27 | 1991-09-27 | Manufacture of dynamic type random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3248656A JPH0590529A (en) | 1991-09-27 | 1991-09-27 | Manufacture of dynamic type random access memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0590529A true JPH0590529A (en) | 1993-04-09 |
Family
ID=17181379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3248656A Pending JPH0590529A (en) | 1991-09-27 | 1991-09-27 | Manufacture of dynamic type random access memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0590529A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI898870B (en) * | 2024-07-19 | 2025-09-21 | 南亞科技股份有限公司 | Method of manufacturing a semiconductor device |
-
1991
- 1991-09-27 JP JP3248656A patent/JPH0590529A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI898870B (en) * | 2024-07-19 | 2025-09-21 | 南亞科技股份有限公司 | Method of manufacturing a semiconductor device |
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