JPH0590290A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To keep an LDD structure unchanged in characteristic in conformity to the more micronization of a MOSEFET and to enable an N<-> layer prevented from deteriorating in transmission conductance to be formed bay a method wherein both the side parts of a gate electrode are formed to become gradually smaller in thickness toward the ends of a gate region, as compared with time thickness of the center of the gate. CONSTITUTION:A gate electrode 3 of polycrystalline silicon or metal film is formed on an Si substrate 1, impurity ions are implanted into the Si substrate 1 using time gate electrode 3 as a mask for the formation of a low concentration ion implanted region 4a under both the sides of the gate electrode 3. In succession, a side wall spacer 5 formed of a silicon oxide film is formed on both the side faces of the gate electrode 3, impurity ions are implanted the side wall spacers 5 and the gate electrode 3 as a mask for the formation of a high concentration ion implanted ion region 4b. In this case, in a process where the gate electrode 3 is formed, both the sides of the gate electrode are formed so as to become gradually smaller in thickness toward the ends of a gate region as compared with the center of the gate electrode 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOS transistor having an LDD (Lightly Dosed Drain) structure.

[0002]

2. Description of the Related Art In recent years, with the progress of microfabrication technology in the manufacture of semiconductor devices, the miniaturization of the gate length of MOSFETs has made remarkable progress, which has led to a dramatic increase in the degree of integration and performance of integrated circuits composed of MOSFETs. It has improved. However, as the miniaturization of the gate progresses, many problems occur. One of them is the problem of reduced reliability such as characteristic deterioration due to hot carrier generation.

Among the techniques for suppressing the characteristic deterioration of the MOSFET due to hot carriers, the LDD structure MOSFET shown in FIG. 4 is known as the most well-known prior art. (Reference: Al F. Tasch, et al., IEEE Electron De
vice Letters, 11, 11 (1990) 517-519).

The feature of the LDD structure is that the high concentration region 4b is formed in the ion implantation region forming the source / drain as shown in FIG.
(N ⁺ layer) and low concentration region 4a (n ⁻ layer, offset region)
The two types of implantation regions are provided. These two types of ion implantation regions 4a and 4b are formed by primary ion implantation using only the gate electrode 3 as a mask and secondary ion implantation using the gate electrode 3 and sidewall spacers 5 formed on both side surfaces thereof as a mask. It is provided by a stepwise ion implantation process.

In this structure, by providing the n ⁻ layer 4a,
Since the electric field near the source / drain is relaxed and the width of the depletion layer extending from the source / drain toward the channel region is reduced, the hot carrier effect, the source / drain breakdown voltage reduction, and the short channel effect are suppressed. It is valid.

However, since the sidewall spacers 5 are generally formed of an insulator such as silicon oxide, the generated hot
Electrons are accumulated therein, and the side wall spacers 5 are negatively charged. As a result, the resistance in the n ⁻ layer 4a is further increased, and thus the transfer conductance gm is further reduced, resulting in characteristic deterioration.

Further, as shown in FIG. 5, there is an improved LDD MOSFET in which the gate electrode 3 is shaped so as to overlap between the side wall spacer 5 and the n ⁻ layer 4a. In this structure, hot electrons are not accumulated in the overlap portion 3a, and the above-mentioned L
It is possible to prevent characteristic deterioration peculiar to the DD MOSFET.

[0008]

[Problems to be Solved by the Invention]
Although the n ⁻ layer plays an important role in the LDD MOSFET that reduces the carrier effect, the increase in the resistance of the n ⁻ layer causes a decrease in the transfer conductance gm. However, if the n ⁻ layer impurity concentration is increased, the resistance of the n ⁻ layer is reduced, but the LDD MOS that suppresses the hot carrier effect is reduced.
It will be out of the essential structure of FET, and short circuit
It can also cause channel effects.

On the other hand, the above-mentioned overlap type LDD M
In the OSFET, impurity ions are implanted using the overlap portion as an ion implantation filter, and an n ⁻ layer having a low impurity concentration is uniformly formed in the lower layer region under the overlap portion. However, even in this case, in order to reduce the resistance of the n ⁻ layer, it is necessary to increase the impurity concentration of the n ⁻ layer, which runs the risk of causing the short channel effect.

Therefore, the present invention has both effects of maintaining the characteristics of the LDD structure and preventing the decrease of the transfer conductance gm in order to solve the above problems in accordance with the further miniaturization of the MOSFET. ^- to provide a method of manufacturing a semiconductor device capable of forming a layer.

[0011]

According to a method of manufacturing a semiconductor device having an LDD structure of the present invention, a gate electrode made of a polycrystalline silicon film or a metal film is formed on a silicon substrate via a gate insulating film, and the gate electrode is formed. A step of forming low-concentration ion-implanted regions of the source / drain ion-implanted regions under both sides of the gate electrode by impurity ion implantation as an ion-implantation mask, and forming sidewall spacers made of a silicon oxide film on both sides of the gate electrode. And a step of forming a high-concentration ion-implanted region of the ion-implanted region forming the source / drain by impurity ion implantation using the sidewall spacer and the gate electrode as an ion-implantation mask. In the process, the thickness of both sides of the gate electrode is smaller than the thickness of the central portion of the gate electrode. Headed is shaped to be thinner gradually, thereby the impurity ion implantation using a mask, n has an impurity concentration gradient ^- and forming a layer.

[0012]

According to the present invention, the gate electrode shaped as described above is used.
Impurity ions through both sides (overlap) of the pole
Ion implantation makes it difficult for ions to pass through on the channel region side.
Under the thick part of the difficult overlap,
N of impurity ion concentration ^-The layers are also n⁺Layer side end
Ions are sufficiently transmitted in the thin area of the overlap area
However, n with a relatively high impurity ion concentration^-Layers are formed
Like n^-Depending on the purpose in the layer region, its impurity ions
It is possible to form a source / drain with a concentration gradient.
It is possible to obtain an overlap type LDD MOSFET
Be done.

[0013]

EXAMPLE FIG. 2 (A)-(H) and FIG. 3 (I)-(M)
A method of manufacturing a MOSFET type semiconductor device is shown as an example of the present invention.

In the first step (FIG. 2A), a normal LDD is used.
Similar to the manufacturing process of the MOSFET having the structure, the gate oxide film 2, the polycrystalline silicon film 3 ′, and the silicon oxide film 6 patterned in a predetermined shape are sequentially formed on the region where the gate electrode is formed on the p-type semiconductor substrate 1. At this time, the polycrystalline silicon film 3'is doped with phosphorus ions (P) in order to reduce the resistance.

In the second step (FIG. 2B), the polycrystalline silicon film 3'is formed by using the silicon oxide film 6 as an etching mask.
Is anisotropically etched to uniformly etch a region of the polycrystalline silicon film 3'not covered with the silicon oxide film 6 to a predetermined depth. In this case, hydrogen bromide (HBr)
1: 1 mixed gas of helium and helium (He) (pressure: 2.66
P), etching rate: 4000Å / m
Etching proceeds in.

In the third step (FIG. 2C), next, the polycrystalline silicon film 3'partially etched and shaped in the second step is formed.
Isotropic etching is performed. In this case, when performed in sulfur hexafluoride (SF ₆ ) gas (room temperature, pressure: 1.33P), etching rate: 2000 to 3000Å / mi
Etching proceeds with n. At this time, the silicon oxide film 6
Etching also proceeds evenly to the polycrystalline silicon film 3'under the edge of the edge of the silicon oxide film 6 to form the edge of the silicon oxide film 6 in the shape of an eaves 6a.

By repeating the preceding step and this step alternately a plurality of times, the polycrystalline silicon film 3'in the region m not covered with the silicon oxide film 6 is uniformly etched from its surface, and finally the region is formed. The etching time is set so that the polycrystalline silicon film 3'is removed at m.

As described above, when the second step and the third step are alternately repeated several times (FIGS. 2D to 2H), the film thickness of the bottom of the polycrystalline silicon film 3'is gradually increased toward the edge thereof. Overlap part 3a which is thin and finally shaped like a staircase
Is formed.

In the fourth step (FIG. 3I), the gate oxide film 2 in the region m whose surface is exposed in the second to third steps is removed by anisotropic etching using the silicon oxide film 6 as a mask. At this time, etching progresses uniformly from both surfaces of the gate oxide film 2 and the silicon oxide film 6, and the region m
The thin gate oxide film 2 is first removed, and the etching process is stopped when the silicon substrate is exposed.

In the fifth step (FIG. 3J), the eave portion 6a at the edge of the silicon oxide film 6 is removed by isotropic etching,
The polycrystalline silicon film 3'shaped in the previous step is shaped to have the same width as the upper portion. Thus, the gate electrode 3 including the gate oxide film 2, the polycrystalline silicon film 3 ′ and the silicon oxide film 6 is formed.

In the sixth step (FIG. 3K), the gate electrode 3
Is used as an ion implantation mask to perform impurity ion implantation 7 through the overlapping portion 3a formed in the second and third steps to form the n ⁻ layer 4a. At this time, when ion implantation 7 of phosphorus ions (P) or arsenic ions (As) is performed with a dose amount of about 1 × 10 ¹³ / cm ² , ions below the overlap portion 3a of the silicon substrate 1 and in the region m of low concentration. An implant region can be formed. At this time, in the lower portion of the overlapping portion 3a having a different thickness, an ion implantation region n ⁻ layer having a relatively low impurity concentration is formed below the thick portion, and an ion implantation region n ⁻ having a relatively high impurity concentration is formed in the thin portion. ^- the layer is formed, n ^- can be formed by cod a gradient to the ion concentration in the layer.

In the seventh step (FIG. 3L), silicon oxide is further deposited, and the silicon oxide is shaped by anisotropic etching to form sidewalls 5 made of silicon oxide on both side walls of the gate electrode 3.

In the eighth final step (FIG. 3M), impurity ion implantation 8 is performed using the gate electrode 3 and the sidewall 5 formed in the previous step as an ion implantation mask, and the gate electrode 2 of the silicon substrate 1 is not covered. N ⁺ layer 4b in the region
To form. At this time, the dose amount of P or As is 5 × 1
When the ion implantation 8 is performed at about 0 ¹⁵ / cm ² , the ion implantation region n ⁺ layer 4 having a high impurity concentration is formed in the region m.
b is formed.

Thus, the impurity concentration layers (n ⁻ layer, n ⁺ layer) of two stages are provided, and further, the impurity concentration distribution of the low impurity concentration layer (n ⁻ layer) has a gradient. It is possible to form the MOSFET of the overlap type LDD structure having the source / drain of the divided structure.

[0025]

According to the method of manufacturing a semiconductor device of the present invention, in the formation of the impurity-implanted layer serving as the source / drain of the MOSFET having the LDD structure, the thickness of both sides of the gate region is larger than the thickness of the central region of the gate region. By performing the impurity ion implantation through both side portions of the gate electrode shaped so as to be gradually thinned toward the end portion of the gate region, an ion concentration gradient can be provided in the low concentration ion implantation region. As a result, the impurity ion concentration on the channel region side of the low-concentration ion implantation region is low, and on the opposite side, the impurity ion concentration can be appropriately increased, so that the LDD structure can be maintained, the hot carrier effect is reduced, and the transmission is reduced. It is possible to obtain a semiconductor device capable of preventing a decrease in the conductance gm. Moreover, since a sufficiently low concentration ion implantation region can be secured, the short channel effect can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device manufactured according to the present invention.

FIG. 2 is a cross-sectional view showing the first half step of the method of the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a second half step of the method of the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the structure of a semiconductor device manufactured by a conventional technique.

FIG. 5 is a cross-sectional view showing the structure of a semiconductor device manufactured by another conventional technique.

Claims (1)

[Claims] 1. A step of forming a gate electrode made of a polycrystalline silicon film or a metal film on a silicon substrate via a gate insulating film, and ions forming source / drain by impurity ion implantation using the gate electrode as an ion implantation mask. A step of forming low-concentration ion implantation areas in the implantation area below both sides of the gate electrode, a step of forming sidewall spacers made of a silicon oxide film on both sides of the gate electrode, and ion implantation of the sidewall spacer and the gate electrode. A method for manufacturing a semiconductor device having an LDD structure, which comprises sequentially forming a high-concentration ion-implanted region of a source / drain ion-implanted region as a mask by implanting impurity ions, wherein in the step of forming the gate electrode, The thickness of both sides of the gate electrode is greater than the thickness of the center of the gate electrode A method of manufacturing a semiconductor device, characterized in that the semiconductor device is shaped so as to become gradually thinner.