JPH0587018B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a monolithic integrated circuit, and more particularly to a gate array type master slice type monolithic integrated circuit in which basic cells are arranged in rows and columns to constitute an internal cell array region.

[Conventional technology]

Conventionally, when supplying an external power supply potential to the internal cell array area of a gate array type master slice integrated circuit (hereinafter referred to as gate array) in which basic cells are arranged in rows and columns to configure the internal cell array area, the internal cell array area It is necessary to supply the basic cells within. Power supply potential supply wiring is laid vertically over the internal cell array area so that all types of external power supply potentials are located on each basic cell, and each basic cell section is provided with the external power supply wiring required by that basic cell. A method of supplying electric potential was used.

Most conventional large-scale gate arrays
It is a CMOS gate array. In the case of CMOS gate arrays, the noise margin of the circuit itself is large and the steady current of the circuit is small, so even if very thin power supply potential supply wiring is laid within the internal cell array area using the conventional method, no problems will occur. Nakatsuta. In addition, in the case of conventional bipolar gate arrays, the scale is relatively small and the noise margin of the circuit itself is small, and even in the case of ECL gate arrays where the steady current of the circuit is large, the conventional method is applied to the internal cell array area. By laying a thick power supply potential supply wiring, it was possible to obtain sufficiently desired electrical characteristics. but,
Nowadays, as the electrical characteristics of CMOS gate arrays, especially their speeds, have progressed, there has been a demand for larger scale and higher speed ECL gate arrays.Power supply potential supply wiring is laid in the internal cell array area using conventional methods. The inconvenience of doing so has become noticeable.
The high speed of ECL gate arrays depends largely on the driving impedance and load capacitance of the circuit. Therefore, in order to have a logic amplitude that secures the minimum necessary noise margin for circuit operation and to keep drive impedance low, the steady current of the ECL circuit is inevitably large.

As the scale of the gate array increases, the number of basic cells to be supplied per one power supply potential supply line that runs vertically within the internal cell array region and supplies external power supply potential to the basic cells usually increases. For large-scale ECL gate arrays that require high speed. Since the steady current of each basic cell is large, when using the conventional power supply potential supply wiring wiring method, the power supply potential supply wiring runs vertically within the internal cell array area in order to minimize the reduction in noise margin due to the level shift of the power supply potential. It is necessary to set the wiring width per wire to be quite large. However, setting the power supply potential supply wiring to be thick will reduce the signal wiring installation area because the wiring installation area is limited in gate arrays, reducing the degree of freedom in laying the signal wiring. . In addition, in order to not reduce the degree of freedom in laying signal wiring, it is necessary to expand the wiring laying area, and in this case, the chip size increases and the average wiring length of signal wiring connecting basic cells increases, which increases the overall integrated circuit. Electrical properties, especially high speed, are impaired and manufacturing yields are reduced.
Furthermore, when the wiring width of the power supply potential supply wiring is set to be large, the intersection area of the signal wiring that is formed in a wiring layer different from the wiring layer in which the power supply potential supply wiring is formed and intersects with the power supply potential supply wiring increases. The parasitic capacitance added to the signal wiring increases, resulting in a loss of high-speed circuit operation.

A conventional gate array type integrated circuit will be explained with reference to the drawings.

FIG. 2 is a layout diagram of an example of a conventional gate array type integrated circuit.

In this integrated circuit, basic cells 11' are arranged in a matrix of 20 rows and 10 columns to form an internal cell array area 25, external power supply potential supply lines 23 and 24 are provided on the opposite side, and external power supply potential supply lines 23 and 24 are connected to external power supply potential supply lines 23 and 24. It is constructed by providing terminals 21 and 22.

The external terminal 21 is supplied with the highest external power supply potential from the outside, and this potential is supplied to the internal cell array region 25 through the external power supply potential supply wiring 23. The external terminal 22 is similarly supplied with the lowest external power supply potential from the outside, and this potential is similarly supplied to the internal cell array region 25 through the power supply potential supply wiring 24 .

FIG. 3 is a layout diagram of the basic cell shown in FIG. 2.

Circuit components are formed in the lower layer of the basic cell 11', and power supply potential supply wiring areas 32, 33 are formed in the upper layer.
is provided. The power supply potential supply wiring area 32 is connected to the adjacent basic cells 1 that are vertically connected in FIG.
It is connected to the external power supply potential supply wiring 23 via the power supply potential supply wiring area 32 1'. Similarly, the power supply potential supply wiring region 33 is connected to the external power supply potential supply wiring 24 in FIG. 2. In this way the second
The power supply potential supply lines 23 and 24 in the figure end up running vertically over each basic cell 11' of the internal cell array region 25.

FIG. 4 is a circuit diagram of a conventional ECL basic circuit.

The ECL basic circuit consists of two circuit components: a current switch section 45 and an emitter follower section 46. In the current switch section 45, a constant current section is formed by a transistor Q ₃ and a resistor R ₃ , and the constant current is connected to a transistor Q. ₁ and the switching operation of transistor _Q2 causes the current to flow through resistor _R1 or resistor _R2 . One ends of the resistor R ₁ and the resistor R ₂ are connected to a power supply potential supply wiring 41 to which a high external power supply potential is applied, and one end of the resistor R ₃ is connected to a power supply potential supply wiring 43 to which a low external power supply potential is applied. connected to.
At one end of resistor _R1 or resistor _R2 connected to the collector terminal of transistor _Q1 or transistor _Q2 , a high level potential is generated when no current flows through resistor _R1 or resistor _R2 , and a low level potential is generated when current flows. , this potential is the emitter follower part 4
It is input to the base terminal of transistor _Q5 or transistor _Q4 of No.6. The difference between the high level potential and the low level potential is called a logic amplitude. The emitter follower section 46 outputs to the emitter terminal a high level potential or a low level potential whose level is shifted by the forward voltage between the base and emitter of each transistor from the level input to the base terminal of transistor _{Q 4 or} transistor Q 5. . The collector terminals of the transistor Q ₄ and the transistor Q ₅ of the emitter follower section 46 are connected to the power supply potential supply wiring 42 to which a high external power supply potential is applied, and one ends of the resistors R ₄ and R ₅ are connected to the low potential external power supply wiring 42 . It is connected to a power supply potential supply wiring 44 to which a power supply potential is applied. This ECL basic circuit is incorporated into the basic cell shown in FIG.

Now, the current switch section 45 in FIG.
Assume that the current in the emitter follower section 46 is 1 mA, the total current in the emitter follower section 46 is 2 mA, and the logic amplitude of the current switch section 45 is 500 mV.
Consider the case where each circuit 1' includes two sets of circuits shown in FIG. To simplify the explanation, only the highest potential external power supply potential system will be explained. The highest potential applied to the external terminal 21 in FIG. 2 is connected to the wiring in the power supply potential supply wiring area 32 in FIG.
The width of the wiring in the power potential supply wiring area 32 of the basic cell 11' is 100 μm, the length is 250 μm, and the wiring layer resistance is
Assume that it is 0.03Ω/□. If the conventional method is adopted, since the highest power supply potential supply wiring for the basic cell 11' is only in the power supply potential supply wiring area 32, both the power supply potential supply wirings 41 and 42 are connected to the wiring in the power supply potential supply wiring area 32. . As a result, when the level shift amount of the basic cell 11' in the cell position closest to the power supply potential supply wiring 23 among the basic cells 11' on the same column in FIG. The level shift amount is 85.5mV. The basic level shift difference between different columns is
Assuming that the voltage is 20 mV, the difference in level shift amount between all basic cells 11' in the internal cell array area 25 is
It becomes 105.5mV. For ECL gate arrays, level shifting of high potential power supply potentials directly leads to a reduction in noise margin. Since a level shift of a low power supply potential normally appears as a decrease in logic amplitude, 1/2 of this is involved in the decrease in noise margin.
For the sake of simplicity, let us assume that this value is 52.5 mV, which is 1/2 of the noise margin reduction due to the level shift of the high power supply potential.

When the logic amplitude is 500mV, the threshold is set at 1/2 of that, and if the point where the differential gain in the transfer characteristic is 1, that is, the unity gain point, is 100mV above the threshold, then the noise margin is acceptable. The output voltage is 150mV. The amount due to other factors that reduce the noise margin
If it is 30 mV, the total noise margin reduction in the above example will be 188 mV, which will divide the unity gain point and become a value that cannot guarantee stable operation of the circuit. Now, in order to keep the total noise margin reduction within 150mV, the width of the wiring in the power supply potential supply wiring area 32 in FIG.
Must be set to 128μm or more. At this time, it is necessary to similarly expand the wiring width of the wiring in the power supply potential supply wiring area 33 on the low potential side.
The total power supply wiring width increase width within 1' is required to be 56 μm or more.

[Problem that the invention seeks to solve]

As mentioned above, conventional wiring methods are used to lay power supply potential supply wiring for supplying external power supply potential within the internal cell array area of large-scale gate arrays with large steady-state currents per basic cell, especially ECL gate arrays. In some cases, it is necessary to set the power supply potential supply wiring width wide enough to ensure the noise margin of the circuit, and the parasitic wiring capacitance of the signal wiring that is formed in a wiring layer different from the wide power supply potential supply wiring and intersects with the wide power supply potential supply wiring. The first drawback is that the electrical characteristics of the integrated circuit as a whole, especially its high speed performance, are impaired. Furthermore, if the width of the power supply potential supply wiring is set to be large without enlarging the internal cell array area, there is a second drawback that the degree of freedom in laying the signal wiring within the limited wiring laying area is reduced. In addition, when expanding the internal cell array area and increasing the degree of freedom in laying signal wiring, the average wiring length of the signal wiring connecting basic cells increases, which increases the parasitic capacitance added to the wiring and reduces the electrical power of the integrated circuit as a whole. The third disadvantage is that the characteristics, especially the speed increase, is impaired, and the fourth disadvantage is that the chip size is increased and the manufacturing yield is reduced.

The purpose of the present invention is to provide a monolithic integrated circuit that uses two power supply potential supply lines for each target circuit, suppresses the noise margin of the circuit, increases the degree of freedom in signal wiring without increasing the chip size, and exhibits high speed. It's about doing.

[Means for solving problems]

The present invention is characterized by an internal cell array region in which basic cells having circuit components and power supply potential supply wiring are arranged in rows and columns, an external power supply potential supply wiring that supplies an external power supply potential to the internal cell array region, and the external power supply In a monolithic integrated circuit having an external terminal connected to a potential supply wiring, the circuit component includes a first type of circuit component section and a second type of circuit component section,
The power supply potential supply wiring is a first power supply potential supply wiring that runs vertically over the basic cell, mainly supplying the first type of circuit component, and a first power supply potential supply wiring that mainly supplies the first type of circuit component. It has a second power supply potential supply wiring that runs vertically over the basic cell as a supply target, and the first power supply potential supply wiring and the second power supply potential supply wiring are connected to the same external power supply outside the internal cell array area. The first type of circuit component section is commonly connected to the potential supply wiring, and the first type of circuit component section is connected to the second type of circuit component section.
A monolithic integrated circuit having a circuit type that is more sensitive to potential level shifts than the type of circuit component parts, and in which the wiring width of the first power supply potential supply wiring is larger than the wiring width of the second power supply potential supply wiring. It is in.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of an embodiment of the present invention. First type power supply potential supply wiring regions 12 and 13 and second type power supply potential supply wiring regions 14 and 15 are arranged in the upper layer of the basic cell 11, and the first type power supply potential supply wiring regions 14 and 15 are arranged in the lower layer.
and a second type of circuitry (not shown).

The first type of circuit component is divided into a current switch section 45 in FIG. 4, and the second type of circuit component is divided into an emitter follower section 46. Then, wiring for supplying a potential to the current switch section 45, which is a first type of circuit component, is placed in the first type of power supply potential supply wiring areas 12 and 13, and in the second type of power supply potential supply wiring area 14, Wiring for supplying a potential to the emitter follower section 46, which is a second type of circuit component, is provided at 15, respectively. Further, the wiring provided in the first type of power supply potential supply wiring region 12 supplies the highest potential to the current switch section 45 and is connected to the power supply potential supply wiring 41. The wiring provided in the first power supply potential supply wiring region 13 supplies the lowest potential to the current switch section 44 and is connected to the power supply potential supply wiring 43. The wiring provided in the second power supply potential supply wiring area 14 is for supplying the highest potential to the emitter/follower section 46, and is used as the power supply potential supply wiring 42.
connected to. Second power supply potential supply wiring area 15
The wiring provided at is for supplying the lowest potential to the emitter follower section 46 and is connected to the power supply potential supply wiring 44.

The wiring provided in the first power supply potential supply wiring areas 12 and 13 has a width of 60 μm and a length of 250 μm in the basic cell 11. The wiring provided in the power supply potential supply wiring areas 14 and 15 has a width of 30 μm and a length of 250 μm. Assume that the dimensions are , and the resistance of all wiring layers is 0.03Ω/□. The wiring in the power supply potential supply wiring regions 12 and 14 are both at the highest potential, and are short-circuited at the end of the internal cell array region 25 by connecting to the power supply potential supply wiring 23 in FIG. Similarly, the wiring within the power supply potential supply wiring regions 13 and 15 are both at the lowest potential, and are connected to the external power supply potential supply wiring 24 for short-circuiting. These power supply potential supply wiring areas 12, 13, 1
4 and 15 run vertically over the basic cells 11' of the internal cell array region 25 in FIG. Now, to explain the highest potential side, the amount of level shift of the power supply potential on the basic cell 11' in the cell position closest to the external power supply potential supply wiring 23 among the basic cells 11' on the same column in FIG. 2 is set to 0 mV. At this time, the level shift amount in the power supply potential supply wiring area 12 of the basic cell 11 corresponding to the farthest basic cell position 11' is 47.5 mV,
The level shift amount of the wiring within the power supply potential supply wiring region 14 is 190 mV. Assuming that the difference in level shift amount between different columns is 20 mV as in the conventional example, the maximum level shift amount difference between all the basic cells 11' in the internal cell array region 25 of the current switch section 45 is 67.5 mV, and The maximum level shift amount difference between all basic cells in the internal cell array region 25 of the emitter follower section 46 is 210 mV. Since the same result is obtained on the lowest potential side, the explanation will be omitted.

As described in the conventional example, in the current switch section 45 shown in FIG. 4, the amount of level shift of the highest power supply potential directly leads to a reduction in the noise margin. The amount by which the level shift amount of the lowest potential power supply potential affects the noise margin is 1/2, which is the same as in the conventional example, and the value is 33.5 mV. As in the conventional example, there is a threshold at 1/2 of the logic amplitude of 500 mV, and 100 mV from there is the unity gain point, and the amount due to other factors that reduce the noise margin is 30 mV.
The total amount of noise margin reduction in this example is
The result is 131mV, leaving a margin of 19mV to the unity gain point. Although the power supply potential supplied to the emitter follower section 46 in FIG. 4 has a level shift of 210 mV, this degree of level shift does not cause any problem with the circuit operation of the emitter follower. As described above, in this embodiment, although the total width of the power supply potential supply wiring provided in the basic cell 11 that supplies the highest potential or the lowest potential is 180 μm, the power supply potential supply in the conventional example is The results showed that the noise margin was greater than that of the case where the total wiring width was 256 μm, and the electrical characteristics were not impaired in any way.

In the above embodiment, the first type of circuit component is a current switch type circuit, and the second type of circuit component is an emitter follower. The TTL circuit component is a TTL logic circuit section, and the second type of circuit component is an output buffer circuit.
Gate array, the first type of circuit component
It can be applied to bipolar/CMOS mixed gate arrays, etc. in which the CMOS circuit part or the second type of circuit component is a bipolar circuit part, and one circuit component is isolated from the noise caused by the other circuit component to ensure a noise margin. This has the effect of

〔Effect of the invention〕

As described above, the present invention provides power supply potential supply wiring for circuit components with sufficient noise margin when supplying external power supply potential to the internal cell array region of a gate array, and power supply potential supply wiring for circuit components with no margin for noise margin. By separating the power supply potential supply wiring from the external power supply potential and supplying the external power supply potential, it is possible to minimize the power supply potential wiring area laid within the internal cell array area while ensuring a noise margin for the circuit.As a result, the chip size and This has the effect of increasing the degree of freedom in laying signal wiring without expanding the internal cell array area, and providing an integrated circuit that can exhibit electrical characteristics, particularly high speed. Furthermore, when the present invention is used, circuit components that undergo transient current changes can be separated from circuit components that are susceptible to noise, making it possible to improve the electrical characteristics and reliability of the integrated circuit itself.

[Brief explanation of drawings]

Figure 1 is a layout diagram of an embodiment of the present invention, Figure 2 is a layout diagram of an embodiment of the present invention.
FIG. 3 is a layout diagram of a conventional gate array type integrated circuit, FIG. 3 is a layout diagram of the basic cell shown in FIG. 2, and FIG. 4 is a circuit diagram of a conventional ECL basic circuit. 11, 11'... basic cell, 12, 13... first type power supply potential supply wiring area, 14, 15...
...Second type of power supply potential supply wiring area, 21, 2
2... External terminal, 23, 24... External power supply potential supply wiring, 25... Internal cell array area, 32, 3
3... Power supply potential supply wiring area, 41, 42, 4
3, 44...Power supply potential supply wiring, 45...Current switch section, 46...Emitter follower section, _Q1 , _Q2 , _Q3 , _Q4 , _Q5 ...Transistor,
R ₁ , R ₂ , R ₃ , R ₄ , R ₅ ...Resistors.

Claims (1)

[Scope of Claims] 1. An internal cell array region in which basic cells having circuit components and power supply potential supply wiring are arranged in rows and columns; an external power supply potential supply wiring that supplies an external power supply potential to the internal cell array region; In a monolithic integrated circuit having an external terminal connected to a power supply potential supply wiring, the circuit component includes a first type of circuit component section and a second type of circuit component section. , the power supply potential supply wiring is a first power supply potential supply wiring that runs vertically over the basic cell, mainly supplying the first type of circuit component, and a first power supply potential supply wiring that mainly supplies the second type of circuit component. It has a second power supply potential supply wiring that runs vertically over the basic cell as a supply target, and the first power supply potential supply wiring and the second power supply potential supply wiring are connected to the same external power supply outside the internal cell array area. are commonly connected to potential supply wiring, the first type of circuit component section is of a circuit type that is more sensitive to potential level shifts than the second type of circuit component section, and the first power supply potential A monolithic integrated circuit characterized in that the wiring width of the supply wiring is larger than the wiring width of the second power supply potential supply wiring. 2. A patent claim characterized in that the circuit component is an ECL type, the first type of circuit component is a current switch type circuit, and the second type of circuit component is an emitter follower. A monolithic integrated circuit according to claim 1.