JPH0585094B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a termination device for a data transmission line. Specifically, the purpose is to provide a new data termination device for connecting various types of asynchronous data terminals to the PCM transmission path.

[Prior Art] A technology related to a conventional data termination device for a synchronous data terminal is disclosed in, for example, Japanese Patent Application Laid-open No. 118032/1983, which will be described with reference to FIGS. 33 to 39.

Figure 33 shows a terminal with a speed of 19.2kbps.
It is a principle diagram for accommodating a 64 kbps transmission line in an electronic exchange. The flag synchronization bit (F bit) located at bit 0 of frame 0 is used to notify the receiving side of the frame position by repeating a flag pattern of "1010". The receiving side can easily recognize the frame position by detecting this. Accommodating a 19.2 kbps terminal on a 64 kbps transmission path can be achieved by accommodating 24 bits of data D0 to D23 in designated bit positions every 10 multiframes, as shown in FIG. Please do not use blank spaces.

FIG. 34 shows the principle of accommodating a 9.6 kbps terminal.

12, which is 1/2 the number of bits of 19.2 kbps in Figure 33.
Speed conversion is possible if bit data D0 to D11 can be accommodated, but in order to accommodate data of different speeds in the same circuit, in this case, the same data is embedded twice as shown in Figure 34. Accommodates different speeds as kbps. Similarly below, 4.8kbps
This data is achieved by embedding the same data four times each, and 2.4kbps data is achieved by embedding eight times each.

The principle of the synchronization establishment bit (SY bit) located at bit 0 of frame 1 will be explained with reference to FIG.
In Fig. 35, L ₁ and L ₂ are the transmission line and reception line, respectively, when viewed from the device A side, and the device B
From a closer perspective, the relationship is the opposite. However, in the following explanation, the state viewed from the A side will be explained.

The line terminating device DCE _a on the A side detects the F bit sent from the line terminating device DCE _b on the B side of the receiving line L ₂ and, when synchronization is established, turns on the SY bit and switches the transmitting line L ₁ on. Send to. When the line terminating device DCE _b on the B side establishes synchronization with the transmission line _L1 by receiving the F bit, it similarly
Sends the on state of the SY bit to receive line _L2 . With the above, the line terminating device DCE _a on the A side is connected to the receiving line.
By monitoring the SY bit of _L2 , the synchronization state of the transmission line _L1 can be known. Line termination device on B side
The same applies to DCE _b . Various control line information specified in JIS-C6361 is stored in bit 7 of frames 0 to 3 in FIGS. 33 and 34.
The alphabetic character to the left of the diagonal line in bit number 7 is A
The signal sent by the side terminating device DCE _a to the transmission line L ₁ ,
The English letters on the right are signals sent from the B-side line termination device DCE _b via the receiving line _L2 .

Here, RS is a request to send signal (Request to Send), CD is a received carrier detection signal (Carrier Detect), CS, CS′ is a clear to send signal (Clear to Send), and ER is a data terminal ready signal. The signal (Equipment Ready) and DR are data set ready signals (Data Set Ready), and CI and CI' are called indicator signals (Call Indicator). FIG. 36 shows a method of accommodating control signals between the terminal device A and the terminal device B, and FIG. 37 shows a method of accommodating control signals between the terminal device and the modem.

In FIG. 36, since terminal devices A and B are interfaces having the same input/output relationship, transmission data SD transmitted from terminal device A is received by terminal device B as reception data RD. Similarly, other lines are connected as shown in the figure. The transmission lines are connected as one unit to make the explanation easier to understand, but since the data formats shown in Figs. 33 and 34 are accommodated, two transmitting/receiving lines L ₁ and L ₂ are connected as shown in Fig. 35.
Lines are concentrated in books. As is clear from the principle explained in FIGS. 33 and 34, since each control signal is sampled only once every 10 frames, for example, even if terminal device A turns on RS (request to send), There is a delay of up to 1.25 ms before the reception carrier detection signal CD of B turns on, and the reception data RD appears before the reception carrier detection signal CD turns on.
When data from terminal device A arrives at , terminal device B cannot receive the data because it is not ready for reception.

Therefore, in order to keep the reception carrier detection signal CD in the on state during data reception, the value of the transmission request signal RS is determined by the logical sum of the previous and current sample values, and the transmission path is set as shown in the table below. This is achieved by determining the state to be sent to.

Value of RS Previous state Current state Transmission state Off Off Off Off On On On Off On On Off On Figure 38 shows the relationship between the transmission request signal RS and the transmission data SD. The relationship between the transmission request signal RS and the transmission data SD is that while the transmission request signal RS is on, the data D
has become effective. If we sample it in units of 10 multiframes (1.25ms) as mentioned above, RS
This becomes the sample pulse (RSP). However, if data D is delayed by 125 ms and sent out as transmission data SD to the transmission path, and the state judgment in the previous table is performed to determine transmission RS, the relationship between transmission RS and data D will be as shown in Fig. 38. and send request signal
The relationship that data D is valid while RS is on is detailed.

To delay data by 1.25ms, a 24-stage shift register is provided as shown in Figure 39, and the register
This is achieved by setting the load pulse to 125ms at the timing of transferring from REG _a to register REG _b .
The reason for providing 24 stages is that 24 stages are added to the 10 multi-frames mentioned above.
This is because bits must be embedded.

FIG. 37 shows a connection between a terminal and a modem, and unlike FIG. 36, transmission data SD is connected one-to-one to transmission data SD of a modem (modem). Other control signals are also connected one-to-one as shown in the figure. Also, the output signal from the modem is
CS and CI are realized by connecting to CS′ and CI′.

[Problems to be Solved by the Invention] The termination devices shown in FIGS. 35, 36, and 37 have a multi-frame configuration on a channel transmission line fixed at 64 kbps, for example, 2.4 kbps,
It accommodated and transmitted synchronous terminal data and various control line information at data (communication) speeds such as 4.8 kbps, 9.6 kbps, and 19.2 kbps.

Recently, however, various data terminal devices have become commercially available, and many of these terminal devices operate using their own clocks, regardless of the operation timing of the transmission line.
As a result, data from asynchronous terminal devices with data (communication) speeds such as 2.4 kbps, 4.8 kpbs, 9.6 kbps, 19.2 kbps, etc., which are not in a synchronous relationship with the transmission path, can be transferred to PCM (pulse code) with various speeds.・Modulation) There is an increasing demand for asynchronous transmission and reception on transmission lines, but such conventional asynchronous terminal equipment can be used at various speeds, such as 128 kbps,
192kbps, 256kbps, 384kbps, 1.544Mbps,
2.048Mbps, etc.
There was a problem that it could not be connected to the PCM transmission line.

[Means to solve the problem] To obtain the basic clock from the PCM transmission line.
A PLL circuit, a timing generation circuit that generates various timing signals necessary for the operation of each circuit in this terminal device based on the basic clock that is the output of this PLL circuit, and a data signal from the terminal device. a mapping circuit that performs mapping to match the data speed of the PCM transmission line in response to the received data, and a speed conversion transmission register that outputs the output of this mapping circuit at a specified speed at a specified time to the PCM transmission line. , a receiving register for receiving the data signal sent via the PCM transmission line and outputting it at the requested time at the data rate required by this terminal device; A demapping circuit for sending the demapped data is provided.

[Function] With this configuration, it is now possible to map the data signal of the terminal device at a speed faster than the data speed of the terminal device, convert the speed, and send it to the PCM transmission line. . Also PCM
The data signal from the transmission path is converted in speed and received.
The data is transmitted to the terminal device using demapping means.

By doing this, you can set different data speeds, for example, 2.4kbps, 4.8kbps, 9.6kbps,
By mapping and demapping various terminal devices operating at one data rate, such as 19.2kbps, the timing is matched and high-speed PCM
It has become possible to communicate asynchronous states via a transmission line.

[Embodiment] The present invention is a PCM transmission path termination device that can handle data at various speeds, and a system configuration diagram for explaining the operational concept is shown in Fig. 1A.
The waveforms of each part are shown in FIG. 1B and will be explained.

In FIG. 1A, a PCM transmission path is interposed between a termination device 5A on the terminal device A side and a termination device 5B on the terminal device B side. The signal speed of this PCM transmission line is, for example, 128kbit, 192kbit,
One of 256 kbit, 384 kbit, 1.544 Mbit, 2.048 Mbit ps, etc. is used, and a PCM exchange switch 8 is provided for exchanging signals on this PCM transmission line. This PCM exchange switch 8
is a PCM transmission line with various timing signals, i.e.
XSYN (transmission synchronization signal), XCLK (transmission clock),
RSYN (reception synchronization signal), RCLK (reception clock)
It includes a PCM timing circuit 9 that sends out data signals and exchanges data signals.

The various timing signals sent from the PCM timing circuit 9 to the termination devices 5A and 5B via the PCM transmission path and the timing of data transferred by the PCM exchange switch 8 are shown in FIG. 1B.

XCLK and RCLK in Figure 1B a and d are:
Various types of clocks are used to regulate the signal speed of this PCM transmission line. XCLK shown in this a
and XSYN of b sent in synchronization with XCLK.
When the terminal device 5A receives, the terminal device 5A receives,
Data signals D0 to D7 received from terminal device A are
PCM in the period of XSYN of b as DOUT shown in
Send to the transmission path. The transmission of DOUT shown in c is performed at intervals of 125 μs. In the terminal device 5B,
During the RSYN period of e synchronized with RCLK shown in d,
Data signals D0 to D7) from terminal device A are received at intervals of 125 μs as DIN shown at f.

Communication between the terminal devices 5A, 5B and the terminal devices A, B uses various timings created from XSYN in the terminal devices 5A, 5B, as shown in FIGS. 36 and 37, which have already been explained as prior art. SD, RD, RS, CS, CS′, CD, ER, DR,
This is done using each signal of CI′CI.

Of the operational concept explained in FIG. 1A, the parts related to the present invention, namely the terminal devices 5A and 5B
The specific configuration of the circuit is shown in FIG. 2A, and the waveforms of each part thereof are shown in FIG. 2B, and will be explained. Here, both terminal devices 5A and 5B have the same configuration.

In Figure 2A, 100 is a PLL (phase
(lock loop) circuit, and is a PCM transmission line
In addition to XSYN (transmission synchronization signal), the basic clock 12 is used to obtain various timing signals within this device.
Create 1. This XSYN and basic clock 121
As shown in FIG. 2B, c and f, the leading edge of the basic clock 121 is synchronized with the trailing edge of XSYN.

The timing generation circuit 200 receiving the basic clock 121 generates a second clock based on XCLK and XSYN.
Signals 231, 232, 2 shown in Figure B b, k, l
33, signals 274, 275, and even signal 26
bus signal 259, bus signal 28 containing 2,264
Outputs 6.

300 is a mapping circuit which receives transmission data SD sent from the terminal device, transmission request signal RS,
The clear-to-send signal CS', the data terminal ready signal ER, and the called indication signal CI' are sent to the bus signal 259 and the signal 27 as shown in FIG. 33 or 34.
4 and outputs the map signal 386 shown in FIG. 2B a.

60 is a transmission register, and a map signal 386
(a) in FIG. 2B is sampled by the signal 231 in FIG. 2B and taken into the register, and the contents of the register are output as DOUT as shown in e during the XSYN period shown in c and in synchronization with XCLK shown in d.
This DOUT e is repeated every 125μs.
One frame shown in FIG. 33 or 34 is sent out in order from frame 0 for each XSYN c.

80 is a receiving register, shown in Figure 2B g.
Load DIN shown in i into the register by sampling with RCLK shown in period h of RSYN,
The demapped signal 90 of j is outputted by the signal 232 of the period k of the signal 233 shown in FIG.

400 is a demapping circuit which receives the demapped signal 90 and outputs the received data contained therein.
RD (D0-5, D6-11... in FIG. 2B j) at the timing of signals 262 and 275, and
Clear to send signal CS, data set ready signal
DR, the called indication signal CI is sent to the timing of the bus signal 286, and the received carrier detection signal CD is sent to the signal 264.
At this timing, contrary to the mapping shown in FIG. 33 or 34, the data is demapped and sent to the terminal device.

Furthermore, the demapping circuit 400 sends the frame numbers (frame 0, frame 1, etc.) shown in FIG. .

In the demapping circuit 400, the frame 1
The mapping circuit 300 detects the SY bit (j in Fig. 2B) and sends a signal 551 indicating that synchronization has been established to the mapping circuit 300.
It is called SY bit (first bit).

In the mapping circuit 300, the transmission request signal RS
When received, it sends out a signal 367, and upon receiving this, the demapping circuit 400 performs an AND operation with the CS of frame 1 in FIG. 2B, j, and outputs a transmittable signal CS.

FIG. 3 illustrates the relationship between the transmission clock b and the transmission data SD a inside the asynchronous terminal device connected to the terminal device 5A (or 5B). The transmission clock inside the terminal shown in b causes the data D0, D1, etc. to be sent out from the terminal device as transmission data SD as shown in a at the rising edge of the clock, as shown in a.
The voltage is applied to the mapping circuit 300. The transmitting clock shown in FIG. 3b is connected to the terminal device 5A (or 5B).
There is no synchronous relationship.

Figure 4 shows that even if the data terminal equipment
Transmitted data SD when operating at a speed of 1.2kbps
a, the relationship between timing signal 274b and sampled SD d is shown. The data terminal device sends the transmission data SD shown in FIG. 4a to the mapping circuit 300 using the internal transmission clock shown in FIG. 3b.

Upon receiving this, the mapping circuit 300 maps the sampled SD shown in d by sampling one data many times (16 times in the illustrated case) using the timing signal 274 shown in b.

FIG. 5 shows the circuit configuration of the timing generation circuit 200. Here, 210 is a register timing circuit, which sends timing signals 231 and 2 to the transmission register 60 and reception register 80.
32, 233 as the basic clock 121 and signal 2
It has been made since 73.

240 is a clock timing circuit, which receives the basic clock 121, XCLK, and XSYN,
Signal 273 to register timing circuit 210
It generates a bus signal 276, a signal 274 to the mapping circuit 300, a bus signal 259, and a signal 275 to the demapping circuit 400. Here, signals 262 and 264 included in bus signal 259
is also applied to the demapping circuit 400.

280 is a reception timing circuit which receives the basic clock 121 and bus signals 526 and 276 and outputs the bus signal 286 to the synchronous reception circuit 400.
is being sent.

FIG. 6A shows a specific circuit of the register timing circuit 210, and waveforms of each part thereof are shown in FIG. 6B.

The signal 273a applied from the clock timing circuit 240 is applied to the reset terminal R of the 24-decimal counter 211 every 125 μs. 211 output Q0
When the value c of ~Q4 reaches 23, it is reset by the signal 273 of a. When the outputs Q3 and Q4 of the 24-decimal counter are both “0”, the inverters 218 and 219
AND gate 214 with a signal applied through
outputs “1”. This and gate 214
Both outputs Q3 and Q4 are "0" during the period when the value shown in c is from 0 to 7.

During the period when the output of the AND gate 214 is "1", the D flip-flop 212 to which this is applied continues to output "1" due to the basic clock 121 being applied to the clock terminal, so the output is "1" as shown in d. The signal will look like signal 233. and·
The gate 216 ANDs this signal 233 and the basic clock 121 to generate a signal 232 shown at h.
get.

The D flip-flop 213 receives a signal 233d and the basic clock 121b via the inverter 220, and outputs a signal 235 which is delayed by half the basic clock 121b from the signal 233 of d.
is obtained at output terminal Q as shown in signal 235 of f.

AND gate 215 receives signal 233 at d and basic clock 121 via inverter 220, performs an AND operation, and obtains signal 234 shown at e. In the AND gate 217, the f signal 23
5 and the e signal 234 to obtain the g signal 231.

7A and 7B are circuit diagrams and timing charts of clock timing circuit 240.

In Figure 7A, 241 is an 8-stage serial
Parallel (S/P) register, Figure 7B a
The XSYN shown at 125 μs intervals is applied to the data input DI, and the XCLK shown at b is applied to the 8-stage S/P register 241 via the inverter 251.
applied to the clock terminal of A signal 278 shown in c is obtained at the output Q7. This signal 278
The rising edge of b is higher than the falling edge of XSYN of a.
The rising edge is 1/2 cycle of XCLK earlier than the falling edge of XSYN shown in a, as shown in b.
The 7th signal falls with a delay of 1/2 cycle of XCLK.
AND gate 249 performs an AND operation with output Q0, which is not shown in figure B, and the signal rises 1/2 cycle before and 1/2 cycle after the falling edge of XSYN shown in figure a. A falling signal 279 shown at d is obtained.

This signal 279 is applied to the reset terminal R of the 24-ary counter 242. On the other hand, the basic clock 121 shown at e is applied to the clock input terminal of the 24-decimal frame counter 242, and when the signal 279 shown at d is applied to the reset terminal R, this basic clock 121 is counted up from 0. When the count reaches 23, a signal 258 shown at g is output from the carry out terminal CRY, and the count value during this counting up is outputted by a bus signal 276 shown at f.

The signal 258 shown at g from the carry-out terminal CRY of the 24-decimal frame counter is connected to the decimal multi-frame counter applied to the enable terminal ENB.
The counter 243 receives the basic clock 121 of e through the inverter 252 to its clock terminal, counts up from 0 every signal 258, outputs a bus signal 277 indicated by the count value h, and outputs a bus signal 277 indicated by the count value h. When the count value of the bus signal 277 reaches 9, the count value of the bus signal 277 shown in h is set to 0 by applying the next signal 258 shown in g and the basic clock 121 via the inverter 252, and the count value starts again. rise.

Bus signal 276, which is the output of 24-decimal frame counter 242, is applied via decoder 244 to flip-flop group 245, which includes one D flip-flop for each signal decoded. Each of the decoded signals is applied to the data terminal of each flip-flop, and the clock terminal of each flip-flop has a basic clock signal.
21 (CK1) or the basic clock 121 (CK2) via an inverter 252 is applied.

In this way, the flip-flop group 245 outputs the signal 260 indicated by i when the bus signal 276 of f reaches 9, and then the signal 260 delayed by 1/2 cycle of the basic clock 121 of e.
62 is obtained as shown in j.

Signal 2, which is the output of flip-flop group 245
61, when the value of the bus signal 277 shown in h indicates 0 and the value of the bus signal 276 shown in f indicates 10 to 15, one pulse, ie, a group of six pulses, is generated for each value of the bus signal 276. This is the case when the value of bus signal 277 of h is 0,
It is also output in the case of 1, 2, and 3 (Fig. 17B d
reference).

Signal 2, which is the output of flip-flop group 245
64 is output as a pulse with a pulse width of one cycle of the basic clock 121 of e when the bus signal 277 shown at h shows a value of 0 and the bus signal 276 shown at f shows a value of 10. .

Similarly, the signal 265 is the bus signal 2 shown at h.
The value of 77 indicates 1, and the bus signal 276 shown at f
When the value of 10 is shown, the basic clock of e is 1 of 121.
It is output as a pulse with a pulse width equal to a cycle.

Similarly, the signal 267 is the bus signal 277 shown in h.
When the value of 3 indicates 3 and the bus signal 276 indicated by f indicates a value of 16, a pulse having a pulse width of one cycle of the basic clock 121 of e is output.

Similarly, the signal 270 shown at l indicates that the value of the bus signal 277 shown at h is 0, and the bus signal 277 shown at f
When 6 shows the value of 16, the basic clock of e is 121
It is output as a pulse with a pulse width of one cycle.

Similarly, the signal 271 is the bus signal 277 shown in h.
The value of indicates 1, and the bus signal 276 indicated by f indicates 16.
When , the signal is output as a pulse having a pulse width of one cycle of the basic clock 121 of e.

Similarly, the signal 272 is the bus signal 277 shown in h.
When the value of 2 indicates 2 and the bus signal 276 indicated by f indicates 16, a pulse having a pulse width of one cycle of the basic clock 121 of e is output.

Similarly, the signal 273 shown at n indicates that the bus signal 277 shown at h has a value of 0, and the bus signal 277 shown at f
When 6 indicates 7, it is delayed by 1/2 cycle of the basic clock 121 of e, and is output as a pulse with a pulse width of 1 cycle.

These signals 260, 261, 262, 26
3,264,265,267,270,271,
272 and 273 form a bus signal 259.

The signal 263 shown at k has a value of 0 for the bus signal at h.
is output while the value of the bus signal f is 10 to 15, and is output in the same way when the value of the bus signal h is 1, 2, or 3.

The signal 276 shown at f is also applied to the decoder 246, and the same signal 262 shown at j is applied to one terminal of the AND gate 250.

The bus signal 277 shown at h is also applied to the decoder 247, decoded, and becomes the bus signal 277 at h.
While the value of 7 is 0, “1” is output to the other terminal of the AND gate 250. Therefore, the output of this AND gate 250 becomes the same signal as the j signal 262 and is applied to the reset terminal R of the decimal counter 248 to reset it. On the other hand, this 10
The basic clock 121 shown at e is applied to the clock terminal of the advance counter 248, and the signal 2 shown at j is applied.
e applied after the same time as the rise of 62
When the basic clock 121 rises, the signal 275 shown at p rises, causing the basic clock 121 to rise to 5.
It falls when counting 5 times, and then rises again when it counts 5 times. Signal 275 to inverter 25
3, a clock 274 is obtained.

A specific circuit of the reception timing circuit 280 and its timing chart are shown in FIGS. 8A and 8B.

In FIG. 8A, decoder 281 decodes bus signals 276 and 526 and applies them to flip-flop group 282. Here decoder 2
81, flip-flop group 282 and inverter 283 are connected to decoder 24 shown in FIG. 7A.
4, flip-flop group 245, and inverter 252, respectively.

The signal 288 shown in c is the bus signal 52 shown in d.
This signal is output every time the value of 6 changes, has a pulse width of one cycle of the basic clock 121 of a, and indicates "1" from the latter half of 23 to the first half of 0 of the value of the bus signal 276 of b. .

The signal 287 shown in e is the bus signal 52 shown in d.
Each time the value of 6 changes, the bus signal 276 shown in b
When the value of is 9, the basic clock 121 of a
It is output with a pulse width of one cycle.

The signal 289 shown in h is the bus signal 52 shown in d.
When the value of 6 indicates 1, and the bus signal 2 of b
The value of 76 indicates "1" in the second half when it shows 9 and the first half when it shows 10.

The signal 293 shown in g is the bus signal 52 shown in d.
When the value of 6 indicates 0, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 16 to the first half when it shows 17.

The signal 294 shown in i is the bus signal 52 shown in d.
When the value of 6 indicates 1, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 16 to the first half when it shows 17.

The signal 296 shown in j is the bus signal 52 shown in d.
When the value of 6 indicates 2, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 16 to the first half when it shows 17.

The signal 297 shown in k is the bus signal 52 shown in d.
When the value of 6 indicates 3, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 16 to the first half when it shows 17.

The signal 290 shown in f is the bus signal 52 shown in d.
When the value of 6 indicates 0, 1, 2, 3, b
From the second half when the value of the bus signal 276 shown in
By the time it finishes showing 15, 6 pulses are output.

FIG. 9 shows a specific circuit example of the transmission register 60, and its timing chart is as follows.
The structure is as shown in FIGS. 2B a to e.

61 is a 9-bit serial-in/serial-out (S/S) register, which receives the map signal 386 shown in FIG. Frame 0 of the map signal 386 of a is loaded into the terminal. Next, the XCLK of d is ANDed by the AND gate 62 at the XSYN timing shown in c, and received at the clock terminal via the OR gate 63, and the 9-bit S/S register 61 receives the XCLK of c.
During XSYN, it is output from the output terminal SO of frame 0 that has already been loaded, and AND gate 6 is output.
In step 4, the XSYN of c is ANDed and outputted as the data output DOUT of e.

In the same manner, frame 1 is loaded and that frame is output as DOUT.

FIG. 10 shows a specific circuit example of the receiving register 80, and its timing chart is shown in FIGS. 2B g-l. The configuration in FIG. 10 is almost the same as the configuration in FIG. 9 except that an inverter 82 is added. The data input DIN in FIG. 10 corresponds to the map signal 386 in FIG. 9, and similarly, RCLK becomes XCLK,
RSYN corresponds to XSYN, signal 232 corresponds to 231, demapped signal 90 corresponds to data output DOUT, 9-bit S/S register 81 corresponds to 61, AND gate 83 corresponds to 62, and OR gate 84 corresponds to 63. However, the signal 233 shown in FIG. It is sent to the synchronous receiving circuit 400 as a signal 90.

FIG. 11a shows the circuit configuration of the PLL circuit 100, and 101 is an oscillator that oscillates a clock 105 of, for example, 3.072 MHz. 110 is a frequency dividing circuit, which receives this clock 105 and
The frequency is divided by 15, 16, or 17 under the control of signals 161, 162, and 163 shown in the table. signal 16
3, 162, 161 are “0”, “1”, respectively
When it shows "1", it is judged that there is a phase lag, that is, the frequency of the basic clock 121 is low, the frequency division ratio is set to 15, the frequency of the basic clock 121 is increased, and the clock is set to "1", "0", "0". ”, it is assumed that there is no phase delay or lead, and the frequency division ratio is set to 16.
When "1", "0", and "1" are shown, it is judged that the phase is leading, that is, the frequency of the basic clock 121 is high, and the frequency division ratio is set to 17.
By lowering the frequency of the basic clock 121, the basic clock 1 of 192KHz synchronized with XSYN
I got 21. This frequency dividing circuit 110 further divides the frequency of the 3.072 MHz clock 105 by 3, 4, or 5, as shown in FIG. 11b, to obtain a signal 128 with a frequency of 768 kHz. Also, frequency dividing circuit 1
10, the basic clock 121 is divided by 24 to create 8K.
A signal 126 with a frequency of Hz is obtained, and a signal 127 whose timing is different from that of the signal 128 but whose frequency is the same is output.

130 is a phase comparator circuit which receives XSYN and signals 126 and 127 and outputs XSYN and signals 126 and 127.
The phases of are compared. This comparison is performed every 125 μs, and when the phase of the signal 126 is ahead, the signal 141 is output, and when the phase is behind, the signal 142 is output, and during the period when no comparison is performed, both signals 141 and 142 are output. Both indicate "0".

In the frequency division ratio control circuit 150, the clock 105 and
Upon receiving a signal 141 representing a phase lead, a signal 142 representing a phase lag, and a signal 128, it is determined that the phase is leading when the signal 141 is "1", and the signals 163, 162, and 161 are set to "1",
“0” and “1”, and when the signal 142 is “1”, it is determined that there is a phase delay and the signals 163, 162, 16
1 as “0”, “1”, “1”, and the signals 141, 14
When both 2 are “0”, “1”, “0”,
“1” is output.

FIG. 12A shows a specific circuit example of the frequency dividing circuit 110, and FIG. 12B shows its timing chart.

111 in FIG. 12A is a hexadecimal counter, and its clock terminal is connected to the clock 1 in FIG. 12B a.
05 is applied, and the output of the carry terminal CRY is applied to the load terminal LD via the inverter 117.

Furthermore, the data terminal of this hexadecimal counter 111
D0, D1, D2, D3 are signals 161, 1, respectively
62,163 and +5V. "H" is applied, and outputs Q1 and Q2 are connected to AND gate 112 to obtain signal 129 shown at e.

When the phase is delayed, that is, the signals 163, 16
When the carry CRY is output when 2,161 is "0", "1", "1", the signal 128 shown in FIG.
The hexadecimal counter 111 applied to LD
Load the count value 11 in figure B c, count up the clock 105 in a, and check the count value.
When the count reaches 11, 14, and 15, output Q1 indicates "1", and output Q2 indicates "1" when the count number is 12 to 15, so by taking the AND, e
A signal 129 shown in FIG. Therefore, the signal 129 shown at e will show "1" when the values of Q0 to Q3 of the counter 111 at d show 14 and 15.

When the phase is advanced, that is, the signals 163, 162,
Carry when 161 is “1”, “0”, “1”
When CRY is output, the hexadecimal counter 111
Loaded with 13 of Figure 12B c, clock 105
count up and the count number is 14,
15, the output Q1 indicates “1”,
Further, since the output Q2 shows "1" when the count number is 13 to 15, the AND is performed to obtain the signal 129 shown at e.

Similarly, when there is no phase lead or lag, that is, signals 163, 162, 161 are "1", "0",
If carry CRY is output when “0”, 16
The decimal counter 111 has the count value 12 in Figure 12B c.
is loaded, counts up clock 105, and when the count reaches 13, 14, 15,
Since the output Q1 indicates "1" and the output Q2 indicates "1" when the count number is 12 to 15, the AND is performed to obtain the signal 129 shown at e.

113 and 114 are D flip-flops, a signal 129 of e is applied to the data terminal D of the flip-flop 113, a clock 105 is applied to its clock terminal via an inverter 116, and an output Q is applied to the data terminal of the flip-flop 114. applied. A clock 105 is applied to the data terminal of the flip-flop 114, and its output Q provides a signal 127 shown at f which is delayed by one cycle of the clock 105 of the signal 129 a. This signal 127 is applied to the 96-decimal counter 115, and the signal 121 whose frequency is divided into 1/4 and 1/96
A signal 126 is obtained.

FIG. 13A shows a specific circuit example of the phase comparison circuit 130, and FIG. 13B shows its timing chart.

131 to 133 are D flip-flops, and the signal 126 shown in FIG.
143 of c and 144 of d are output at its output Q and not output Q. Here, for XSYN of a, signal 12 of b
When 6 is delayed, the signal 143 of c is “0”
, and when it is progressing, it will show "1".

The signal 127 of e is connected to the flip-flop 132,1
33, and XSYN is applied to the data terminal D of the flip-flop 132 via an inverter 137. Its output is f
A signal 145 shown in FIG.
At its output Q, a signal 146 shown in g is obtained,
This is applied to the other input terminal of NAND gate 134 via inverter 138. signal 1
45 and 146 and inverting it, a signal 147 of h is obtained.

Signal 143 of c and signal 147 of h are input to NOR gate 135 to obtain signal 141 shown at i. Also, the signal 144 of d and the signal 147 of h
is applied to NOR gate 136 to obtain signal 142 shown at j. This i and j signal 14
1 and 142 both enable only data obtained from signal 126 immediately after the falling edge of XSYN.

FIG. 14A shows a specific circuit example of the frequency division ratio control circuit 150, and FIG. 14B shows its timing chart.

Reference numerals 151 to 155 are D flip-flops, and a signal 1 indicating the phase lead in FIG.
41 is applied, a signal 165 shown in b is obtained, and the signal 165 shown in b is applied to the clock 10 of e through an inverter 157.
A signal 128 indicated by f is applied to the data terminal D of the flip-flop 153 to which 5 is applied.
Its output Q is the D flip-flop 154, 155
applied to the clock terminal of

On the other hand, since the c signal 142 representing the phase delay is "0" at this point, the d signal 164, which is the output Q of the flip-flop 151, is "0". Therefore, the h and g signals 162 and 163 indicate "0" and "1", respectively, before time _t1 , and the not Q output of the D flip-flop 155 and the NAND gate 1 to which the g signal 163 is applied.
56 outputs the signal 161 shown at i and sets it to "1". This signal 161 indicates "0" before time _t1 .

After time t ₁ in FIG. 1B, the signal 12 of f
8 indicates "0", and the trailing edge of the e signal 105 applied next to the rise of this signal 128, that is, the time
At t ₂ , the signal 161 of i changes from “1” to “0”
become.

Similarly, at time _t3 , i's signal 161
changes from “0” to “1”, h signal 162 changes to “0”
The signal 163 of g changes from “1” to “0”. Comparing this state with the signal in FIG. 11b, before time _t1 , the signal 14B
Signals 163, 162, 161 in figures g, h, and i are
Since they indicate "1", "0", and "0", respectively,
This shows the state without phase control. At time _t1 to _t2 , the same signals 163, 162, 161 are
Since they respectively indicate "1", "0", and "1", they indicate a state of phase advance. Similarly, at times _t3 to _t4 , the signals indicate "0", "1", and "1", respectively, indicating a phase lag. After time _t4 , a state without phase control is shown.

FIG. 15A shows that when a data rate signal (transmission data signal SD) of, for example, 2.4 kbps, 4.8 kbps, 9.6 kbps, 19.2 kbps, etc. is received from an asynchronous terminal device, the data rate of the PCM transmission path, for example, is determined.
128kbps, 192kbps, 256kbps, 384kbps,
The circuit configuration of the mapping circuit 300 for adapting to one data rate of 1.544 Mbps, 2.048 Mbps, etc. is shown, and its timing chart is shown in FIG. 15B.

This is Figure 33 showing mapping and also Figure 34.
The F bit at bit number 0 in the figure, the SY bit, and various control signals at bit number 7, that is,
CS', CI', RS, ER and bit numbers 1 to 6
A circuit for concentrating data D0 to D23 is shown. The F bit sending circuit 310
In response to the signal 260 in Figure 5B (b), it outputs a signal 316 "1" indicating the F bit of c. Since the F bit is "0" after 1.25 ms, that is, after one multiframe, the c signal 316 indicates "0" at that time.

The SD sending circuit 320 is shown in FIG. 15B d, e, f.
In response to the signals 261 and 263 shown in
SD is sampled by clock 274 and signal 3
26 is output.

The CS' sending circuit 330 samples the transmittable signal CS' with the signal 264, and outputs the signal 336 at the timing of the signal 265 shown in FIG. 15B, j.

The CI' sending circuit 340 samples the called indication signal CI' with the signal 264 and outputs the signal 346 at the timing of the signal 267 shown in FIG. 15B (n). Here, the configuration of this CI' sending circuit 340 is as follows:
The configuration is the same as that of the CS' sending circuit 330.

The SY bit sending circuit 350 receives the signal 551 and outputs the signal 356 at the timing of the signal 271 shown in FIG. 15B k.

The RS sending circuit 360 receives the sending request signal RS, samples it with a signal 264, and outputs the signal shown in FIG. 15B.
The signal 366 is sent out at the timing of the signal 270. Here, the signal 367 constantly outputs the sampled signal RS.

The ER sending circuit 370 outputs a data terminal ready signal.
ER is sampled with signal 264, and at the timing of signal 272 shown in Figure 15B, signal 376 is sampled.
is outputting. Here, this ER sending circuit 37
The configuration of CS′ sending circuit 330 is the same as that of CS′ sending circuit 330.

Concentrator circuit 380 receives signals 316, 326 of FIG. 15B, c and g, and signals 336, 346, 35.
Concentrate 6,366,376 lines, take OR, and get the first
A map signal 386 shown in FIG. 5B p is output.

FIG. 16A shows an example of a specific circuit of the F bit sending circuit 310, and FIG. 16B is a timing chart showing waveforms of each part thereof.

Reference numeral 311 denotes a D flip-flop, and the signal 317 shown in FIG. be done. This c signal 316
and a signal 260 are ANDed by an AND gate 312 to output a c signal 316. The signal 312 of c is output every 10 frames at the start of the frame.

FIG. 17A shows an example of a specific circuit of the SD sending circuit 320, and FIG. 17B is a timing chart of signals in each part of the circuit.

S/ for 24-bit serial/parallel conversion
The P register 321 samples the transmission data SD shown in FIG.
It is loaded into a register and output in parallel. Here, the clock 274 of a has a period of 110 frames.
This is a signal that divides 125ms into 24 equal parts, which is 19.2kbps.
It has a frequency of Transmission data SD in b indicates data 0 to 23 sent from the terminal side.

A P/P that receives data in parallel from the S/P register 321 and performs 24-bit parallel-to-serial conversion.
The S register 322 loads the data received at the timing of the signal 262 shown in c, and loads the data received at the timing of the signal 262 shown in c.
At timing 61, a signal 326 of i among f, g, h, and i shown on an enlarged time axis is outputted via an AND gate 323 during a period of signal 263 of e.

Here, the repetition period of signal 263 of h is 125μs
The repetition frequency of the signal 261 of g during the period of one signal 263 of h is equivalent to 192 Kbps,
Six pieces of data are sent four times every 1.2ms at 125μs intervals.

FIG. 18A shows a specific example of the CS' sending circuit 330, and FIG. 18B is a timing chart of signals in each part of the circuit.

The send enable signal CS' of FIG. 18B b is applied to the data terminal D of the D flip-flop 331.
The signal a is applied to the clock terminal at intervals of 1.25 ms, and the output signal Q and signal c are 265 ms.
is applied to AND gate 332, and a signal 336 shown at d is output. This signal 336 indicates the timing at which the transmittable signal CS' is sent to the PCM transmission line.

The operation of this CS' sending circuit 330 is the same as that of the CI' sending circuit 340 and the ER sending circuit 370, and the ready-to-send signal CS' is called the called indication signal CI' or the data terminal ready signal ER. signal 2
65 is called signal 267 or signal 272,
output signal 336 as signal 346 or signal 3
It can be called 76 instead.

FIG. 19A shows an example of a specific circuit of the SY bit sending circuit 350, and FIG. 19B shows a timing chart of signals in each part of the circuit. Here, the signal 551 shown in FIG. 19B a and b and the signal 271 at 1.25 ms intervals are applied to the AND gate 351, and the AND gate is taken to output the signal 356 of c. This signal 356
Indicates the timing of sending the SY bit to the PCM transmission line.

FIG. 20A shows an example of a specific circuit of the RS sending circuit 360, and FIG. 20B shows a timing chart of signals in each part of the circuit.

The transmission request signal RS shown in FIG. 20B is applied to the data terminal D of the D flip-flop 361.
A signal 264 shown at a is applied to its clock terminal, and a signal 368 shown at c is outputted to its output Q. c signal 368 and b transmission request signal RS
is applied to the OR gate 363 and ORed,
Applied to data terminal D of D flip-flop 362. The a signal 264 is applied to the clock of this D flip-flop 362, and the d signal 367 is outputted to its output Q. This d signal 3
67 is the same as the transmission RS in FIG.

The signal 368 indicates the value of the previous transmission request signal RS, that is, 1.25ms ago. If the previous RS (signal 368) is "0" and the current RS is "0", the signal 367 of d is "0". 0” and the previous RS
is “0” and the current RS is “1”, signal 3
67 is "1", and if the previous RS is "1" and the current RS is "0", the signal 367 is "1", and the previous RS is "1" and the current RS is "0". If so, the signal 367 is "1". To summarize, if either the previous RS or the current RS is "1", the signal 36 indicates "1".

This signal 367 and the signal 270 of FIG. 20B e are applied to an AND gate 364 and are ANDed to output a signal 366 shown at f. This signal 36
6 indicates the timing for sending the transmission request signal RS to the PCM transmission path.

FIG. 21A shows a specific example of the concentrator circuit 380, and FIG. 21B is a timing chart of signals in each part of the circuit.

Signal 316 in FIG. 21B a, signal 326 in d,
e signal 336, g signal 346, c signal 35
6, b signal 366, and f signal 376 are applied to OR gate 381 to output a map signal 386 shown at h. Therefore, the F bit is sent out at the beginning of a multi-frame consisting of 10 frames, the data D0-5 are sent out at the next 6 bits, and the transmission request signal R is sent out at the last bit of the first frame.

In the first bit of the second frame, the SY bit is
Data D6 to D11 are sent to the next 6 bits, and a send enable signal CS' is sent to the first bit.

The first bit of the third frame is "0", the next 6 bits are data D12-17, and the last bit is the data terminal ready signal ER of signal 376 shown at f.

The first bit of the fourth frame is "0", the next 6 bits are data D18-23, and the last bit is the called indicating signal CI' of signal 346 shown in g.

This h between the 5th frame and the 10th frame
All signals 386 indicate "0". In this way, the mapping shown in FIG. 33 is executed.

Figure 22A shows, for example, 128kbps, 192kbps,
A demapped signal 90, which is a data input DIN from a PCM transmission line with a data rate of one of 256 kbps, 384 kbps, 1.544 Mbps, 2.048 Mbps, etc., is received and demapped to determine the speed of the asynchronous terminal device, for example, 2.4. kbps, 4.8kbps, 9.6kbps,
Receive data according to data speeds such as 19.2kbps
A configuration diagram of a demapping circuit 400 for transmitting RD to a terminal device asynchronously with the PCM transmission line is shown, and FIG. 22B shows a timing chart of the waveforms of each part.

The F-bit receiving circuit 410 detects the F-bit signal from the demapped signal 90 shown in FIG. It outputs a signal 501 indicating whether or not it is in a synchronized state. Here, in order to detect the F bit, the basic clock 121 and the bus signal 2
Signals 287 and 288 included in 86 are used,
The signal 287 is applied at the timing of the first bit position of each frame as shown in FIG. 22B (c). Signal 288 is applied every frame to indicate the timing for outputting bus signal 526.

The RD receiving circuit 560 samples the demapped signal 90 shown in FIG. It is outputting to the terminal side. The received data RD of g has a speed of, for example, 19.2 Kbps, which is suitable for the operation of the terminal equipment. Therefore, the received data RD repeats the same data 16 times.

In the CS receiving circuit 580, the demapped signal 90 of FIG. 22B (b) is sampled with the l signal 294, and the m transmittable signal CS is extracted. Here, the send enable signal CS is sent only when the signals 367 and 551 are both "1".

In the CI receiving circuit 595, the demapped signal 90 of FIG. 22B b is sampled with the q signal 297, and the r called call indication signal CI is extracted and sent.

In the SY bit receiving circuit 530, FIG.
The demapped signal 90 of ``h'' is sampled with the signal 289 of ``h'', and the signal 501 is
It is sent as a signal 551 only when .

The CD receiving circuit 570 samples the demapped signal 90 shown in FIG. 22B with the signal 293 of i, and outputs the result as a received carrier detection signal CD shown at k at the timing of the signal 264 of j.

The DR receiving circuit 590 operates in the same manner as the CI receiving circuit 595, and converts the signal 297 into the n signal 296 and the called indication signal CI into the p data set ready signal DR.
You can call it instead.

FIG. 23 is a diagram showing the internal configuration of the F-bit receiving circuit 410, and FIG. 23B shows a timing chart of waveforms of each part thereof. Here the second
In FIG. 3B, only the F bit of the demapped signal 90 is displayed, and all other data signals and control signals are displayed as "0".

In the frame counter 420, the basic clock 1
21 and the signal 287 of FIG. 23B a, and outputs the bus signal 440 of c. This c bus signal 440 indicates frame numbers 0 to 9,
When this frame number is 0, the signal 441 of d is output at the timing of the signal 287 of a. g
When the signal 501 of is “0”, the signal 47 shown in f
1, it is not possible to count up the bus signal 440 that is the output of the frame counter, and when it receives the signal 470 of e, it becomes possible to count up, and the signal 28 of a
Each time 7 is applied, the contents of the c bus signal 440 are counted up from 0 to 9 and then 0 again.
Return to Here, when the f signal 471 is applied, the count is not increased, and when the e signal 470 is applied, it is possible to count up.

When the g signal 501 is "1", the frame counter 420 counts up the a signal 287 and c The operation of counting the contents of the bus signal 440 from 0 to 9, then back to 0, and counting back to 9 is continued.

In the comparator circuit 450, the g signal 501 is “0”
In this case, the demapped signal 90 representing only the F bit of b is compared with the circuit state of the flip-flop in the comparison circuit 450 at the timing of the signal 441 of d, and if a match is obtained, it is determined that the F bit has been detected. Therefore, output signal 470 of e, invert the state of the internal flip-flop, and if there is a mismatch,
Since the F bit is not detected, f
The state of the internal flip-flop is not inverted.

When the signal 501 of g is "1", each time the signal 441 of d is applied, regardless of whether the demapped signal 90 representing only the F bit of b matches or does not match the state of the internal flip-flop,
The state of the D flip-flop is reversed.

In the protection circuit 480, the basic clock 121 is applied, and when the signal 471 indicating a mismatch of f is applied twice, it is assumed that synchronization has been lost and the signal 501 of g is set to "0", indicating a match. When the e signal 470 is repeatedly applied four times, the g signal 501 becomes "1", assuming that frame synchronization has been achieved. By doing so, protection is provided by preventing the signal 501 representing the synchronization state from immediately changing even if it receives noise.

The rack circuit 520 receiving the bus signal 440
The contents (frame number) of bus signal 440 of c latched at the timing of signal 288 are transferred to bus signal 52.
Send as 6.

FIG. 24A shows a specific circuit example of the frame counter 420, and FIG. 24B shows a timing chart of the waveforms of each part of the circuit.

The basic clock 121 of FIG. 24B a is applied to the clock terminal of the D flip-flop 421 via an inverter 430, the signal 287 of b is applied to its data terminal D, and the signal 442 of c is applied to its output Q. is obtained.

On the other hand, a signal 470 representing a coincidence of h is applied to the clock terminal of the D flip-flop 422 via an inverter 431, and its data terminal D is +
It is connected to 5V and becomes "1", and a signal 471 indicating a mismatch is applied to its reset terminal. When a signal 470 representing a coincidence of h is applied, a signal 445 of d of the output Q of the D flip-flop 422 becomes "1", and this state continues until a signal 471 representing a mismatch is applied. d
The g signal 445, the g signal 501, and the g signal 444 are ORed by two OR gates 428 and 429, and the output thereof is applied to the enable terminal of the decimal counter 424. When this enable terminal is "1", each time the signal 442 of c is applied to the decimal counter 424, it counts up.

Output Q0, Q1, Q2, Q3 of this counter 424
The signal 441 in FIG. 24B is obtained through the OR gate 425 and the NOR gate 426. This signal 441 indicates "1" when the frame number that is the content of the bus signal e is 0 and the signal 287 representing the beginning of the frame b is applied.
This indicates the presence of an F bit signal.

The basic clock 121 of FIG. 24Ba is applied to the clock terminal of the D flip-flop 423, and the OR gate 425 is applied to its data terminal D.
is applied, and the g signal 444 indicates "1" when the value of the e bus signal 440 is 1 to 9.
is output.

The enable terminal ENB of the count 424 to which the output of the OR gate 429 is applied becomes "1" when the signal 501 representing the establishment of frame synchronization is "1" and the signal 470 representing the coincidence of h.
is applied, and when the value of the e bus signal 440, which is the output of the counter 424, is between 1 and 9, that is, when the g signal 444 is "1".

In this way, the enable terminal ENB becomes “1”
When , the counter 424 counts up and when the content of the bus signal 440 of e reaches 9, the outputs Q _B and Q _C are applied via the respective outputs Q _A and Q _D of the counter 424 and the inverters 432 and 433. The NAND gate 427 changes the f signal 443 from "1" to "0" and applies it to the load terminal LD to load 0, and the count is counted up again.

FIG. 25A shows an example of a specific circuit of the comparison circuit 450, and FIG. 25B shows a timing chart of waveforms of each part of the circuit. Here, in FIG. 25B, only the F bit of the demapped signal 90 is displayed, and all other data signals and control signals are displayed as "0".

Since the data terminal of D flip-flop 453 is connected to its NOT output, the d signal 472 of its output Q is inverted each time signal 475 of FIG. 25B, j, applied to the clock terminal is not applied. The output Q of this D flip-flop 453
The signal 472 of d and the demapped signal 90 representing only the F bit of c are exclusive signals.
It is exclusively ORed at OR gate 458, the output of which is applied via inverter 460 to NAND gate 454 and directly to NAND gate 455. The b signal 441 is applied to these NAND gates 454 and 455, and the e signal 473 and f signal 474, which are the outputs of the NAND gates 454 and 455, are applied to the D flip-flops 451 and 455, respectively. The signal is applied to the data terminal D of 452.

These D flip-flops 451 and 45
Both clock terminals are connected to an inverter 459.
The basic clock 121 of a is applied to the output Q of the D flip-flop 451, and the signal 470 of h is applied to the output Q of the D flip-flop 452.
1 is output. Here, the h signal 470 is output ("0") when the c demapped signal 90 and the d signal 472 match, and when they do not match, the i signal 471 is output ("0").

Nott Q output of D flip-flop 452 and g
The signal 501 of j is ANDed by an AND gate 456, and its output is applied to a NOR gate 457, which is NORed with the not Q output of the D flip-flop 451 to obtain a signal 475 of j, which is
It is applied to the clock terminal of flip-flop 453. The signal 501 of g is a signal that indicates "1" when frame synchronization is established, and "0"
, and when 471 is "0", the D flip-flop 453 is not inverted. signal 50
1 is "1" and the signal 471 is "0" (when they do not match), the D flip-flop 453 is caused to be inverted. Regardless of the value of signal 501, when signal 470 is "0" (when there is a match), D flip-flop 453 is inverted.

FIG. 26A shows a specific embodiment of the protection circuit 480, and FIG. 26B shows a timing chart of waveforms at various parts thereof.

The not-Q output of D flip-flop 482 is connected to its data terminal D, its clock terminal is applied with the match signal 470 of FIG. 26B, and the b signal 502 is available at its Q output.

The b signal 502 and the a signal 470 are applied to an OR gate 488 and ORed together to obtain a c signal 503, which is applied to the up count terminal UC of the up down counter 481. The terminal A of this up-down counter 481 is set to "1" (+5V), the terminals B, C, and D are set to "0", and when "0" is applied to the load terminal LD, the output terminal Q0 becomes “1” has Q1, Q2,
Q3 is set to "0". up, down,
The down count terminal DC of the counter 481 has
d signal 471 is applied.

When the output terminal Q0 of e is "1" and all Q1 to Q3 are "0", when the signal 503 of c is applied to the up count terminal UC, the output terminal Q of e
The count value of 0 to Q3 becomes 2, and therefore the output terminal Q1 becomes "1". Next, signal 50 of c
3 changes from “1” to “0”, the NAND signal 503 is applied via the inverter 491.
The output of the gate 489 goes from "1" to "0" like the f signal 504. A D flip-flop 483 receives this f signal 504 at its data terminal D.
Now, the basic clock 121 of g is received at the clock terminal, and the signal 505 shown in h is changed from "1" to "0".
Make it. This h signal 505 is connected to the preset terminal.
The D flip-flop 485 receiving PR changes the output Q from "0" to "1" as shown by the signal 501 of i.

The not-Q output of flip-flop 483 is D
It is applied to the data terminal of flip-flop 486, and the basic clock 121 is applied to its clock terminal via inverter 492, and its output Q
At this point, a signal having a polarity opposite to the first "0" signal of the signal 506 of j is obtained, and is passed through the NOR gate 490 to become the signal 506 of j.

This j signal 506 is applied to the load terminal LD of the up-down counter 481, and in order to load the value of the terminals A to D, that is, 1, the value of the outputs Q0 to Q3 of e becomes 1 again.

A signal 47 indicating a mismatch of d is sent to the down count terminal DC of the up/down counter 481.
1 is applied, it shows the output Q0~Q3 of e, and d
When the second signal indicating "0" of the signal 471 is applied, the count value of the up-down counter 481 becomes negative, so that the borrow terminal
A signal 509 of k indicating "0" is output from BRW.

This signal 509 is applied to the data terminal of flip-flop 484, whose clock terminal has g
A basic clock 121 of 1 is applied, and a signal 507 of 1 is obtained at its not-Q output.

This l signal 507 is applied to the D flip-flop 4.
The signal 501 shown at i of the output Q changes from "1" to "0".
The l signal 507 is also applied to the data terminal D of the D flip-flop 487, whose output Q is as shown in the m signal 508. This m signal 508 is applied to a NOR gate 490 and the j signal 506
Obtain a signal indicating the second “0” of
06 is applied to the load terminal LD of the up-down counter 481 to load the value 1 set to the terminals A to D, so the values of the outputs Q0 to Q3 of e again indicate 1.

In this way, the operation of up-counting by the signal 470 of a and down-counting by the signal 471 of d continues, and when the signal 470 indicating the match of a is applied four times in a row, the count of i is The signal 501 changes from "0" to "1", and when the signal 471 indicating the mismatch of d is applied twice in succession, the signal 501 of i changes from "1" to "0".

FIG. 27 shows a specific example of the latch circuit 520. Here, the latch 521 has
A bus signal 440 representing a frame number is received at data terminals D0 to D3, and a signal 288 (FIG. 8c) is received.
Each time a signal (see FIG. 8B) is applied, outputs Q0 to Q3 are outputted as a bus signal 526 (see FIG. 8B, d).

FIG. 28A shows a specific embodiment of the SY bit receiving circuit 530, and a timing chart of waveforms of each part thereof is shown in FIG. 28B. Here, the demapped signal 90 of FIG.
represents only the SY bit, and other data signals and control signals are shown as "0".

The signal 501 is applied to the reset terminals R of the D flip-flops 531, 532, 533 via two inverters 542, 543, and the signal 50
1 is “1”, the D flip-flop 531
The demapped signal 90 of FIG. 28Bb is applied to the data terminal D of
A signal 289 of c is applied, and a signal 552 of c is obtained at its output Q. This signal 552 is applied to the data terminal D of the D flip-flop 532;
At its output terminal Q, a signal 553 of d is obtained. This signal 553 is connected to the D flip-flop 53.
3, and its output Q has e
A signal 554 is obtained.

The not-Q output of each D flip-flop 531, 532, and 533 is applied to a NOR gate 537 whose output is applied to the data terminal of a D flip-flop 534. The clock terminal of this D flip-flop 534 has a signal 289 of a.
is applied via an inverter 541, and a signal 555 shown at f is obtained at its output Q.

The Q outputs of D flip-flops 531, 532, and 533 are applied to a NOR gate 538 whose output is applied to the data terminal of D flip-flop 536. This D flip-flop 53
A signal 289 of a is applied to the clock terminal of 6 through an inverter 541, and a signal 556 of h is obtained at its output Q.

The data terminal D of the D flip-flop 535 is
"1" (+5V), and the h signal 556 and the signal 501 via the inverter 542 are applied to the reset terminal R via the NOR gate 539. Also, flip-flop 535
The signal 555 of f is applied to the clock terminal of , and when the signal 501 is "1" and the signal 556 is "0", the reset terminal R is "1", so the signal 555 of f is applied. Then, the output Q becomes "1" as shown in the signal 551 of g, and then the signals 552, 553 of c, d, e,
When all 554 become "0", the data terminal D of the flip-flop 536 becomes "1", so the a signal 289 applied to the clock terminal via the inverter 541 causes the h signal 556 to become "1". goes from "0" to "1", and this signal 556 is reset to "0" at the reset terminal R of the D flip-flop 535 via the NOR gate 539, and the signal 556 is reset to "0" at the reset terminal R of the D flip-flop 535.
The output Q of 5 changes from "1" to "0" as shown in the signal 551 of g.

When the signal 501 representing the synchronization state is "0", the reset terminal R of the D flip-flop 535
is reset to “0”, and the signal 55
1 always becomes "0".

The SY bit receiving circuit 5 shown in FIG. 28A
30, it is possible to sample 90 samples of the demapped signal representing only the SY bit in b using the signal 289 for sampling the SY bit in FIG. When the terminating device on the communication partner side
It is determined that the state has become synchronized with respect to the F bit, and the g signal 551 is changed from "0" to "1". Conversely, "0" of the demapped signal 90 representing only the SY bit of b three times in a row is changed to the signal 2 of a.
When sampled at 89, it is determined that the terminal device on the other side is no longer in a synchronized state with respect to the F bit, and the signal 551 of g is changed from "1" to "0".

FIG. 29A shows an example of a specific circuit of the RD receiving circuit 560, and FIG. 29B shows a timing chart of waveforms of each part thereof. Here, the demapped signal 90 of FIG.
represents only data signals, and all other control signals are shown as "0".

In the S/P register 561 that converts 24-bit serial input data to parallel data, the second
The demapped signal 90 representing only the data in Figure 9B (b) is received at the data input terminal DI, sampled by the signal 290 (a) applied to the clock terminal, loaded, and output in parallel as 24-bit data. This 24-bit data output in parallel is
Applied to P/S register 562 which converts parallel data to serial data.

In the P/S register 562, this parallel data is loaded with “1” of the signal 262 of c, and the data is changed to “0”.
During the interval d, the received data RD of e is sequentially outputted by the clock 275.

FIG. 30A shows an example of a specific circuit of the CD receiving circuit 570, and FIG. 30B shows a timing chart of waveforms of each part thereof. Here, the demapped signal 90 in FIG. 30B represents only the received carrier detection signal CD, and all other control signals and data signals are shown as "0".

The demapped signal 90 of FIG. 30Bb is applied to the data terminal D of the D flip-flop 571, the signal 293 of FIG. . Then signal 264 of c
is applied to the clock terminal of the D flip-flop 572, the output Q signal 576 shown at d, which was previously at "0", becomes "1". If the demapped signal 90 representing only the received carrier detection signal CD of b is “0”, then the signal 26 of c
4 is applied, the received carrier detection signal of d
Signal 576, which is CD, indicates "0". 30th B
The arrow in the figure indicates that the demapped signal 90 in b is output by the signal 576 indicated by the arrow in d.

FIG. 31 shows an example of a specific circuit of the CS receiving circuit 580. D flip-flop 581
The data terminal D of the demapped terminal 9 of FIG.
0 is applied and a signal 294 of l having a period of 1.25 ms is applied to its clock terminal, the output Q is obtained, and this output Q is applied to the AND gate 5.
82. This AND gate 582 has signals 367 (see FIG. 20B, d) and 55
1 (see Figure 28B, g) is applied, and the clear-to-send signal CS of Figure 22B, m, is obtained at its output.
The terminal that receives this starts transmission.

FIG. 32 shows an example of a specific circuit of the DR receiving circuit 590. D flip flop 591
The demapped signal 90 of FIG. 22Bb is applied to the data terminal D of
signal 296 is applied to output the p data set ready signal DR.

The specific circuit of the CI receiving circuit 595 is the 32nd
The circuit is the same as the one shown in the figure, and instead of the signal 296, the signal 297 in Figure 22B g is applied, and the called indication signal CI (its value is indicated as "0") shown at r is the data. - Output in place of the set/ready signal DR.

In this way, various signals RD, CS, CD, DR, and CI are sent out in parallel from the demapping circuit 400 to the terminal device.

[Effects of the Invention] As is clear from the above explanation, the present invention allows various speeds, such as 128 kbps,
192kbps, 256kbps, 384kbps, 1.544Mbps,
When the device of the present invention is used as a termination device for one PCM transmission line capable of transmitting at one data rate such as 2.048 Mbps, even if the transmission rate is changed,
No additional operations were required, and it became possible to transmit data in accordance with the timing of the PCM transmission line, convert the speed, and send and receive data at the speed required by the terminal, asynchronously with the PCM transmission line. Therefore, the effects of the present invention are extremely large.

[Brief explanation of the drawing]

Fig. 1A is a conceptual configuration diagram for explaining the operational concept of the present invention, Fig. 1B is a timing chart showing waveforms of each part in Fig. 1A, and Fig. 2A is an embodiment of the terminal device of the present invention. Block diagram representing 2nd B
The figures are a timing chart of the waveforms of each part in Fig. 2A, Fig. 3 is a timing chart showing the sending timing of the data terminal device, and Fig. 4 is a timing chart showing the timing of sending data from the data terminal device generated by the timing generation circuit. A timing chart showing the relationship between a timing signal and sampled data, FIG. 5, a circuit configuration diagram showing one embodiment of the timing generation circuit 200, FIGS. 6A and 6B.
7A and 7B are a circuit configuration diagram showing one embodiment of the register timing circuit 210 included in the timing generation circuit 200 of FIG. 5, and a timing chart showing the waveforms of each part thereof. A circuit configuration diagram showing one embodiment of the clock timing circuit 240 included in the timing generation circuit 200 of FIG. 5, a timing chart showing waveforms of each part, and FIGS. 8A and 8B are
A circuit configuration diagram showing one embodiment of the reception timing circuit 280 included in the timing generation circuit 200 shown in the figure, and a timing chart showing the waveforms of each part thereof. FIG. 10 is a circuit configuration diagram showing an example of the receiving register 80 in FIG. 2A, and FIG. 11 is a circuit configuration diagram showing an example of the PLL circuit 100 in FIG. 2A. and its state diagram, 12th
Figure A and Figure 12B are the PLL circuit 1 of Figure 11.
A circuit configuration diagram showing an example of the frequency dividing circuit 110 included in 00, and a timing diagram showing waveforms of each part thereof.
Chart, Figures 13A and 13B are
A circuit configuration diagram showing one embodiment of the phase comparator circuit 130 included in the PLL circuit 100 in FIG. 1, a timing chart showing waveforms of each part, and FIGS. 15A and 15B are a circuit configuration diagram showing an embodiment of the frequency division ratio control circuit 150 shown in FIG. 2A, and a timing chart showing the waveforms of each part. 16A and 16B are a timing chart showing an embodiment of the F bit sending circuit 310 in FIG. 15A and a timing chart showing waveforms of each part. 17
Figure A and Figure 17B are a circuit configuration diagram showing one embodiment of the SD sending circuit 320 in Figure 15A, and a timing chart showing waveforms of each part, and Figures 18A and 18B are CS′ sending circuit 330
A circuit configuration diagram showing an embodiment of the invention and a timing chart showing waveforms of each part, FIGS. 19A and 19
Figure B shows the SY bit sending circuit 350 of Figure 15A.
A circuit configuration diagram showing an example of the above and a timing chart showing waveforms of each part, FIGS.
FIG. B is a circuit configuration diagram showing one embodiment of the RS sending circuit 360 in FIG. 15A and a timing chart showing waveforms of each part. FIGS. 21A and 21B are one implementation of the integrated circuit 380 in FIG. 1A. FIGS. 22A and 22B are circuit configuration diagrams showing an example of the demapping circuit 400 of FIG. 2A and timing charts showing waveforms of each part. , FIGS. 23A and 23B are a block diagram showing an embodiment of the F-bit receiving circuit 410 in FIG. 22A, and a timing chart showing waveforms of each part. 25A and 25B are a circuit configuration diagram showing an embodiment of the frame counter 420 and a timing chart showing waveforms of each part. FIGS. 26A and 26B show the waveforms of the protection circuit 480 of FIG. 23A.
FIG. 27 is a circuit configuration diagram showing an example of the latch circuit 520 of FIG. 23A, and FIGS. 28A and 28B are a timing chart showing the waveforms of each part. A circuit configuration diagram showing an embodiment of the SY bit receiving circuit 530 in FIG. 22A and a timing chart showing waveforms of each part, and FIGS. 29A and 29B show an embodiment of the RD receiving circuit 560 in FIG. 22A. The circuit configuration diagram shown and the timing chart showing the waveforms of each part, Figures 30A and 30B, are shown on the CD of Figure 22A.
A circuit configuration diagram showing an embodiment of the receiving circuit 570 and a timing chart showing waveforms of each part, FIG. 31 is a circuit configuration diagram showing an embodiment of the CS receiving circuit 580 in FIG. 22A, and FIG. Figure 22A
33 and 34, which are circuit configuration diagrams showing one embodiment of the DR receiving circuit 590, are similar to timing charts, FIGS. 35, 36, and 34 showing mapping time slots for accommodating conventional control signals and data. FIG. 37 is a conceptual configuration diagram of a conventional transmission system,
FIG. 38 is a timing chart for explaining the operations in FIGS. 36 and 37, and FIG. 39 is a circuit configuration diagram for delaying signals used in FIGS. 36 and 37. 5A, 5B...Terminal device, 8...PCM exchange switch, 60...Transmission register, 61...9-bit S/S
Register, 62...and gate, 63...or
Gate, 64...and. Gate, 80... Reception register, 81... 9-bit S/S register, 82... Inverter, 83... AND gate, 84... OR
gate, 85...and gate, 90...signal to be demapped, 100...PLL circuit, 101...oscillator,
105... Clock, 110... Frequency dividing circuit, 111...
Hex counter, 112...and gate, 11
3,114...D flip-flop, 115...96 base counter, 116,117...inverter, 121
...Basic clock, 126-129...Signal, 130
...Phase comparator circuit, 131-133...D flip-flop, 134...NAND gate, 135, 13
6...NOR gate, 137, 138...Inverter, 141-147...Signal, 150...Division ratio control circuit, 151-155...D flip-flop, 1
56...NAND gate, 157...Inverter, 1
61-165...Signal, 200...Timing generation circuit, 210...Register timing circuit, 211
...24-decimal counter, 212, 213...D flip-flop, 214-217...AND gate, 21
8-220...Inverter, 231-235...Signal, 240...Clock timing circuit, 241
…8-stage S/P register, 242…24-decimal frame・
Counter, 243...Decimal multi-frame counter, 244...Decoder, 245...Flip-flop group, 246, 247...Decoder, 248...10
decimal counter, 249, 250...and gate,
251-253...Inverter, 258...Signal, 2
59...Bus signal, 260-267, 270-27
3... Signal, 274, 275... Clock, 276,
277...Bus signal, 278,279...Signal, 28
0...Reception timing circuit, 281...Decoder,
282...Flip-flop group, 283...Inverter, 286...Bus signal, 287-290, 29
3,294,296-298...signal, 300...mapping circuit, 310...F bit sending circuit, 31
1...D flip-flop, 312...AND gate, 313...inverter, 316, 317...signal, 320...SD sending circuit, 321...S/P register, 322...P/S register, 323...AND gate, 326...signal , 330...CS' sending circuit, 331...D flip-flop, 332...AND gate, 336...signal, 340...CI' sending circuit, 346...signal, 350...SY bit, 351
...and gate, 356...signal, 360...RS
Sending circuit, 361, 362...D flip-flop, 363...OR gate, 364...AND gate, 366-368...signal, 370...ER sending circuit, 376...signal, 380...integrated circuit, 381
...OR gate, 386...Map signal, 400...
Demapping circuit, 410...F bit receiving circuit,
420...Frame counter, 421-423...
D flip-flop, 424...Counter, 425
…Or Gate, 426…Noah Gate, 427
7... NAND gate, 428, 429... OR gate, 430-433... Inverter, 440... Bus signal, 441-445... Signal, 450... Comparison circuit, 421-453... D flip-flop, 45
4,455...Nand Gate, 456...and
Gate, 457...Nor gate, 458...Exclusive or gate, 459, 460...Inverter, 470-475...Signal, 480...Protection circuit, 481...Up/down counter, 48
2-487...D flip-flop, 488...OR gate, 489...NAND gate, 490...
Noah Gate, 491,492...Inverter, 5
01-509...Signal, 520...Latch circuit, 52
1...Latch, 526...Bus signal, 530...SY bit receiving circuit, 531-536...D flip-flop, 537-539...NOR gate, 541-
543...Inverter, 551-556...Signal, 5
60...RD receiving circuit, 561...S/P register,
562...P/S register, 570...CD receiving circuit,
571, 572...D flip-flop, 576...
Signal, 580...CS receiver circuit, 581...D flip-flop, 582...AND gate, 590...
DR receiving circuit, 591...D flip-flop, 5
95...CI receiving circuit, CD...receiving carrier detection signal,
CI, CI′...Called display signal, CS, CS′...Send ready signal,
DIN…data input, DOUT…data output, DR…
Data set ready signal, ER...data terminal ready signal, _L1 , _L2 ...transmission/reception line, RCLK...reception clock, RD...reception data, REG _a , REG _b ...24
Stage shift register, RS...Transmission request signal, RSYN
…Reception synchronization signal, SD…Transmission data, XCLK…Transmission clock, XSYN…Transmission synchronization signal.

Claims (1)

[Claims] 1. Accommodating data and control signals in a multi-frame configuration and transmitting PCM synchronization signals (RSYN, XSYN)
and PCM clock signals (RCLK, In a terminal device 5 for connecting an asynchronous data terminal device that operates at a speed lower than the transmission speed of any one line, the terminal device receives data SD and control signals RS, CS from the data terminal device. ', ER, CI' are mapped according to a predetermined procedure to form a multi-frame and mapped signal 3
mapping means 300 for outputting 86; and a mapping means 300 for temporarily storing the map signal from the mapping means, and transmitting the map signal on the PCM transmission line at the timing of the PCM synchronization signal and the PCM clock signal of the PCM transmission line. transmission register means 60 for transmitting data to the PCM transmission line at a transmission speed of the PCM transmission line; a reception register 80 for storing the demapped signal 90 at a predetermined timing synchronized with the PCM synchronization signal; Demapping means 40 for sending to the device
0 and a basic clock 1 synchronized with the PCM synchronization signal.
PLL means 100 having a phase lock loop for generating 21; and the basic clock generated by the PLL means;
Timing generation means 200 for sending a required timing signal from the PCM synchronization signal and the PCM clock signal to the transmission register means, the reception register means, the mapping means, and the demapping means. A terminal device characterized by: 2. The terminal device according to claim 1, wherein the transmission register means includes a register 61 that receives data and outputs data. 3. The terminal device according to claim 1, wherein the reception register means includes a register 81 that receives data and outputs data. 4. The PLL means includes: oscillation means 101 for generating a PLL clock 105 having a higher repetition frequency than the basic clock; and a phase control signal 161,1 for generating the PLL clock.
frequency division means 110 for obtaining the basic clock by dividing the frequency at a frequency division ratio indicated by 62, 163;
and the phase of the frequency dividing operation in the frequency dividing means and the phase of the frequency dividing operation in the frequency dividing means.
Comparison result 14 by comparing the phase of the PCM synchronization signal
Phase comparison means 130 for outputting 1,142
2. The termination device according to claim 1, further comprising: a frequency division ratio control means 150 for receiving the comparison result from the phase comparison means and outputting the phase control signal. 5. F bit sending means 310 for the mapping means to send at least bits 316 representing a frame; and data sent from the data terminal device.
Terminal device according to claim 1, comprising: SD sending means 320 for sending SD; and RS sending means 360 for sending a transmission request signal RS sent from the data terminal device. . 6. F bit receiving means 410 for the demapping means to receive at least F bits representing a frame in the demapped signal 90;
RD receiving means 560 for receiving the data in the demapped signal; and CD receiving means 570 for receiving the received carrier detection signal in the demapped signal. Terminal device as described in section. 7. The mapping means includes an F bit sending means 310 for sending F bits 316 representing a frame, and data 3 sent from the data terminal device.
SD sending means 320 for sending out the signal 26; and CS' sending means 330 for sending the ready-to-send signal 336 sent from the data terminal device.
and CI' sending means 340 for sending a called indication signal 346 sent from the data terminal device.
and SY bit 35 indicating that synchronization has been established.
SY bit sending means 350 for sending 6, and RS sending means 360 for sending a transmission request signal 366 sent from the data terminal device.
ER sending means 370 for sending out a data terminal ready signal 376 sent from the data terminal device; an output of the F bit sending means; an output of the SD sending means; and an output of the SD' sending means. Output and the above
The output of the CI' sending means, the output of the SY bit sending means, the output of the RS sending means, and the output of the ER sending means are condensed to generate the map signal 386.
3. The termination device according to claim 1, further comprising a line concentrating means 380 for sending out the line. 8. The demapping means includes: F bit receiving means 4 for receiving F bits representing a frame in the demapped signal 90;
10, RD receiving means 560 for receiving data in the demapped signal, CS receiving means 580 for receiving a send clear signal in the demapped signal, and a called indication in the demapped signal. CI receiving means 595 for receiving a signal; SY bit receiving means 530 for receiving a SY bit indicating that synchronization in the demapped signal has been established; and a SY bit receiving means 530 for receiving a received carrier detection signal in the demapped signal. 2. The terminal device according to claim 1, further comprising: a CD receiving means 570 for receiving the data set ready signal in the demapped signal; and a DR receiving means 590 for receiving the data set ready signal in the demapped signal. 9. Register timing means 210 for receiving the basic clock 121 and a signal 273 representing a frame and transmitting a timing signal to the transmitting register means and the receiving register means; and the basic clock 121. , a mapping clock 274 for receiving the PCM synchronization signal XSYN and the PCM clock signal XCLK and applying it to the mapping means; a timing signal 259 for instructing a mapping position; and a demapping signal for applying to the demapping means. a timing signal 259 indicating the demapping position, and a signal 25 indicating the position of each bit in the frame in the mapping means.
a clock timing means 240 for outputting the basic clock and a signal 27 indicating the position of each bit in the frame in the mapping means;
6, and a reception timing means 280 for receiving a signal 526 indicating the position of a frame in the signal to be demapped and outputting a signal 286 indicating the position of each bit in the frame in the demapping means. A terminal device according to claim 1, which comprises: 10 the F bit receiving means receives the basic clock 121 and a signal 287 indicating the interval between frames in the demapped signal 90;
A frame for receiving a signal 470 representing a match, a signal 471 representing a mismatch, and a signal 501 representing a synchronization state, and outputting a frame number and a signal 440 representing a time point at which a specific number of the frame is output. - counter means 420, the demapped signal, and the basic clock;
A signal representing the synchronization state and a signal 44 representing that a specific number of the frame has been output.
1, and includes flip-flops 451 and 452 that change their states each time they receive a signal indicating that a specific number of the frame has been output;
a comparing means 450 for comparing the state of the flip-flop and the signal to be demapped, and outputting a signal 470 representing the match when they match, and outputting a signal 471 representing the mismatch when they do not match; receiving the clock, the signal representing the coincidence, and the signal representing the mismatch, and outputting the signal representing the synchronized state when a predetermined number of the signals representing the coincidence are received in succession, and the signal representing the synchronization state is output, and the signal representing the mismatch is output. Claim 8, further comprising a protection means 480 for protecting the synchronization state by not outputting the signal 501 representing the synchronization state when a predetermined number of signals are consecutively received. Termination device as described.