JPH0584113B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a receiver for high-definition television signals, and in particular converts a high-definition television signal that has been band-compressed and sent to the original high-definition television signal by image interpolation. The present invention relates to a signal processing circuit suitable for decoding.

[Background of the Invention] As an example of a high-definition television signal and a receiver for decoding this high-definition television signal, the “High-Definition Television Satellite” by Ninomiya, Otsuka, and Izumi in TV Society Technical Report, TEBS95-2, March 1984, There is a method discussed in the document entitled "One Channel Transmission System (MUSE)".

As stated in the document, this system transmits broadband high-definition television signals at 4:1 in 4 fields.
This method uses sub-Nyquist sampling to compress the bandwidth to about 1/4 before transmitting it.

1a in FIG. 1 shows an example of a high-definition television signal that is transmitted after being band-compressed. In this way, the band-compressed high-definition television signal consists of a luminance signal whose time axis is not compressed, a line-sequential color difference signal whose time axis is compressed to 1/4, and positive horizontal synchronization signals 1 and 2 in one horizontal period. It is a multiplexed signal format. However, the multiplexing order of the color difference signals may be reversed.
With this signal format, it is not possible to insert a color difference zero level reference signal, and when decoding a color difference signal compressed in the time axis and returning it to the original time axis, the color difference zero level cannot be restored, resulting in poor hue reproducibility. This causes the problem of deterioration.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems of the conventional example, and to accurately decode a color difference signal that is time-base compressed and time-division multiplexed into a luminance signal into the original color difference signal that is not time-compressed. An object of the present invention is to provide a high-definition television receiver capable of restoring hue.

[Summary of the invention]

In order to achieve the above object, in the present invention, an AGC circuit (automatic gain control circuit) is installed at the front stage of an A/D converter (analog-digital converter) that digitizes the sent time-division multiplexed signal for high-definition television. )
is installed to control the amplitude of the synchronization signal (including frame pulse and horizontal synchronization signal) of the time division multiplexed signal for high-definition television so that it is constant. A clamp circuit is provided, and the color difference zero level is approximately the center value of the quantization number in digitization with an A/D converter (for example, the quantization number in 8-bit quantization is 256, and the center value is 128). Clamp the sync signal so that

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an embodiment of a decoder circuit for high-definition television signals in a receiver according to the present invention. FIG. 1 shows the original luminance signal Y on the time axis and the color difference signals RY, B after the band-compressed high-definition television signal is widened by image interpolation according to the embodiment shown in FIG.
FIG. 6 is a time chart showing that the data is decoded into -Y. In addition, Figure 3 shows the frame pulse of a band-compressed high-definition television signal and the horizontal synchronization signal HD.
This is an example of a positive synchronization signal consisting of

In Figure 2, 6 is an input terminal for band-compressed high-definition television signals, 7 is an AGC circuit, 8 is a clamp circuit, 9 is an A/D converter that digitizes the analog signal, and 10 is approximately 1/4 This is a circuit that digitally interpolates a band-compressed high-definition television signal by sub-Nyquist sampling, and the signal whose band-band has been compressed to 1/4 by this image interpolation circuit 10 is the original wide-band high-definition television signal. will be returned to. 11 is a circuit for separating the positive polarity synchronization signal and other control signals shown in FIG. 3;
A clock generator 2 generates a clock signal phase-synchronized with the frame pulse from the synchronization separation circuit 11. Here, the frame pulse is included in the synchronization signal as shown in Fig. 3, and for example, as shown in the figure, the polarity is reversed between line 3a and the next line 3b, and the amplitude level is 0. ~
100IRE, and the frequency is chosen to be an integer multiple of the horizontal frequency _H. 13 surrounded by a broken line is a decoder circuit that returns a time-division multiplexed signal for high-definition television, in which the color difference signal is time-base compressed and multiplexed, to its original time base; 14 and 15 are each one-line random memories; 16- 18 is a D/A converter that converts a digital signal into an analog signal, 19 to 21 are output terminals, and the terminals 1f, 1g, 1 in FIG.
The decoded luminance signal Y, red difference signal RY, and blue difference signal B-Y shown in h are derived. 22 is a circuit for separating the audio and additional information multiplexed during the vertical blanking period, 23 is a circuit for processing the separated audio and additional information, and 24 is an output terminal for the processed audio and additional information.

The feature of this embodiment in FIG. 2 is that an AGC circuit 7 and a clamp circuit 8 are provided before the A/D converter 9.
The amplitude level of the synchronizing signal shown in FIG. 3 obtained in FIG. In this case, the frame pulse is selected as the reference signal of the AGC circuit 7 as a synchronization signal, and the amplitude level is 0 to 100IRE.
By always setting the dynamic range of the A/D converter and digitally applying feedback to the AGC circuit 7 so that 0IRE becomes "00000001" and 100IRE becomes "11111110" at 8 bits, the S/N can be optimized. Clamping is also performed using this frame pulse, and by digitally controlling the clamp circuit with feedback so that, for example, 0IRE becomes "00000001", the gray level 50IRE is set as the center value of the quantization number. By doing this, for example, when the color difference signal compressed in the time axis by the time-division multiplexed signal decoder 13 surrounded by the broken line is expanded to the original time axis, the zero level of color difference in the horizontal blanking period can be easily restored. can do. This will be explained below in Section 1.
This will be explained in detail using figures.

Both the band-compressed high-definition television signal from the input terminal 6 and the wide-band high-definition television signal from the image interpolation circuit 10, the color difference signal is time-axis compressed to, for example, 1/4 and becomes a luminance signal, as shown in 1a. Time division multiplexed. This time division multiplexed signal is transferred to the RAM
114 is, for example, 1b's 1920 _H write frequency and 1
A clock CLK consisting of a readout frequency of 480 _H
1 for writing and reading, RAM215
The D/A converter 17 is written and read by clock CLK2, which has a write frequency of 1920 _H for 1c and a read frequency of 480 _H for 1e.
and 18, color difference signals R-Y and B-Y whose time axes are expanded by 1g and 1h are obtained. The problem here is color difference zero levels 4 and 5, but this can be easily solved by setting the digital data in the pedestal period other than the readout period of RAM114 and RAM215 to the gray level of the center value of the quantization number. Can be restored.

For luminance signals that are not subjected to time axis expansion processing, for example, the horizontal synchronization signals HD1 and HD2 and the color difference signal multiplexing period are replaced with the minimum level (for example, "00000000" for 8 bits) at the input of the D/A converter. By doing so, the pedestal level of the luminance signal 1f from the D/A converter 16 can be set to 0IRE as shown in the figure.

As described above, by using the present invention, high-definition television signals sent with band compression can be
It is possible to decode at an optimal level, and to accurately and easily restore a color difference zero level signal, thereby improving hue reproducibility during decoding.

In the above embodiment of the present invention, a case has been described in which the frame pulse shown in FIG. 3 is used as the amplitude level detection signal of the AGC circuit 7, and the frame pulse is also used as the clamp signal. However, for example, in 4a where the synchronization signal is N lines before the frame pulse as shown in Fig. 4, the synchronization signal is at the 100IRE level (N
+1) When line 4b is at the 0IRE level, the AGC circuit 7 peak-detects the frame pulse front stage of line 4a, and this level is
The amplitude can be controlled to be 100IRE.
In this case, peak detection becomes easy. Also, (N
+1) Before the frame pulse of line 4b
0IRE can be clamped and made the minimum input of the A/D converter 9. In this case, clamping becomes easier.

Next, a case where a synchronizing signal for controlling the amplitude level of the AGC circuit 7 is detected in an analog manner at a stage before the A/D converter 9, unlike the embodiment shown in FIG. 2, will be described.

FIG. 5 shows an embodiment of the present invention in this case. A feature of this embodiment is that a synchronization signal amplitude level detector 25 is provided at the next stage of the AGC circuit 7, and detects the synchronization signal using, for example, a gate pulse for the synchronization signal from the synchronization and control signal separation circuit 12. The gate of the detector 25 is opened and peak detection is performed. In this case, the peak detection of the synchronizing signal can be performed in an analog manner, and the circuit system can be simplified. The same effect can be obtained even if the detector 25 is provided at the next stage of the clamp circuit 8.

Furthermore, in the embodiment shown in FIG. 5, the audio and additional information separation circuit 22 is provided at the subsequent stage of the AGC circuit. In this case, the amplitude level of the digitized audio signal and additional information can be optimized, and data detection errors can be reduced. This audio and additional information separation circuit 22
It is also possible to provide the AGC circuit 7 subsequent to the AGC circuit 7 in the embodiment shown in FIG.

Furthermore, an embodiment in FIG. 5 shows a case where a synchronization signal generator 26 is provided. This is because the synchronization signal of the band-compressed high-definition television signal from the input terminal 6 is of positive polarity, and the synchronization signal indicating the frame period has only two lines, for example, as shown in FIGS. 3 and 4. This is to restore a normal synchronization signal by the synchronization signal generator 26 and output it from the output terminal 28 together with the decoded luminance signal Y and color difference signals R-Y, B-Y.

In the embodiments of the present invention described above, sufficient effects can be obtained when there is no sag equal to or less than the frame period in the band-compressed high-definition television signal from the input terminal 6. However, for example, if the transmitted high-definition television signal has a sag equal to or less than the frame period, the above-described embodiments of the present invention may not provide sufficient performance. That is, it becomes impossible to accurately detect the zero-crossing point of the horizontal synchronizing signal HD of positive polarity for each line from the frame pulse shown in FIG. 3 or FIG. 4, and normal decoding cannot be performed.
Further, the color difference zero level varies, for example, with a frame period, causing a hue error.

The above problem can be solved by using the present invention and, for example, by digitally detecting the level of the horizontal synchronizing signal HD every horizontal period as follows, and by using the clamp circuit 8 shown in the embodiments of FIGS. 2 and 5. This can be solved by feedback and controlling the clamp level in horizontal cycles.

FIG. 6 is an explanatory diagram of this embodiment, and 6a is a band-compressed high-definition television signal 6b with sag.
is the pulse that detects the horizontal synchronization signal HD, and 6c is 6
The sag 6d is a clamp level control signal that is fed back to the clamp circuit 8. By feeding back this clamp level control signal 6d, the clamp level of the high-definition television signal 6a with sag is controlled line by line, and a high-definition television signal without sag can be obtained as shown in 6e. This makes it possible to accurately detect the horizontal synchronizing signal HD of positive polarity for each line, allowing normal decoding.
Naturally, the zero color difference level can be accurately restored and hue errors can be suppressed.

Next, a method for more accurately detecting the level of the horizontal synchronizing signal HD for each line will be described.

FIG. 7 shows an embodiment of the present invention that enables more accurate level detection of the horizontal synchronizing signal HD.
The figure is an explanatory diagram of the operation. In FIG. 7, 28 is a one-line delay line (semiconductor delay line such as a shift register or RAM), 29 is a circuit for adding the horizontal synchronization signal HD' of the previous line and the current horizontal synchronization signal HD, and the others are second-line delay lines. It is the same as FIG.
Further, in FIG. 8, 8a indicates one line period, 8b is a high-quality television signal input to the A/D converter 9, 8c is a horizontal synchronization signal HD detected by the synchronization separation circuit 11, and 8d is a horizontal synchronization signal HD detected by the synchronization separation circuit 11. 1 line delay line 2
This is the horizontal synchronization signal HD' from 8. In this way, by digitally adding, for example, the current horizontal synchronizing signal HD8c and the horizontal synchronizing signal HD'8d of one line before in the adder 29, a horizontal synchronizing signal of gray level (50IRE) as shown in 8e is obtained. be able to. In this case, unlike the horizontal synchronizing signal of 8c or 8d, the obtained horizontal synchronizing signal becomes flat at the level of 50 IRE, making level detection easy. In addition, since it is added to the phase-inverted horizontal synchronization signal from one line before, the S/N is improved. Especially for waveform distortion, since signals with different distortion directions are added, the accuracy of horizontal synchronization signal level detection is improved. do.

The horizontal synchronization signal 8e obtained in this way is
For example, it is also possible to expand the time axis together with the time axis compressed color difference signal and use it as a color difference zero level signal.

〔Effect of the invention〕

By using the present invention, a high-definition television signal in which a band-compressed and time-base compressed color difference signal and a positive horizontal synchronization signal are time-division multiplexed on a luminance signal is decoded into the original signal. ,
In addition to improving the S/N and decoding performance, in particular, the zero color difference level can be easily and accurately restored, and the reproducibility of hue can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the operation of decoding a time-division multiplexed high-definition television signal to the original time axis, FIG. 2 is a block diagram showing an embodiment of the decoding circuit of the receiver of the present invention, and FIG. The figure is a waveform diagram showing an example of a synchronization signal of a high-definition television signal.
A waveform diagram showing an example of 100 IRE and 0 IRE, Fig. 5 is a block diagram showing an embodiment of the present invention different from Fig. 2, and Fig. 6 controls the clamp level by feeding back the horizontal synchronization level to the clamp circuit. FIG. 7 is a block diagram showing an embodiment of the present invention that can improve horizontal synchronization signal level detection; FIG. 8 is a waveform diagram showing an explanation of the operation of FIG. 7. . Explanation of symbols, 1, 2...Horizontal synchronization signal, 4, 5
...Color difference zero level reference signal, 7...AGC circuit,
8... Clamp circuit, 9... A/D converter, 10
...Image interpolation circuit, 11...Synchronization and control signal separation circuit, 12...Clock generator, 1
3...Time division multiplexed signal decoder circuit, 16-18
...D/A converter, 25...Synchronization level detector,
28...1 line delay line, 29...adder.

Claims (1)

[Claims] 1. A signal obtained by time-division multiplexing of at least a band-compressed video signal and a time-axis compressed line-sequential color difference signal, a luminance signal, a positive horizontal synchronization signal, and a positive vertical synchronization signal. In the device that demodulates the video signal to the original video signal that has not been compressed in the time axis, an A/D converter converts the analog signal into a digital signal.
It includes a D converter, a decoding circuit that digitally restores the video signal to the original wideband signal, and a D/A converter that converts the digital signal restored to the original wideband video signal into an analog signal. In addition, an automatic gain control circuit operates to keep the amplitude level of the synchronization signal or a line containing the synchronization signal constant at the stage before the A/D converter, and clamps the synchronization signal to a constant DC voltage level. A high-definition television receiver characterized by comprising a clamp circuit. 2 The automatic gain control circuit provided before the A/D converter is configured to control the amplitude level of the frame synchronization signal or the line containing the frame synchronization signal digitally detected after the A/D converter. The high-definition television receiver according to claim 1, wherein the high-definition television receiver is controlled to be constant. 3. Claim 1, wherein the clamp circuit provided before the A/D converter performs clamp control for each cycle of the horizontal synchronization signal.
The high-definition television receiver according to item 1 or 2. 4 The clamp circuit provided at the front stage of the A/D converter performs clamp control for each cycle of the horizontal synchronization signal, and also controls the DC voltage level of the horizontal synchronization signal that is digitally detected at the rear stage of the A/D converter. 3. A high-definition television receiver according to claim 1 or 2, wherein the high-definition television receiver is controlled to a certain constant level. 5 DC voltage level detection of the horizontal synchronization signal digitally detected at the subsequent stage of the A/D converter,
5. The high-definition television receiver according to claim 4, wherein the horizontal synchronizing signals of two adjacent lines are obtained by addition means.