JPH0582792A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0582792A JPH0582792A JP3243910A JP24391091A JPH0582792A JP H0582792 A JPH0582792 A JP H0582792A JP 3243910 A JP3243910 A JP 3243910A JP 24391091 A JP24391091 A JP 24391091A JP H0582792 A JPH0582792 A JP H0582792A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- trench groove
- forming
- semiconductor substrate
- distance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims description 14
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 abstract description 3
- 239000007943 implant Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 244000228957 Ferula foetida Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- -1 nitrogen nitride Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
- H10D62/107—Buried supplementary regions, e.g. buried guard rings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/156—Drain regions of DMOS transistors
- H10D62/157—Impurity concentrations or distributions
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に係わり、特に、トレンチ溝を用いる縦型MOS FET の製
造に利用するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a vertical MOS FET using a trench groove.
【０００２】[0002]
【従来の技術】従来から縦型MOS FET にあっては、図１
に示す断面図のようにＮ型のシリコン半導体基板１に形
成するいわゆるトレンチ溝２を利用した型も採用してい
る。即ち、不純物としてＳｂを導入したＮ型のシリコン
半導体基板１にＮ層３を形成する。これは、不純物とし
て５×１０15／ｃｃ程度のＰを含有するＮ層３であり、
ここにドーズ量が１０13／ｃｍ2 位のＢをイオン注入し
てＰ層４を形成して、トランジスタのベース層として機
能させ、更にその表面付近にＮ層５を形成する。この表
面には、シリコン酸化物層、窒化珪素層または酸窒化珪
素層などで構成する絶縁物層７を被覆後、公知のフォト
リソグラフィ技術を利用するドライプロセス例えばＲＩ
Ｅ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）法に
よる異方性エッチングによりトレンチ溝２を、トランジ
スタのベース層として機能するＰ層４よりＮ層３に達す
る深さに形成する。2. Description of the Related Art Conventionally, a vertical MOS FET has been shown in FIG.
As shown in the cross-sectional view of FIG. 3, a mold utilizing a so-called trench groove 2 formed in the N-type silicon semiconductor substrate 1 is also adopted. That is, the N layer 3 is formed on the N type silicon semiconductor substrate 1 into which Sb is introduced as an impurity. This is the N layer 3 containing P of about 5 × 10 15 / cc as an impurity,
B having a dose amount of about 10 13 / cm 2 is ion-implanted therein to form a P layer 4, which functions as a base layer of the transistor, and an N layer 5 is formed near the surface thereof. This surface is covered with an insulator layer 7 formed of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like, and then a dry process using a known photolithography technique, for example, RI.
The trench groove 2 is formed to a depth reaching the N layer 3 from the P layer 4 functioning as the base layer of the transistor by anisotropic etching by the E (Reactive Ion Etching) method.
【０００３】トレンチ溝２の壁面とＮ層５表面を被覆す
る絶縁物層６には、公知のフォトリソグラフィ技術によ
り図示しない窓または孔部（トレンチ溝に対応する）を
形成後、導電性金属層例えばソース電極７やゲート電極
８更にＮ型のシリコン半導体基板３の裏面にドレイン電
極９を形成して、縦型ＭＯＳ−ＦＥＴを得る。実際に
は、この外に他の工程を施すが、本発明に直接関係しな
いので省略する。A window or hole (not shown) (corresponding to the trench groove) (not shown) is formed in the insulator layer 6 covering the wall surface of the trench groove 2 and the surface of the N layer 5 by a known photolithography technique, and then a conductive metal layer is formed. For example, the source electrode 7, the gate electrode 8 and the drain electrode 9 are formed on the back surface of the N-type silicon semiconductor substrate 3 to obtain a vertical MOS-FET. Actually, other steps are performed in addition to this, but they are omitted because they are not directly related to the present invention.
【０００４】[0004]
【発明が解決しようとする課題】図１に示した縦型ＭＯ
Ｓ−ＦＥＴでは、ゲート・ソースとドレイン間の耐圧
は、ｎ層３、５とｐ層４を最適条件で形成しても、トレ
ンチ溝２底部のコーナ部Ａに電界が集中する度合いで決
定することになる。しかし、トレンチ溝２底部のコーナ
Ａの形状は、縦型ＭＯＳ−ＦＥＴの機種に依存する程度
が大きく簡単に変えられない。従って、縦型ＭＯＳ−Ｆ
ＥＴの耐圧は、このコーナ部Ａに大きく依存した上に、
向上させることができない。[Problems to be Solved by the Invention] The vertical MO shown in FIG.
In the S-FET, the breakdown voltage between the gate and the source and the drain is determined by the degree to which the electric field is concentrated in the corner portion A at the bottom of the trench groove 2 even if the n layers 3 and 5 and the p layer 4 are formed under the optimum conditions. It will be. However, the shape of the corner A at the bottom of the trench groove 2 largely depends on the model of the vertical MOS-FET and cannot be easily changed. Therefore, the vertical MOS-F
The withstand voltage of ET largely depends on the corner portion A, and
Cannot be improved.
【０００５】本発明は、このような事情により成された
もので、特に、ゲート・ソースとドレイン間の耐圧を上
げることを目的とするものである。The present invention has been made under such circumstances, and it is an object of the present invention to increase the breakdown voltage between the gate and source and the drain.
【０００６】[0006]
【課題を解決するための手段】第１導電型を示す半導体
基板にｐｎ接合を形成する工程と，前記ｐｎ接合を貫い
て半導体基板内部に達するトレンチ溝を形成する工程
と，前記トレンチ溝内部を被覆する絶縁物層を形成する
工程と，前記絶縁物層に隣接する電極を形成する工程
と，前記トレンチ溝底部との距離がほぼ一定の空乏層を
形成する手段に本発明に係わる半導体装置の製造方法の
特徴がある。A step of forming a pn junction in a semiconductor substrate showing a first conductivity type, a step of forming a trench groove penetrating the pn junction and reaching the inside of the semiconductor substrate, and a step of forming a trench groove in the trench groove The step of forming an insulating layer to cover, the step of forming an electrode adjacent to the insulating layer, and the means of forming a depletion layer having a substantially constant distance from the bottom of the trench groove are used in the semiconductor device according to the present invention. There is a feature of the manufacturing method.
【０００７】[0007]
【作用】第１導電型を示す半導体基板に形成するｐｎ接
合を貫いてトレンチ溝を形成する半導体素子例えば縦型
ＭＯＳ−ＦＥＴの耐圧を向上するに当たって，トレンチ
溝底部との距離がほぼ一定の空乏層を形成する手段とし
て例えばＰ層をトレンチ溝底部に設置することにより、
トレンチ溝底部における電界集中を緩和することができ
更に、耐圧が向上する事実を基に本発明は、完成したも
のである。In improving the breakdown voltage of a semiconductor device, such as a vertical MOS-FET, having a trench groove formed through a pn junction formed in a semiconductor substrate having the first conductivity type, depletion with a substantially constant distance from the bottom of the trench groove is performed. As a means for forming a layer, for example, by providing a P layer at the bottom of the trench groove,
The present invention has been completed based on the fact that the electric field concentration at the bottom of the trench groove can be relaxed and the breakdown voltage is improved.
【０００８】[0008]
【実施例】本発明に係わる実施例を図２乃至図４を参照
して説明する。なお従来と同じ部品には同一番号を付け
る。Embodiments of the present invention will be described with reference to FIGS. The same parts as in the past will be given the same numbers.
【０００９】図２に明らかなように、Ｓｂを〜２×１０
18／ｃｃ程度含有する半導体基板１に、ρが０．８〜１
Ωｃｍ（５×１０15／ｃｃ）でＰを不純物として含む第
１ｎ層３を例えばエピタキシャル法により堆積してから
更に、第１ｐ層４及び第２ｎ層５を例えばイオン注入法
により形成する。As is apparent from FIG. 2, Sb is ˜2 × 10
Ρ is 0.8 to 1 in the semiconductor substrate 1 containing about 18 / cc.
A first n layer 3 containing P as an impurity at Ωcm (5 × 10 15 / cc) is deposited by, for example, an epitaxial method, and then a first p layer 4 and a second n layer 5 are further formed by, for example, an ion implantation method.
【００１０】イオン注入による第１ｐ層４の形成におい
ては、Ｂのドーズ量がほぼ１０13／ｃｍ2 加速電圧５０
ＫｅＶ、第２ｎ層５は、Ａｓのド−ズ量が２×１０15／
ｃｍ2 加速電圧４０ＫｅＶの条件で形成する。なお、イ
オン注入工程後、公知の加熱工程を行うのは勿論であ
る。In the formation of the first p-layer 4 by ion implantation, the dose amount of B is approximately 10 13 / cm 2 accelerating voltage 50
KeV, the second n layer 5 has an As dose of 2 × 10 15 /
It is formed under the conditions of a cm 2 acceleration voltage of 40 KeV. Of course, a known heating step is performed after the ion implantation step.
【００１１】このような処理を終えた半導体基板１表面
には、絶縁物層６を厚さ５００〜１０００オングストロ
ーム被覆後、異方性エッチング法例えば反応性イオンイ
オンエッチング法（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃ
ｈｉｎｇ）法により所定の位置にいわゆるトレンチ溝２
を深さ４μｍ程度形成する。この結果、トレンチ溝２の
底部と半導体基板１との距離は大体６μｍとなる。On the surface of the semiconductor substrate 1 which has been subjected to such treatment, an insulating layer 6 having a thickness of 500 to 1000 angstrom is coated, and then an anisotropic etching method such as a reactive ion etching method (Reactive Ion Etc) is used.
so-called trench groove 2 at a predetermined position by the Hing method.
To a depth of about 4 μm. As a result, the distance between the bottom of the trench groove 2 and the semiconductor substrate 1 is about 6 μm.
【００１２】更に、トレンチ溝２の底部の所定の位置以
外にインプラマスクを設置してから例えばＢを導入拡散
して第２Ｐ層１０を図２に明らかにしたように形成す
る。Further, an implantation mask is provided at a position other than a predetermined position on the bottom of the trench 2, and then, for example, B is introduced and diffused to form the second P layer 10 as shown in FIG.
【００１３】このように第２Ｐ層１０の形成を終えてか
ら厚さ５００〜１０００オングストロームの絶縁物層６
を半導体基板１表面に堆積する。材質としては、珪素酸
化物、窒化窒素、酸窒化珪素（オキシ窒化珪素:SiON ）
などが適用可能であり、その複数種を重ねることもでき
る。After the formation of the second P layer 10 as described above, the insulating layer 6 having a thickness of 500 to 1000 angstroms is formed.
Are deposited on the surface of the semiconductor substrate 1. Materials include silicon oxide, nitrogen nitride, silicon oxynitride (silicon oxynitride: SiON)
Etc. are applicable, and a plurality of types thereof can be stacked.
【００１４】この絶縁物層６には、公知のフォトリソグ
ラフィ工程を施して窓を設け、ここに導電性金属層とし
てＡｌまたはＡｌ合金例えばＡｌ−ＳｉやＡｌ−Ｓｉ−
Ｃｕを堆積するが、その後、公知のフォトリソグラフィ
工程により所定の形状として縦型ＭＯＳ−ＦＥＴのソー
ス電極７とゲート電極８を形成し、更に半導体基板１の
裏面にはドレイン電極９を形成する。実際には、縦型Ｍ
ＯＳ−ＦＥＴのソース電極７とゲート電極８を電気的に
短絡する。This insulating layer 6 is provided with a window by a known photolithography process, and a window is provided therein with Al or an Al alloy such as Al--Si or Al--Si-- as a conductive metal layer.
Cu is deposited, and thereafter, the source electrode 7 and the gate electrode 8 of the vertical MOS-FET are formed into a predetermined shape by a known photolithography process, and further, the drain electrode 9 is formed on the back surface of the semiconductor substrate 1. Actually, vertical M
The source electrode 7 and the gate electrode 8 of the OS-FET are electrically short-circuited.
【００１５】縦型ＭＯＳ−ＦＥＴとしては、この他の工
程があるが、本発明に関係がないので省略する。As the vertical MOS-FET, there are other steps, but they are omitted because they are not related to the present invention.
【００１６】[0016]
【発明の効果】図３及び図４は、本発明の効果を説明す
る図面で、前者が従来の技術、後者が本発明を示してお
り、特に空乏層１１の延び方を表している。即ち、トレ
ンチ溝底部のコーナ部図３のＢと、図４のＣ部付近と空
乏層１１間の距離が、際立って相違していることが明ら
かである。3 and 4 are views for explaining the effect of the present invention. The former shows the conventional technique and the latter shows the present invention, and particularly shows how the depletion layer 11 extends. That is, it is apparent that the distance between the corner portion at the bottom of the trench groove, B in FIG. 3 and the vicinity of C portion in FIG. 4 and the depletion layer 11 is significantly different.
【００１７】従来の技術では、Ｂと空乏層１１間の距離
は、他の空乏層１１とトレンチ溝２間の距離が違ってい
るのに対して、図４では、殆ど一定の距離を保ってい
る。このことは、Ｃ部分における電界の集中が緩和され
ることになり、図３の従来技術より耐圧が増加すること
になる。In the prior art, the distance between B and the depletion layer 11 is different from the distance between the other depletion layer 11 and the trench groove 2, whereas in FIG. 4, the distance is kept almost constant. There is. This means that the concentration of the electric field at the C portion is alleviated, and the breakdown voltage is higher than that of the conventional technique shown in FIG.
【００１８】従って、縦型ＭＯＳ−ＦＥＴに要求される
耐圧５２ｖを完全に満たすと共に、６０ｖも得られるの
で、量産上の効果は極めて大きいものがある。Therefore, the withstand voltage 52v required for the vertical MOS-FET can be completely satisfied and 60v can be obtained, so that the effect in mass production is extremely large.
【図１】従来の縦型ＭＯＳ−ＦＥＴの要部を示す断面図
である。FIG. 1 is a cross-sectional view showing a main part of a conventional vertical MOS-FET.
【図２】本発明に係わる縦型ＭＯＳ−ＦＥＴの要部を示
す断面図である。FIG. 2 is a sectional view showing a main part of a vertical MOS-FET according to the present invention.
【図３】従来の縦型ＭＯＳ−ＦＥＴに電圧印加時の空乏
層の伸びを明らかにする断面図である。FIG. 3 is a cross-sectional view showing the extension of a depletion layer when a voltage is applied to a conventional vertical MOS-FET.
【図４】本発明の縦型ＭＯＳ−ＦＥＴに電圧印加時の空
乏層の伸びを明らかにする断面図である。FIG. 4 is a cross-sectional view showing the extension of a depletion layer when a voltage is applied to the vertical MOS-FET of the present invention.
１：半導体基板、 ２：トレンチ溝、 ３：第１ｎ層、 ４：第１ｐ層、 ５：第２ｎ層、 ６：絶縁物層、 ７：ソース電極、 ８：ゲート電極、 ９：ドレイン電極、 １０：第２ｐ層。 1: semiconductor substrate, 2: trench groove, 3: first n layer, 4: first p layer, 5: second n layer, 6: insulator layer, 7: source electrode, 8: gate electrode, 9: drain electrode, 10 : Second p layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 馬場 嘉朗 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝多摩川工場内 (72)発明者 開 俊一 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝多摩川工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiro Baba No. 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Tamagawa Plant, Toshiba Corporation (72) Inventor Shun-ichi Komu-shishi-cho, Kawasaki-shi, Kanagawa No. 1 Stock Company Toshiba Tamagawa Factory
Claims (1)
導体基板に隣接してより高抵抗の領域を設置する工程
と，前記高抵抗の領域に達するトレンチ溝を形成する工
程と，前記高抵抗の領域に連続して設置する半導体層
と，前記トレンチ溝内部及び半導体層を被覆する絶縁物
層を形成する工程と，前記絶縁物層に電極を形成する工
程と，前記トレンチ溝底部との距離がほぼ一定の空乏層
を形成する手段を具備することを特徴とする半導体装置
の製造方法1. A semiconductor substrate having a first conductivity type, a step of providing a region of higher resistance adjacent to the semiconductor substrate, a step of forming a trench groove reaching the region of high resistance, A semiconductor layer continuously provided in the region of the resistance; a step of forming an insulating layer covering the inside of the trench groove and the semiconductor layer; a step of forming an electrode on the insulating layer; and a bottom portion of the trench groove. A method of manufacturing a semiconductor device, comprising means for forming a depletion layer having a substantially constant distance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3243910A JPH0582792A (en) | 1991-09-25 | 1991-09-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3243910A JPH0582792A (en) | 1991-09-25 | 1991-09-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0582792A true JPH0582792A (en) | 1993-04-02 |
Family
ID=17110828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3243910A Pending JPH0582792A (en) | 1991-09-25 | 1991-09-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0582792A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719409A (en) * | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
| JPH1098188A (en) * | 1996-08-01 | 1998-04-14 | Kansai Electric Power Co Inc:The | Insulated gate semiconductor device |
| WO1998026458A1 (en) * | 1996-12-11 | 1998-06-18 | The Kansai Electric Power Co., Inc. | Insulated gate semiconductor device |
| US5864159A (en) * | 1994-12-13 | 1999-01-26 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device structure to prevent a reduction in breakdown voltage |
| US5969378A (en) * | 1997-06-12 | 1999-10-19 | Cree Research, Inc. | Latch-up free power UMOS-bipolar transistor |
| US6121633A (en) * | 1997-06-12 | 2000-09-19 | Cree Research, Inc. | Latch-up free power MOS-bipolar transistor |
| US6534830B2 (en) * | 1999-05-12 | 2003-03-18 | Infineon Technologies Ag | Low impedance VDMOS semiconductor component |
| US6570185B1 (en) | 1997-02-07 | 2003-05-27 | Purdue Research Foundation | Structure to reduce the on-resistance of power transistors |
| JP2006319282A (en) * | 2005-05-16 | 2006-11-24 | Fuji Electric Device Technology Co Ltd | Manufacturing method of semiconductor device |
| US7470953B2 (en) | 2003-10-08 | 2008-12-30 | Toyota Jidosha Kabushiki Kaisha | Insulated gate type semiconductor device and manufacturing method thereof |
| JP2009260253A (en) * | 2008-03-26 | 2009-11-05 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
| CN102396070A (en) * | 2009-04-13 | 2012-03-28 | 罗姆股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN103107193A (en) * | 2011-11-11 | 2013-05-15 | 上海华虹Nec电子有限公司 | Grooved type insulated gate field effect transistor |
-
1991
- 1991-09-25 JP JP3243910A patent/JPH0582792A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5864159A (en) * | 1994-12-13 | 1999-01-26 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device structure to prevent a reduction in breakdown voltage |
| US5719409A (en) * | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
| US5831288A (en) * | 1996-06-06 | 1998-11-03 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
| JPH1098188A (en) * | 1996-08-01 | 1998-04-14 | Kansai Electric Power Co Inc:The | Insulated gate semiconductor device |
| WO1998026458A1 (en) * | 1996-12-11 | 1998-06-18 | The Kansai Electric Power Co., Inc. | Insulated gate semiconductor device |
| US6570185B1 (en) | 1997-02-07 | 2003-05-27 | Purdue Research Foundation | Structure to reduce the on-resistance of power transistors |
| US5969378A (en) * | 1997-06-12 | 1999-10-19 | Cree Research, Inc. | Latch-up free power UMOS-bipolar transistor |
| US6121633A (en) * | 1997-06-12 | 2000-09-19 | Cree Research, Inc. | Latch-up free power MOS-bipolar transistor |
| US6534830B2 (en) * | 1999-05-12 | 2003-03-18 | Infineon Technologies Ag | Low impedance VDMOS semiconductor component |
| US7470953B2 (en) | 2003-10-08 | 2008-12-30 | Toyota Jidosha Kabushiki Kaisha | Insulated gate type semiconductor device and manufacturing method thereof |
| JP2006319282A (en) * | 2005-05-16 | 2006-11-24 | Fuji Electric Device Technology Co Ltd | Manufacturing method of semiconductor device |
| JP2009260253A (en) * | 2008-03-26 | 2009-11-05 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
| US9166038B2 (en) | 2008-03-26 | 2015-10-20 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US9496387B2 (en) | 2008-03-26 | 2016-11-15 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US10290733B2 (en) | 2008-03-26 | 2019-05-14 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US10686067B2 (en) | 2008-03-26 | 2020-06-16 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US11127851B2 (en) | 2008-03-26 | 2021-09-21 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US12009420B2 (en) | 2008-03-26 | 2024-06-11 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US12034073B2 (en) | 2008-03-26 | 2024-07-09 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| CN102396070A (en) * | 2009-04-13 | 2012-03-28 | 罗姆股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN103107193A (en) * | 2011-11-11 | 2013-05-15 | 上海华虹Nec电子有限公司 | Grooved type insulated gate field effect transistor |
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