JPH0579648U - Watchdog detection control circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] CPU abnormality detection control is performed with a simple structure. [Configuration] The CPU 1 enters a normal operation state when the ignition switch 7 is turned on, enters a standby state in which a clock frequency is not generated when the ignition switch 7 is turned off, and outputs an abnormal output frequency from the watchdog output terminal WDP during a runaway.
A watchdog timer IC 11 that detects the abnormal output frequency and outputs a reset signal to the CPU 1 is provided. During standby, the transistor Q1 is turned on by the standby signal output from the standby output terminal -HALT, and the voltage of the capacitor C of the watchdog timer IC11 is held at a predetermined voltage to prevent reset output. During normal control, the transistor Q1 is turned off via the transistor Q2 which is turned on when the ignition switch 7 is turned on. A circuit that resets the CPU 1 when a standby output is output during normal control can be easily configured.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a watchdog detection control circuit, and more particularly to a watchdog detection control circuit suitable for detecting an abnormality of a CPU that is controlled so that a clock frequency is stopped and a dark current is passed when control is not performed.

[0002]

[Prior Art]

 2. Description of the Related Art Conventionally, there has been a control circuit that uses a CPU to perform various complicated controls, and is used for controlling an operating portion of a vehicle or the like. Generally, the CPU executes the calculation at a predetermined clock frequency, and generates the clock frequency when performing control by the CPU. In addition, a watchdog timer IC is connected to the CPU to monitor a watchdog signal of a predetermined frequency based on the clock frequency output from the CPU, and the output of this watchdog signal is stopped or an abnormal frequency is detected. When an output is output, this is detected by the watchdog timer IC and a reset signal is output to the CPU to prevent the CPU from running away.

As a circuit provided with the runaway detection circuit, there is a circuit shown in FIG. 2 which shows a motor drive control circuit for an automobile. In FIG. 2, a control unit 2 having a CPU 1 controls a motor group 3 having various motors in accordance with switch signals from a switch group 4 having various switches for appropriately operating them. To do. In the figure, in the control unit 2, there is provided a regulator 6 for converting the voltage from the battery 5 into a constant voltage and supplying it to the CPU 1. The signal of the ignition switch 7 connected to the voltage terminal of the battery 5 is input to the interrupt terminal INT of the CPU 1 via the diode D and the inverting circuit 8, and each switch signal from the switch group 4 is input via the input circuit 9. Is input to the CPU 1 and the motor control signal from the CPU 1 is output to the motor group 3 via the output circuit 10.

Further, in the control unit 2, a watchdog timer IC 11 as a watchdog circuit for monitoring a watchdog signal output when the CPU 1 is abnormal and outputting a reset signal to the CPU 1 when the abnormality is judged. It is provided. The watchdog output terminal WDP of the CPU1 is input to the check terminal CK of the watchdog timer IC11, and the reset output terminal -RESET of the watchdog timer IC11 is connected to the reset terminal -RESET of the CPU1. A capacitor C is connected to the time constant setting terminal CT of the watchdog timer IC11, and the other end of the capacitor C is grounded. A constant voltage from the regulator 6 is supplied to the power supply terminal Vcc of the watchdog timer IC 11. Normally, the watchdog timer IC charges and discharges the capacitor C corresponding to the watchdog output from the CPU1, monitors the voltage of this capacitor C, and when the watchdog output is stopped when the CPU1 is abnormal, the voltage of the capacitor C is changed. The voltage becomes equal to or lower than a predetermined voltage, and the CPU 1 is reset by detecting this and outputting a reset signal from the watchdog timer IC 11 to the CPU 1I.

By the way, since the power consumption due to the generation of the clock frequency during the operation of the CPU 1 is relatively large, the generation of the clock frequency is stopped when the engine is stopped to prevent the battery from running down in an automobile or the like. It is advisable to control so that the dark current necessary for the above is passed to the CPU 1. However, in the standby state when the engine is stopped, the clock frequency is stopped as described above, the watchdog output is stopped, and the watchdog timer IC11 outputs a reset signal to the CPU1. The inconvenience of being canceled occurs.

Therefore, generally, as shown in the figure, a standby output terminal -HALT is provided for detecting the off state of the ignition switch 7 and outputting a standby signal. The emitter of the transistor Q1 is connected to the reference voltage output terminal Vref of the watchdog timer IC11, the collector of the transistor Q1 is grounded via the resistor R1 and the capacitor C, and the resistor R1 and the capacitor C are connected. Node is connected to the time constant setting terminal CT of the watchdog timer IC11. In this way, the standby state setting circuit is configured.

During standby, the standby output terminal −HALT of the CPU 1 is set to a low level by turning off the ignition switch 7, the transistor Q1 is turned on, the capacitor C is charged through the resistor R1, and the voltage of the time constant setting terminal CT is increased. Is kept constant. Therefore, even if the watchdog output of the CPU 1 is stopped, the watchdog timer IC11 does not judge that the CPU is abnormal and outputs the reset signal, and thus the standby state can be maintained.

However, if an abnormality occurs in which the standby signal, that is, the standby output terminal −HALT becomes low level during the operation of the CPU 1, the reset signal from the watchdog timer IC 11 is not output and the CPU 1 may not be reset. There is

[0009]

[Problems to be solved by the device]

 In view of the above problems of the prior art, a main object of the present invention is to provide a watchdog detection control circuit capable of detecting an abnormality of a CPU and controlling the abnormality with a simple structure.

[0010]

[Means for Solving the Problems]

 According to the present invention, there are two states, such as a normal control state in which a clock frequency is generated by controlling a selection switch for control, and a standby state in which the clock frequency is stopped and a dark current is supplied. The CPU configured to operate in the CPU, the watchdog circuit that resets the CPU when a watchdog output is detected when the CPU is abnormal, and the standby signal output from the CPU in the standby state In a watchdog detection control circuit having a standby state setting circuit for stopping the watchdog detection of the watchdog circuit, the standby state setting circuit when the selection switch is switched to the normal control side. Control is prohibited, and the control prohibition state is released when the selection switch is switched to the standby state side. The signal is accomplished by providing a the watchdog detection control circuit, characterized in that a watchdog control switching circuit for outputting to the standby state setting circuit in accordance with the switching of the selection switch.

[0011]

[Action]

 By doing so, the watchdog circuit resets the CPU when the CPU is abnormal, and the watchdog detection control of the watchdog circuit is stopped when the CPU is in the standby state. Even if a corresponding watchdog output is issued, the CPU will not be reset. In the event of a runaway that outputs a standby signal during normal CPU control, the watchdog circuit is disabled because the control of the standby state setting circuit is prohibited if the selection switch is switched to normal control. Since it can operate, the above abnormality can be detected and the CPU can be reset.

[0012]

【Example】

 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing a motor drive control circuit for an automobile to which the present invention is applied. The same parts as those shown in the conventional example are designated by the same reference numerals and detailed description thereof will be omitted. To do.

In the present embodiment, the collector of the transistor Q2, whose emitter is connected to the voltage output terminal of the regulator 6, is connected to the base of the transistor Q1. The output terminal of the inverting circuit 8 for transmitting the ignition switch signal to the CPU 1 is connected to the base of the transistor Q2 via the resistor R3. A resistor R4 is connected between the base and emitter of the transistor Q2. The watchdog control switching circuit is configured in this way.

When the ignition switch 7 is turned off, the transistor Q2 is turned off, a high level signal is input to the interrupt terminal INT of the CPU1, the standby output terminal −HA LT becomes low level, and the transistor Q1 is turned on. The capacitor C is charged and the time constant setting terminal CT is kept at a predetermined voltage. Therefore, even if the CPU 1 enters the standby state and the watchdog output is stopped when the ignition switch 7 is turned off, the capacitor C connected to the watchdog timer IC 11 is held at the predetermined voltage, so the watchdog timer IC is It is not judged that the CPU1 is abnormal, the reset signal is not output to the CPU1, and the CPU1 maintains the standby state.

By the way, when the ignition switch 7 is on, the transistor Q2 is on, so that the transistor Q1 is off regardless of the output level of the standby output terminal −HALT. Therefore, the capacitor C connected to the watchdog timer IC11 charges and discharges corresponding to the watchdog output. Even if an abnormality occurs in the CPU1 and the standby output terminal -HALT goes low, the transistor Q1 does not turn on, and if the watchdog output stops, the watchdog timer IC11 outputs a reset signal. The CPU 1 is in the reset state.

[0017]

[Effect of the device]

 As described above, according to the present invention, in the watchdog detection control circuit having the standby state setting circuit, the watchdog timer IC reliably outputs the reset signal even if an abnormal standby signal is output during the operation of the CPU. You can reset the CPU.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of a motor drive control circuit for an automobile to which the present invention is applied.

FIG. 2 is a diagram showing a main part of a motor drive control circuit for an automobile showing a conventional example.

[Explanation of symbols]

 1 CPU 2 Control Unit 3 Motor Group 4 Switch Group 5 Battery 6 Regulator 7 Ignition Switch 8 Inversion Circuit 9 Input Circuit 10 Output Circuit 11 Watchdog Timer IC

Claims (1)

[Scope of utility model registration request] 1. A normal control state in which a clock frequency is generated and controlled by switching a selection switch, and a standby state in which the clock frequency is stopped and a dark current is supplied.
CPU adapted to operate in a state, and the CPU
When the watchdog output at the time of abnormality is detected, the CPU
Watchdog detection control circuit having a watchdog circuit for resetting the watchdog and a standby state setting circuit for bringing the watchdog detection of the watchdog circuit into a stopped state by a standby signal output from the CPU in the standby state In the above, when the selection switch is switched to the normal control side, the control of the standby state setting circuit is prohibited, and when the selection switch is switched to the standby state side, a signal for releasing the control prohibition state is provided. A watchdog detection control circuit provided with a watchdog control switching circuit for outputting to the standby state setting circuit according to switching of the selection switch.