JPH0578856B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a loop control type data processing device that does not have any branch instructions other than a branch instruction to address 0, for example.

[Background Art] For example, in a loop control type data processing device that does not have a branch instruction other than a branch instruction to address 0, initialization to uniquely set the state of this data processing device and data processing are required. The operations are executed within one loop control. In other words, once initialization is executed, only data processing is executed repeatedly.
It is configured so that execution of initialization can be prohibited.

However, with this configuration, even when initialization is not executed, all addresses where initialization instructions are stored are read by the program counter. Therefore, regardless of whether initialization and data processing are executed, the loop around the program becomes long and the data processing speed becomes slow.

Therefore, a loop control type data processing device that can effectively perform data processing is required.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned points. The present invention aims to provide a loop control type data processing device that can repeatedly execute only data processing without reading the address where the data is stored.

[Means for Solving the Problems] A loop control type data processing device according to the present invention is a loop control type data processing device that does not have a branch instruction other than a branch instruction to address 0, and is capable of initializing a reset register. In addition to setting the reset command state for make it happen. Further, the reset command state of the register reset is determined and the contents of the reset register set in this reset command state are set in the output permission register to set the initialization state, and initialization is performed based on this initialization setting. After execution, a restart instruction is set to invert the contents of the reset register, and thereafter, the output permission register is set to process the store instruction in accordance with the contents of the reset register set by the restart instruction. is allowed to execute and branches to address 0.

[Function] In the loop control type multi-processing device configured in this way, the reset register is set to the reset command state when the power is turned on, and the set output is inverted by inverting this content. The permission register executes or prohibits the store instruction. Then, when it is determined that the reset register is set to the reset command state, initialization processing is performed, and the contents of the reset register are then inverted, and from then on, a branch instruction to address 0 is set. .

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a loop control type data processing device, in which a program counter 11 specifies an address of an instruction stored in a ROM 12. The address specified ROM12 is
The command stored at the designated address is output to the command decoder 13. This instruction decoder 13
decodes the instructions output from ROM12,
A signal corresponding to the command is output to address bus 14, data bus 15 and control bus 16. The signals output to this control bus 16 are read signals and write signals. An output enable (OEN) register 17 is used to determine execution of a store instruction, and the output of this ONE register 17 is connected to one of the inputs of an AND circuit 18.
The other input of this AND circuit 18 is connected to the control bus 16.

Therefore, via the control bus 16
The write signal output from the OEN register 17 to the RAM 19 is determined by the AND of the contents set in the OEN register 17 and the write signal output from the instruction decoder 13. Therefore, from reset (RES) register 20 to data bus 1
When the signal set in the OEN register 17 via the input/output port 21 is logic "1", a write signal to the RAM 19 is generated, a store instruction is executed, and data is written from the input/output port 21 to the RAM 19. It becomes possible. Further, when the signal set in the register OEN17 is logic "0", this write signal is not generated and the store instruction is not executed.

The logic unit (LU) 22 performs logical operations based on control signals output from the instruction decoder, and the results of the operations are stored in a result register (RR) 23. The output of this RR register 23 is connected to the input of the logic unit 22 and to the instruction decoder 13. When a logic "0", that is, a restart command is output from the RR register 23 to the instruction decoder 13, the program counter 11 is set to address 0 by the instruction decoder 13.

FIG. 2 is a flowchart explaining the operation of the above embodiment. First, when the power is turned on,
"1" is set in the RES register 20, and in step 101, the inverted RES, that is, "0" is set.
Set in OEN register 17. Next, in step 102, if the content set in the OEN register is "1", the instruction decoder 13
A write signal is output to the RAM 19, and a store instruction is executed. When the store instruction is executed, data can be written from the input/output port 21 to the RAM 19, and normal data processing is executed.
Furthermore, if the content set in the OEN register 17 is "0", no write signal to the RAM 19 is output, and the store instruction is not executed. Therefore, data processing is no longer executed.

In step 103, the RES register 20 is read by the read signal output from the instruction decoder 13.
The content of is set in the RR register 23, and if the set content is "1", the process advances to the instruction at the next address, that is, step 104. Also,
If the content set in the RR register 23 is "0", the restart instruction is executed. That is, the address specified by the program counter 11 is set to address 0, and the operation of step 101 is executed. In step 104, the contents of the RES register 20 are set in the OEN register 17. In step 105, since the content set in this ONE register 17 is "1", initialization is executed. Then, in step 106, the RES register is set to "0" and the address specified by the program counter 11 becomes address 0, so the process starts again.
101 operations are performed.

That is, once initialization is executed in step 105, steps 101 to 103 are executed.
These operations, that is, data processing, are performed repeatedly.

[Effects of the Invention] As described above, according to the present invention, execution of a branch instruction to address 0 can be controlled based on the contents set in the RES register, and after initialization is executed, By setting a predetermined value in the RES register, we made it possible to branch to address 0, where the data processing program is stored. Therefore, if there is no need to perform initialization, do not call the address where the initialization instruction is stored,
Only data processing can be executed repeatedly.
Therefore, the data processing speed is higher than that of conventional data processing devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data processing apparatus according to an embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of the data processing apparatus. 11...Program counter, 12...
ROM, 13...Instruction decoder, 17...ONE register, 18...AND circuit, 19...RAM,
20...RES register, 22...logic unit,
23...Result register.

Claims (1)

[Claims] In a loop control type data processing device that has no branch instructions other than a branch instruction to address 1, a reset register setting that sets the reset register to a reset command state for initialization in an initial state. an output permission register set by inverting the contents of the reset register; write control means for permitting or prohibiting the execution of store instruction processing based on the contents of the output permission register; and resetting the reset register. Initialization setting means for determining a command state and setting it in the output permission register; and restart command setting means for inverting the contents of the reset register after initialization is executed based on the initialization setting means. Thereafter, the output permission register is inverted in accordance with the contents of the reset register set by the restart instruction, execution of the store instruction is permitted, and branching is made to address 0. A loop control type data processing device characterized by: