JPH0576178B2 - - Google Patents
Info
- Publication number
- JPH0576178B2 JPH0576178B2 JP59207300A JP20730084A JPH0576178B2 JP H0576178 B2 JPH0576178 B2 JP H0576178B2 JP 59207300 A JP59207300 A JP 59207300A JP 20730084 A JP20730084 A JP 20730084A JP H0576178 B2 JPH0576178 B2 JP H0576178B2
- Authority
- JP
- Japan
- Prior art keywords
- sic
- type
- silicon carbide
- heterojunction
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 74
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 17
- 238000000034 method Methods 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000815 Acheson method Methods 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は炭化硅素（SiC）のポリタイプの積
層によるヘテロ接合をゲートとする耐ゲート電圧
の大きい炭化硅素電界効果型トランジスタ素子に
関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a silicon carbide field effect transistor element having a high gate voltage withstand voltage and having a heterojunction formed by stacking silicon carbide (SiC) polytypes as a gate. .
従来、電界効果型トランジスタ（FET）素子
のゲートには、酸化物等の絶縁物を用いる方法
（例：Si−MOSFET）、金属／半導体接合による
シヨツトキー障壁を用いる方法（例：GaAs−
MESFET）がある。
Conventionally, the gates of field-effect transistors (FETs) have been made using an insulating material such as an oxide (e.g., Si-MOSFET), or using a Schottky barrier with a metal/semiconductor junction (e.g., GaAs-MOSFET).
MESFET).
炭化硅素（SiC）はSiやGaAsに比して大きな
禁制帯幅を持ち、耐熱、耐薬品性に優れ、耐環境
電子素子用材料として適している。SiCを用いた
FET素子を作る場合、MOS型とMES型とが考え
られる。しかし、SiCは非常に酸化しにくく、酸
化層の形成には飽和水蒸気中1000℃以上の加熱が
必要である。この方法でも酸化速度は毎分1nm程
度と極めて遅く、また再現性も悪い。また酸化層
の耐圧は約２×106V／cm程度であり、40nmの酸
化層に対して耐圧は約8Vである（参考文献：A.
Suzuki他、Appl.Phys.Lett.，39，89（1981））。 Silicon carbide (SiC) has a larger forbidden band width than Si or GaAs, and has excellent heat and chemical resistance, making it suitable as a material for environmentally resistant electronic devices. Using SiC
When making FET elements, MOS type and MES type can be considered. However, SiC is extremely difficult to oxidize and requires heating to over 1000°C in saturated steam to form an oxidized layer. Even with this method, the oxidation rate is extremely slow at about 1 nm per minute, and the reproducibility is also poor. The breakdown voltage of the oxide layer is approximately 2×10 6 V/cm, and the breakdown voltage for a 40 nm oxide layer is approximately 8V (Reference: A.
Suzuki et al., Appl. Phys. Lett., 39 , 89 (1981)).
シヨツトキー電極としてAu，Ag，Alなどが試
みられているが、金属蒸着前のSiC表面処理に難
点がある。即ち、Hagen（J.Appl.Phys.39，1458
（1968））の実験では、超高真空中劈解した6H型
SiC面に金属を蒸着した場合のみしか良好なシヨ
ツトキー障壁が得られなかつた。真空中結晶の劈
解、真空蒸着のプロセスは素子作製プロセスとし
ては使えない。第１図は3C型SiCにAuを蒸着し
た場合の電流−電圧特性を示す図で、耐圧は４〜
5Vである。 Au, Ag, Al, etc. have been tried as shot key electrodes, but there are difficulties in treating the SiC surface before metal deposition. That is, Hagen (J.Appl.Phys. 39 , 1458
(1968)), the 6H type was cleaved in an ultra-high vacuum.
A good Schottky barrier could only be obtained when metal was deposited on the SiC surface. The processes of cleaving crystals in vacuum and vacuum evaporation cannot be used as device fabrication processes. Figure 1 shows the current-voltage characteristics when Au is deposited on 3C type SiC.
It is 5V.
この発明はMOS構造あるいはMES構造の代り
に禁制帯幅の異なる炭化硅素のポリタイプのヘテ
ロ接合をゲートとすることにより、高い耐ゲート
電圧を持つ炭化硅素電界効果型トランジスタ素子
を提供するものである。
This invention provides a silicon carbide field effect transistor element with high gate voltage resistance by using a silicon carbide polytype heterojunction with different forbidden band widths as the gate instead of the MOS structure or MES structure. .
炭化硅素には数多くの結晶形（以下「ポリタイ
プ」という。）が存在する。そのポリタイプには
立方晶系のものと、六方晶系、菱面体晶系のもの
とがある。ここでは、これらのポリタイプの内、
唯一の立方晶系であるポリタイプ（以下「3C−
SiC」という。）をチヤンネルに、六方晶系の中
で繰り返し周期が６であるポリタイプ（以下
「6H−SiC」という。）をゲートとする場合を例に
して、本発明の原理について説明する。 Silicon carbide has many crystal forms (hereinafter referred to as "polytypes"). The polytypes include cubic, hexagonal, and rhombohedral polytypes. Here, among these polytypes,
Polytype (hereinafter referred to as "3C-
It is called "SiC". ) is used as a channel and a polytype (hereinafter referred to as "6H-SiC") having a repeating period of 6 in a hexagonal crystal system is used as an example to explain the principle of the present invention.
第２図はｎ型3C−SiC2（禁制帯幅Eg＝2.2eV）
とｎ型6H−SiC1（Eg＝2.8eV）が接合している時
のエネルギー帯図である。接合界面に界面準位が
形成され、接合近傍でエネルギー帯の曲りが生じ
る。この結果、接合に二重シヨツトキー障壁が形
成される。このヘテロ接合をゲートとして用い、
ｎ型6H−SiC1に負電圧を印加すれば、印加電圧
によつてｎ型3C−SiC2中の担体電子の数を制御
することができる。 Figure 2 shows n-type 3C-SiC2 (forbidden band width Eg = 2.2eV)
It is an energy band diagram when and n-type 6H-SiC1 (Eg = 2.8eV) are joined. Interface states are formed at the junction interface, and the energy band bends near the junction. This results in the formation of a double Schottky barrier at the junction. Using this heterojunction as a gate,
By applying a negative voltage to n-type 6H-SiC1, the number of carrier electrons in n-type 3C-SiC2 can be controlled by the applied voltage.
以下、実施例により高耐ゲート電圧の炭化硅素
FET素子の化学気相成長法による作製法につい
て説明する。
In the following, silicon carbide with high gate voltage resistance is shown in examples.
A method for manufacturing FET devices using chemical vapor deposition will be explained.
第３図ａ〜ｄは、この化学気相成長法による
3C−SiC／6H−SiCヘテロ接合結晶を用いたFET
の作製手順を示した図である。 Figures 3a to 3d are obtained by this chemical vapor deposition method.
FET using 3C-SiC/6H-SiC heterojunction crystal
FIG.
アチソン法で作製された6H−SiC（0001）面を
カーボランダム、ダイヤモンドペーストで研摩し
て鏡面にしたものを基板として用いる。弗化水素
により表面酸化層を除去した後、反応管中のグラ
フアイトサセプター上に置く。シラン、プロパン
反応ガス及び水素キヤリアガスを流し、基板温度
1750℃で6H−SiCをホモエピタキシヤル成長させ
る。次に基板温度を1400〜1500℃に下げて3C−
SiCを6H−SiC上にヘテロエピタキシヤル成長さ
せる〔第３図ａ〕。6H−SiC上の3C−SiCは
（0001）6H（111）3Cとなるような結晶方位で
エピタキシヤル成長する。この面方位での格子不
整は0.34％と極めて小さいため、良質のヘテロエ
ピタキシヤル成長が得られる。なお、両SiCは共
にノンドープでｎ型であり、電子濃度は1017cm-3
オーダである。 A 6H-SiC (0001) surface prepared by the Acheson method is polished to a mirror surface with carborundum and diamond paste and used as a substrate. After removing the surface oxidation layer with hydrogen fluoride, it is placed on a graphite susceptor in a reaction tube. Flow silane, propane reaction gas, and hydrogen carrier gas to increase the substrate temperature.
Homoepitaxial growth of 6H-SiC at 1750℃. Next, lower the board temperature to 1400~1500℃ to 3C−
SiC is grown heteroepitaxially on 6H-SiC [Figure 3a]. 3C-SiC on 6H-SiC grows epitaxially with a crystal orientation of (0001)6H(111)3C. Since the lattice misalignment in this plane orientation is extremely small at 0.34%, high-quality heteroepitaxial growth can be obtained. Both SiCs are non-doped and n-type, and the electron concentration is 10 17 cm -3
It is an order.
SiCヘテロエピタキシヤル成長結晶の6H−SiC
基板６を除去し〔第３図ｂ〕、6H−SiC成長層５
の一部をエツチング〔第３図ｃ〕したのち、ソー
ス８、ゲート９、ドレイン１０に相当する電極と
して、ニツケルを真空蒸着し、アルゴン中1050℃
で５分間焼鈍しオーミツク接触を得る〔第３図
ｄ〕。 6H−SiC of SiC heteroepitaxial growth crystal
The substrate 6 is removed [Fig. 3b], and the 6H-SiC growth layer 5 is removed.
After etching a part (Fig. 3c), nickel was vacuum-deposited as electrodes corresponding to the source 8, gate 9, and drain 10, and heated at 1050°C in argon.
Anneal for 5 minutes to obtain ohmic contact (Fig. 3d).
第４図はｎ型3C−SiC／ｎ型6H−SiCヘテロ接
合の電流−電圧特性を示す図である。また、第５
図は3C−SiCに正、6H−SiCに負電圧を印加した
時の容量Ｃの印加電圧Va依存から求めた１／C2
とVaとの関係を示した図である。印加電圧20V
までほぼ直線となつており、耐圧が20V以上であ
ることを示している。 FIG. 4 is a diagram showing current-voltage characteristics of an n-type 3C-SiC/n-type 6H-SiC heterojunction. Also, the fifth
The figure shows 1/C 2 obtained from the dependence of the capacitance C on the applied voltage Va when a positive voltage is applied to 3C-SiC and a negative voltage is applied to 6H-SiC.
FIG. 3 is a diagram showing the relationship between and Va. Applied voltage 20V
It is almost a straight line up to , indicating that the withstand voltage is 20V or higher.
化学気相成長法においてｎ型ドーパントとして
アンモニアあるいは窒素、ｐ型ドーパントとして
ジボラン、トリメチルアルミニウムなどを用いて
ｎ型及びｐ型のSiCを作製することができる。第
６〜９図はｎ及びｐ型SiCを用いた種々のFETの
構造を示した図である。第６，７図はｎ−ｎ及び
ｐ−ｐ接合を用いたそれぞれ(a)はデイプレツシヨ
ン型及び同じく(b)はエンハンスメント型FETの
構造である。また、第８，９図はｎ型3C−SiC／
ｐ型6H−SiC及びｐ型3C−SiC／ｎ型6H−SiCヘ
テロ接合を用いたそれぞれ(a)はデイブレツシヨン
型、同じく(b)はエンハンスメント型FETの構造
である。以上では、3C−SiCをチヤンネルに、
6H−SiCをゲートとする場合について本発明を説
明してきたが、これはあくまでも本発明の一実施
例であり、本発明は、禁制帯幅の異なるいかなる
ポリタイプの組み合わせにも適用して有効なもの
である。 In a chemical vapor deposition method, n-type and p-type SiC can be produced using ammonia or nitrogen as an n-type dopant, and diborane, trimethylaluminum, or the like as a p-type dopant. 6 to 9 are diagrams showing the structures of various FETs using n- and p-type SiC. 6 and 7 show the structures of (a) a depletion type FET and (b) an enhancement type FET using nn and pp junctions, respectively. Also, Figures 8 and 9 show n-type 3C-SiC/
(a) uses a p-type 6H-SiC and a p-type 3C-SiC/n-type 6H-SiC heterojunction, and (a) is a deblection type FET, and (b) is an enhancement type FET. In the above, 3C−SiC is used as a channel,
Although the present invention has been described with respect to the case where 6H-SiC is used as the gate, this is just one embodiment of the present invention, and the present invention can be applied effectively to any combination of polytypes with different forbidden band widths. It is something.
以上説明したように、この発明は炭化硅素のポ
リタイプのヘテロ接合をゲートとして用いた電界
効果型トランジスタ素子である。これは従来炭化
硅素を用いたトランジスタ素子で、MOS型でも
MES型でも問題のあつた耐ゲート電圧を高める
ことを可能にし、耐熱、耐薬品性に優れた耐環境
電子素子が提供できる。
As explained above, the present invention is a field effect transistor element using a silicon carbide polytype heterojunction as a gate. This is a transistor element that conventionally uses silicon carbide, and even MOS type
This makes it possible to increase the gate voltage resistance, which was a problem even with the MES type, and provides environmentally resistant electronic devices with excellent heat and chemical resistance.
第１図はAu／3C−SiCシヨツトキー障壁の電
流−電圧特性を説明するための図、第２図はｎ型
3C／SiC／ｎ型6H−SiCヘテロ接合のエネルギー
帯図、第３図は化学気相成長法による3C−SiC／
6H−SiCヘテロ接合結晶を用いたFETの作製手
順を示したもので、第３図ａは3C−SiC／6H−
SiCヘテロ接合結晶の概略構成図、同図ｂは基板
を除去した概略構成図、ｃは6H−SiC成長層の一
部をエツチングした概略構成図、ｄはソース、ゲ
ート、ドレイン電極を着けたFET構造の概略構
成図、第４図は化学気相成長法で作製したｎ型
3C−SiC／ｎ型−SiCヘテロ接合の電流電圧特性
を説明するための図、第５図は同ヘテロ接合の
3C−SiCに正、6H−SiCに負電圧を印加した時の
容量Ｃの印加電圧Va依存から求めた１／C2とVa
との関係を説明するための図、第６図、第７図は
ｎ−ｎ及びｐ−ｐ接合を用いたもので第６図ａ，
第７図ａはデイプレツシヨン型構造の概略構成
図、同じくｂはエンハンスメント型FET構造の
概略構成図、第８図、第９図はｎ型3C−SiC／ｐ
型6H−SiC及びｐ型3C−SiC／ｎ型6H−SiCヘテ
ロ接合を用いたもので第８図ａ，第９図ａはデイ
プレツシヨン型構造の概略構成図、同じくｂはエ
ンハンスメント型FET構造の概略構成図である。
図中１はｎ型6H−SiC、２はｎ型3C−SiC、３
は界面準位、４は3C−SiC成長層、５は6H−SiC
成長層、６は6H−SiC基板、７は絶縁体、８はソ
ース電極（Ni）、９はゲート電極（Ni）、１０は
ドレイン電極（Ni）、１１はｎ型6H−SiC、１２
は3C−SiC ｎチヤンネル、１３はn+3C−SiC、
１４はｐ型あるいは半絶縁3C−SiC、１５はｎ型
3C−SiCでVa＝０でのデイプレツシヨン層、１
６はソース電極（Al−Si）、１７はゲート電極
（Al−Si）、１８はドレイン電極（Al−Si）、１９
はｐ型6H−SiC、２０は3C−SiC ｐチヤンネル、
２１はp+3C−SiC、２２はｎ型あるいは半絶縁
3C−SiC、２３はｐ型3C−SiCでVa＝０でのデイ
プレツシヨン層である。
Figure 1 is a diagram to explain the current-voltage characteristics of the Au/3C-SiC Schottky barrier, and Figure 2 is an n-type diagram.
Energy band diagram of 3C/SiC/n-type 6H-SiC heterojunction, Figure 3 shows 3C-SiC/n-type 6H-SiC heterojunction by chemical vapor deposition.
The fabrication procedure of FET using 6H-SiC heterojunction crystal is shown in Figure 3a.
Schematic diagram of the SiC heterojunction crystal; Fig. b is a schematic diagram with the substrate removed; c is a schematic diagram with a part of the 6H-SiC growth layer etched; d is a FET with source, gate, and drain electrodes. Schematic diagram of the structure, Figure 4 is an n-type fabricated by chemical vapor deposition method.
Figure 5 is a diagram to explain the current-voltage characteristics of a 3C-SiC/n-type-SiC heterojunction.
1/C 2 and Va obtained from the dependence of the capacitance C on the applied voltage Va when a positive voltage is applied to 3C-SiC and a negative voltage is applied to 6H-SiC.
Figures 6 and 7 are diagrams for explaining the relationship between
Figure 7a is a schematic diagram of the depletion type structure, b is a schematic diagram of the enhancement type FET structure, and Figures 8 and 9 are n-type 3C-SiC/p
It uses type 6H-SiC and p-type 3C-SiC/n-type 6H-SiC heterojunction. Figures 8a and 9a are schematic diagrams of the depletion type structure, and figure b is a schematic diagram of the enhancement type FET structure. FIG. In the figure, 1 is n-type 6H-SiC, 2 is n-type 3C-SiC, and 3
is the interface level, 4 is the 3C-SiC growth layer, 5 is the 6H-SiC
Growth layer, 6 is 6H-SiC substrate, 7 is insulator, 8 is source electrode (Ni), 9 is gate electrode (Ni), 10 is drain electrode (Ni), 11 is n-type 6H-SiC, 12
is 3C−SiC n channel, 13 is n + 3C−SiC,
14 is p-type or semi-insulating 3C-SiC, 15 is n-type
Depression layer at Va=0 in 3C-SiC, 1
6 is a source electrode (Al-Si), 17 is a gate electrode (Al-Si), 18 is a drain electrode (Al-Si), 19
is p-type 6H-SiC, 20 is 3C-SiC p channel,
21 is p + 3C-SiC, 22 is n-type or semi-insulating
3C-SiC, 23 is p-type 3C-SiC and is a depletion layer at Va=0.
Claims (1)
１の結晶形と異なる第２の結晶形を有する第２の
炭化硅素とのヘテロ接合からなるゲートと、前記
第１および第２の炭化硅素の一方の炭化硅素上に
設けられたゲート電極と、他方の炭化硅素上に設
けられたソース電極およびドレイン電極とを有す
ることを特徴とする炭化硅素電界効果トランジス
タ。1 a gate consisting of a heterojunction of a first silicon carbide having a first crystal form and a second silicon carbide having a second crystal form different from the first crystal form; A silicon carbide field effect transistor characterized by having a gate electrode provided on one silicon carbide, and a source electrode and a drain electrode provided on the other silicon carbide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207300A JPS6184873A (en) | 1984-10-03 | 1984-10-03 | Semiconductor device using silicon carbide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207300A JPS6184873A (en) | 1984-10-03 | 1984-10-03 | Semiconductor device using silicon carbide |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6184873A JPS6184873A (en) | 1986-04-30 |
| JPH0576178B2 true JPH0576178B2 (en) | 1993-10-22 |
Family
ID=16537495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59207300A Granted JPS6184873A (en) | 1984-10-03 | 1984-10-03 | Semiconductor device using silicon carbide |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6184873A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01185978A (en) * | 1988-01-20 | 1989-07-25 | Sharp Corp | Silicon carbide semiconductor element |
| JP3440861B2 (en) * | 1999-01-19 | 2003-08-25 | 松下電器産業株式会社 | Method for manufacturing field effect transistor |
-
1984
- 1984-10-03 JP JP59207300A patent/JPS6184873A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6184873A (en) | 1986-04-30 |
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