JPH0575439A - Ttl circuit - Google Patents

Abstract

PURPOSE:To eliminate an output delay of the TTL circuit caused in a current path formed to a Schottky diode located between a collector and a base of a pull-down TR and between a base and an emitter of a base drive transistor(TR) for the pull-down TR. CONSTITUTION:A 0 clamp circuit comprising a TR 10 and Schottky diodes 16, 17 is connected between a circuit output 25 and a collector of an emitter follower TR 7 of a first stage of the circuit input. With a negative noise applied to the output 25 when the output 25 is at a low level, the 0 clamp circuit is set to clamp the output 25 to 0V (almost low level). Then a current path formed between a Schottky diode of a pull-down TR 21 and a base-emitter of a drive TR 11 is eliminated and a change from an output low level to a high level is quickened.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a TTL circuit, and more particularly to a TTL circuit having an output transistor that pulls up and pulls down an output potential.

[0002]

2. Description of the Related Art A conventional TTL circuit of this type has a three-stage amplifier circuit configuration as shown in FIG. 2, and in this example, a one-input inverter circuit is shown, but a NAND circuit having a plurality of inputs may be used.

The input 1 is the base input of the emitter follower transistor 7 via the diode 3, and the emitter follower output is the base input of the drive transistor 11. A pair of complementary signals are obtained at the collector and the emitter of the transistor 11, and the collector output signal of the pair of complementary signals becomes the base input of the transistor 18, and the emitter output signal becomes the base input of the transistor 21.

The transistors 18 and 19 are Darlington-connected, and the potential of the output 25 is pulled up (the positive power supply 24) by the transistors 18 and 19. Also, the transistor 21 pulls down (potentially grounds) the potential of the output 25.

The diodes 2, 4, 14, 15, 23
Is a Schottky diode, and in particular, the diodes 2 and 23 are electrostatic breakdown preventing diodes at the input / output terminals of the circuit. Also, 5, 6, 8, 12, 13, 20,
Reference numeral 22 represents a resistance element.

In such a configuration, the output stage pull-up transistor 19 is on and the pull-down transistor 21 is off when the transistor 11 in the second stage from the input stage (the same applies to the transistor 7 in the first stage) is turned on and off. And the output low level state in which the pull-up transistor 19 is off and the pull-down transistor 21 is on.

When negative noise is superimposed on the output 25, a leak current flows due to the following reason and the second-stage transistor 11 is not turned off. Therefore, the pull-up transistor 19 in the output stage is not turned on. The output 25 has a long delay time from low to high level.

In general, the pull-down transistor 21 uses a Schottky transistor in order to improve switching characteristics, and a Schottky diode is formed between the base and the collector in the direction from the base to the collector. Therefore, when negative noise is superimposed on the output 25, a current path to the output 25 is formed via the base and emitter of the transistor 11 and the shot diode between the base and collector of the pull-down transistor 21.

At this time, the input changes and the transistor 1
Even if 1 is turned off, while the output 25 has negative noise due to reflection noise, crosstalk noise, etc., current flows through the above current path, the transistor 11 is not turned off, and thus the output 25 is in a high state. I won't. Therefore,
While the negative noise is present at the output, the output state does not change from low level to high level, so the delay time increases.

At present, TTL circuits are used at high speed, and negative noise due to reflected waves, ground noise, crosstalk noise, etc. is increasing, which causes the above-mentioned increase in delay time. Therefore, the reliability of the device is deteriorated, and the device design is also difficult.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a TTL circuit which can operate at high speed without an output delay time.

[0012]

The TTL circuit according to the present invention comprises a pull-up transistor for pulling up the output potential, a pull-down transistor with a Schottky diode for pulling down the output potential, and a pair of the pull-up and pull-down transistors. Driving means for complementary driving with the complementary driving signal, and clamping means for operating when the output potential drops below the logical low level potential to clamp the output potential to the logical low level potential. Is characterized by.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The same parts as those in FIG.
An input inverter circuit is shown, but is not limited to this.

There is provided a Schottky transistor 10 whose base is connected to the collector of the first emitter follower transistor (Schottky transistor) 7 in the input stage and whose collector is pulled up to the positive power source 24 via the resistor 9.

Two stages of Schottky diodes 16 and 17 are connected in series between the emitter of the transistor 10 and the circuit output 25. The polarity of the connection is such that the output 25 side is the cathode and the emitter side of the transistor 10 is the anode. The polarity is as follows.

This transistor 10 and diode 16,
A zero clamp circuit is constituted by 17 and the other constitution is the same as that of FIG. 2, and therefore its explanation is omitted.

When the logic level of the output 25 is high, the transistors 7 and 11 are both off, so that between the base voltage of the transistor 10 and the voltage of the output 25, the transistor 10 and the Schottky diodes 16 and 17 are provided. The 0 clamp circuit does not function at all because it does not generate a sufficient potential difference to turn on.

When the logic level of the output 25 is low, both the transistors 7 and 11 are turned on. At this time, the base potential of the transistor 10 is equal to that of the transistor 1
Two stages of base-emitter voltage of 1, 21 (0.8 x 2
= 1.6v) and the collector-emitter voltage of the transistor 7 (approximately 0.2v), which is 1.8v.

At this time, the potential of the output 25 is about 0.2v at the low level, so that the difference between the base potential of the transistor 10 and the output potential is about 1.6v. In order for the 0 clamp circuit to turn on, the base-emitter voltage of the transistor 10 (0.8 v) and the forward voltage of the Schottky diodes 16 and 17 for two stages (0.5 × 2 = 1.
A potential difference of 1.8v or more, which is the sum of 0v), is required between the base of the transistor 10 and the output 25.

Therefore, even when the output 25 is at the low level, the 0 clamp circuit does not turn on and does not function at all.

Consider a case where negative noise is added to the output 25 due to crosstalk noise or the like in the low output state. The base potential of the transistor 10 of the 0 clamp circuit is about 1.8 V at the time of low output as described above, and the output 2
When the potential of 5 becomes a negative potential lower than the low level due to negative noise, it becomes equal to or higher than the threshold value of the 0 clamp circuit (potential difference between the base of the transistor 10 and the output 25 = 1.8v), and the 0 clamp circuit starts. It will be turned on.

Therefore, the potential of the output 25 is clamped to about 0 v (which can be regarded as substantially equal to the low level of the logic signal) by the ON operation of the 0 clamp circuit. As a result, the output 25 does not have a negative potential, and thus an increase in delay time due to negative noise is prevented.

[0024]

As described above, according to the present invention, when the output potential becomes lower than the logic low level due to noise or the like, it is detected to operate and the output is clamped to the substantially low level. Therefore, there is an effect that the output does not become a negative level due to noise or the like, and thus the delay time from the low to the high of the output is eliminated and the high speed operation becomes possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a conventional TTL circuit.

[Explanation of symbols]

 1 Input 7 Emitter Follower Transistor 100 Clamp Circuit 11 Drive Transistor 16,17 Schottky Diode 18,19 Pull-up Transistor 21 Pull-down Transistor 25 Output

Claims (2)

[Claims] 1. A pull-up transistor that pulls up an output potential, a pull-down transistor with a Schottky diode that pulls down the output potential, and the pull-up and pull-down transistors are complemented by a pair of complementary drive signals. Driving means for driving the output potential and clamping means for operating when the output potential drops below a logical low level potential to clamp the output potential at the logical low level potential.
circuit. 2. The driving means includes an emitter follower transistor having a circuit logic input signal as a base input, and a driving transistor having an emitter follower output of the emitter follower transistor as a base input and generating the pair of complementary driving signals. The clamp means includes two clamp transistors, the base of which is connected to the collector of the emitter follower transistor and the collector of which is pulled up, and two clamp transistors which are connected in series between the emitter of the clamp transistor and the output potential point. 3. The TTL circuit according to claim 1, further comprising: