JPH0574784A - Manufacture of silicon substrate - Google Patents
Manufacture of silicon substrateInfo
- Publication number
- JPH0574784A JPH0574784A JP26536691A JP26536691A JPH0574784A JP H0574784 A JPH0574784 A JP H0574784A JP 26536691 A JP26536691 A JP 26536691A JP 26536691 A JP26536691 A JP 26536691A JP H0574784 A JPH0574784 A JP H0574784A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- oxygen
- single crystal
- substrate
- oxygen concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、シリコン基板の製造方
法に関し、詳しくはデバイス工程中に誘起される欠陥、
不純物等を、デバイスが構成される活性領域から除去す
ることができるようにしたシリコン基板の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a silicon substrate, and more particularly, to defects caused during a device process,
The present invention relates to a silicon substrate manufacturing method capable of removing impurities and the like from an active region in which a device is formed.
【０００２】[0002]
【従来の技術】近年、メガビットメモリの量産化に基づ
いてＤＲＡＭ等の半導体素子の高集積化が要求され、シ
リコン基板についてもより一層の高品質化が要望されて
いる。2. Description of the Related Art In recent years, high integration of semiconductor elements such as DRAMs has been demanded based on mass production of megabit memories, and further higher quality of silicon substrates has been demanded.
【０００３】従来、ＣＺ単結晶から切り出された単結晶
シリコン基板では、特定の加熱処理が施されている。こ
の加熱処理により、基板表面に無欠陥層（ＤＺ）を、基
板内部に内部領域微小欠陥（Bulk Micro Defect:BMD）
を、それぞれ形成している。この内部領域微小欠陥によ
り、半導体集積回路の製造過程中に侵入する微量の重金
属、例えば鉄、ニッケル、銅等を析出させている。イン
トリンシック・ゲッタリング（ＩＧ）効果を積極的に利
用しているものである。そして、その結果として、半導
体装置の歩留まりの向上、例えばｐｎ接合のリーク電流
の減少、キャリアのライフタイムの向上等を図ってい
る。Conventionally, a single crystal silicon substrate cut out from a CZ single crystal has been subjected to a specific heat treatment. By this heat treatment, a defect-free layer (DZ) is formed on the substrate surface, and internal area micro defects (BMD) are formed inside the substrate.
Are formed respectively. Due to the small defects in the internal region, a trace amount of heavy metals, such as iron, nickel, and copper, which enter during the manufacturing process of the semiconductor integrated circuit, are deposited. It actively utilizes the intrinsic gettering (IG) effect. As a result, the yield of the semiconductor device is improved, for example, the leak current of the pn junction is reduced, the carrier lifetime is improved, and the like.
【０００４】この場合、ＩＧ効果には、単結晶シリコン
基板中に含有されている酸素（［Ｏi］：格子間に存在
する酸素）濃度が関連する。すなわち、結晶成長時、坩
堝や雰囲気から混入し、単結晶シリコン中に溶解してい
る過剰の酸素（高酸素）は、高温処理、例えば１１００
〜１１５０℃程度の熱処理を行い、基板中の酸素を外方
拡散させている。このことにより、酸素濃度が低下した
領域内の一部を最終的にＤＺに形成するものである。次
に、低温処理、例えば９００℃以下の熱処理を行い、基
板内部に酸素が析出し、その析出箇所の周囲に結晶欠陥
を形成する。この形成により、結晶格子に歪が生じ、ゲ
ッタリング源として作用し、重金属等が析出するもので
ある。In this case, the IG effect is related to the concentration of oxygen ([Oi]: oxygen existing between the lattices) contained in the single crystal silicon substrate. That is, excess oxygen (high oxygen) mixed in the crucible or the atmosphere during crystal growth and dissolved in the single crystal silicon is subjected to high temperature treatment, for example, 1100.
The heat treatment is performed at about 1150 ° C. to diffuse oxygen in the substrate outward. As a result, a part of the region where the oxygen concentration is lowered is finally formed in the DZ. Next, low-temperature treatment, for example, heat treatment at 900 ° C. or lower is performed to precipitate oxygen inside the substrate and form a crystal defect around the precipitation portion. This formation causes strain in the crystal lattice, acts as a gettering source, and deposits heavy metals and the like.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のＩＧ処理では、シリコン結晶中に固溶する酸
素の濃度が低いシリコン基板では、酸素析出物が発生し
難いものであった。また、ＤＺ（デバイス形成領域）を
形成するための上記高温処理により、酸素析出物の核も
縮小してしまう。このため、低酸素濃度のシリコン基板
については十分な量のゲッタリング源の確保が難しかっ
た。すなわち、従来のＩＧ処理は、主に高酸素濃度のシ
リコン基板にのみ用いられ、低酸素濃度のシリコン基板
には用いられていなかった。換言すると、低酸素濃度の
シリコン基板については十分なＩＧ効果を備えることは
できなかった。However, in such a conventional IG process, it was difficult to generate oxygen precipitates on a silicon substrate having a low concentration of oxygen dissolved in a silicon crystal. Further, the nuclei of oxygen precipitates are also reduced by the high temperature treatment for forming DZ (device forming region). Therefore, it is difficult to secure a sufficient amount of gettering source for a silicon substrate having a low oxygen concentration. That is, the conventional IG process is mainly used only for a silicon substrate having a high oxygen concentration, and has not been used for a silicon substrate having a low oxygen concentration. In other words, it was not possible to provide a sufficient IG effect for a low oxygen concentration silicon substrate.
【０００６】[0006]
【発明の目的】本発明の目的は、低酸素濃度のシリコン
基板においても十分なＩＧ効果を得ることのできるシリ
コン基板の製造方法を提供することである。An object of the present invention is to provide a method for manufacturing a silicon substrate which can obtain a sufficient IG effect even in a silicon substrate having a low oxygen concentration.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
になされた本発明のシリコン基板の製造方法において
は、７.５×１０17ａｔｏｍｓ／ｃｍ3以下の格子間酸素
を含有している単結晶シリコン基板を準備する工程と、
この単結晶シリコン基板の裏面に多結晶シリコン膜を形
成する工程と、このシリコン基板を１２００℃以上で３
０分間以上熱処理する工程と、このシリコン基板を１０
００℃以下で２時間以上熱処理する工程と、を有してい
る。In the method for producing a silicon substrate of the present invention, which has been made to achieve the above object, a simple substance containing interstitial oxygen of 7.5 × 10 17 atoms / cm 3 or less is contained. A step of preparing a crystalline silicon substrate,
The step of forming a polycrystalline silicon film on the back surface of this single crystal silicon substrate, and
The process of heat-treating for 0 minutes or more and this silicon substrate 10
And a step of performing heat treatment at 00 ° C. or lower for 2 hours or more.
【０００８】[0008]
【作用】上記のように構成されたシリコン基板の製造方
法では、７.５×１０17ａｔｏｍｓ／ｃｍ3以下の格子間
酸素を含有している低酸素濃度の単結晶シリコン基板の
裏面に、例えばＣＶＤ法（化学気相成長法）により、多
結晶シリコン膜を形成する。そして、このシリコン基板
に上記２段階の熱処理を施す。この１２００℃以上の熱
処理と１０００℃以下の熱処理とにより、低酸素濃度の
シリコン基板にあってもそのシリコン基板の内部に形成
される酸素析出物の核の成長が助長される。すなわち、
十分な量のゲッタリング源をシリコン基板の内部に確保
することができるものである。In the method of manufacturing a silicon substrate having the above-described structure, a low oxygen concentration single crystal silicon substrate containing interstitial oxygen of 7.5 × 10 17 atoms / cm 3 or less is used, for example, on the back surface. A polycrystalline silicon film is formed by the CVD method (chemical vapor deposition method). Then, the silicon substrate is subjected to the above-described two-step heat treatment. The heat treatment at 1200 ° C. or higher and the heat treatment at 1000 ° C. or lower promote the growth of nuclei of oxygen precipitates formed inside the silicon substrate having a low oxygen concentration. That is,
It is possible to secure a sufficient amount of gettering source inside the silicon substrate.
【０００９】[0009]
【実施例】以下、本発明に係るシリコン基板の製造方法
の実施例について、図面を参照して説明する。図１は本
発明の一実施例に係るシリコン基板の製造方法の工程を
示す断面図である。Embodiments of the method for manufacturing a silicon substrate according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing the steps of a method for manufacturing a silicon substrate according to an embodiment of the present invention.
【００１０】図１（ａ）、（ｂ）に示すように、まず、
７.５×１０17ａｔｏｍｓ／ｃｍ3（ＪＥＩＤＡ）の格子
間酸素を含んだ単結晶シリコン基板１を準備し、この単
結晶シリコン基板１の裏面（図中の上面）に、例えばＳ
ｉＨ4ガスを用い６２０℃の温度にて通常のＣＶＤ法に
よって、多結晶シリコン膜２を１.５μｍの厚さに被着
し、シリコン基板３を得る。As shown in FIGS. 1 (a) and 1 (b), first,
A single crystal silicon substrate 1 containing 7.5 × 10 17 atoms / cm 3 (JEIDA) interstitial oxygen is prepared, and the rear surface (upper surface in the figure) of the single crystal silicon substrate 1 is provided with, for example, S.
A polycrystalline silicon film 2 is deposited to a thickness of 1.5 μm by a normal CVD method using iH 4 gas at a temperature of 620 ° C. to obtain a silicon substrate 3.
【００１１】このようにして準備したシリコン基板３
に、例えば１２００℃、１時間の高温熱処理を施す（図
１（ｃ））。次に、このシリコン基板３に例えば５５０
℃、４８時間の低温熱処理を加える（図１（ｄ））。こ
の結果、単結晶シリコン基板１内部に、酸素析出物の核
４（図１（ｄ）中×印）が成長する。そして、多結晶シ
リコン膜２と単結晶シリコン基板１との界面近傍におい
ては、酸素析出物の発生量が多くなる。次に、析出物を
顕在化させるために、１０００℃、２４時間の熱処理を
施す。そして、表１は、光顕微鏡の観察により求めた酸
素析出物の密度を示している。酸素濃度の同じ単結晶シ
リコン基板に、多結晶シリコン膜２を被着した場合と、
被着しない場合とを比較して示している。The silicon substrate 3 thus prepared
Is subjected to high temperature heat treatment at 1200 ° C. for 1 hour, for example (FIG. 1C). Next, for example, 550 is added to the silicon substrate 3.
A low temperature heat treatment is performed at 48 ° C. for 48 hours (FIG. 1D). As a result, nuclei 4 of oxygen precipitates (marked with X in FIG. 1D) grow inside the single crystal silicon substrate 1. Then, in the vicinity of the interface between the polycrystalline silicon film 2 and the single crystal silicon substrate 1, the amount of oxygen precipitates generated increases. Next, heat treatment is performed at 1000 ° C. for 24 hours in order to reveal the precipitate. Then, Table 1 shows the density of oxygen precipitates obtained by observation with an optical microscope. When the polycrystalline silicon film 2 is deposited on the single crystal silicon substrate having the same oxygen concentration,
The figure shows a comparison with the case where no coating is applied.
【００１２】[0012]
【表１】 [Table 1]
【００１３】この表より、低酸素濃度のシリコン基板に
あっても、多結晶シリコン膜をその裏面に形成すること
により、そのシリコン基板の内部に形成される酸素析出
物の核の成長が助長されることがわかる。すなわち、十
分な量のゲッタリング源をシリコン基板の内部に確保す
ることができる。この場合、この酸素析出物の周囲に形
成される歪はゲッタリング源として機能することとな
る。すなわち、このシリコン基板３は十分なＩＧ効果を
有することとなる。例えば、その後のデバイス形成工程
において、これらの歪に重金属等が析出される結果とな
る。From this table, even on a silicon substrate having a low oxygen concentration, by forming a polycrystalline silicon film on the back surface thereof, the growth of nuclei of oxygen precipitates formed inside the silicon substrate is promoted. Understand that That is, a sufficient amount of gettering source can be secured inside the silicon substrate. In this case, the strain formed around this oxygen precipitate functions as a gettering source. That is, this silicon substrate 3 has a sufficient IG effect. For example, in the subsequent device forming process, heavy metals and the like are deposited on these strains.
【００１４】また、このシリコン基板３にあっては、多
結晶シリコン膜２の結晶粒界はＥＧ（エクストリンシッ
ク・ゲッタリング）源として作用する。なお、この多結
晶シリコン膜２は、デバイス形成工程にあって酸化工程
等を繰り返すと、それの一部が酸化により消費された
り、多結晶シリコンの再結晶化が起こる。しかし、多結
晶シリコン膜２のこの様な変化が起きても、上記酸素析
出物の成長に起因して、積層欠陥などの二次欠陥がこの
酸素析出物の近傍に高密度に発生し、これが強力なゲッ
ター源として作用し、不純物等を析出させる。つまり、
ゲッター効果が強力で長持ちし、クリーンである。In the silicon substrate 3, the crystal grain boundaries of the polycrystalline silicon film 2 act as EG (extrinsic gettering) sources. It should be noted that if the polycrystalline silicon film 2 is subjected to a device forming step and an oxidizing step or the like is repeated, a part of the polycrystalline silicon film 2 is consumed by the oxidation or recrystallization of polycrystalline silicon occurs. However, even if such a change of the polycrystalline silicon film 2 occurs, secondary defects such as stacking faults are generated at a high density in the vicinity of the oxygen precipitates due to the growth of the oxygen precipitates. It acts as a strong getter source and precipitates impurities. That is,
Strong getter effect, long lasting and clean.
【００１５】さらに、出発原料の単結晶シリコン基板１
の酸素濃度が、従来のＩＧ効果を有する高酸素シリコン
基板より低いので、より完全なＤＺ（無欠陥層）５をシ
リコン基板３の表面（デバイス活性領域）に実現でき
る。また、不純物等のゲッタリング源も、酸素析出物の
周囲の歪、多結晶シリコン膜の結晶粒界、積層欠陥等
で、ＩＧ効果に加え、強力で長持ちするＥＧ効果を得る
ことができる。以上の結果、デバイス特性の劣化、製品
の歩留りの低下をなくすことができる。Further, a single crystal silicon substrate 1 as a starting material
Has a lower oxygen concentration than that of the conventional high oxygen silicon substrate having the IG effect, so that a more complete DZ (defect-free layer) 5 can be realized on the surface (device active region) of the silicon substrate 3. In addition, the gettering source of impurities and the like can obtain a strong and long-lasting EG effect in addition to the IG effect due to strain around oxygen precipitates, crystal grain boundaries of the polycrystalline silicon film, stacking faults, and the like. As a result, it is possible to eliminate deterioration of device characteristics and reduction of product yield.
【００１６】[0016]
【発明の効果】本発明は、以上説明してきたように構成
されているので、格子間酸素濃度の低いシリコン基板に
おいて、十分なＩＧ効果を持つことができる。また、多
結晶シリコン膜によるＥＧ効果を合わせて持つことがで
きる。また、完全なＤＺを得ることができる。そして、
これらの結果として、不純物、重金属等の汚染物質を、
ゲッタリング源に取り込み、基板表面でのデバイス特性
の劣化や、製品歩留りの低下をなくすことができる。Since the present invention is configured as described above, it is possible to have a sufficient IG effect in a silicon substrate having a low interstitial oxygen concentration. Further, it is possible to have the EG effect by the polycrystalline silicon film together. Also, a complete DZ can be obtained. And
As a result of these, contaminants such as impurities and heavy metals,
It can be incorporated into a gettering source to prevent deterioration of device characteristics on the substrate surface and reduction of product yield.
【図１】 本発明の一実施例に係るシリコン基板の製造
方法の工程を示す断面図である。FIG. 1 is a cross-sectional view showing a step in a method for manufacturing a silicon substrate according to an embodiment of the present invention.
１ 単結晶シリコン基板 ２ 多結晶シリコン膜 ３ シリコン基板 ４ 酸素析出物の核 ５ ＤＺ 1 Single Crystal Silicon Substrate 2 Polycrystalline Silicon Film 3 Silicon Substrate 4 Oxygen Precipitate Nucleus 5 DZ
───────────────────────────────────────────────────── フロントページの続き (72)発明者 堀口 清一 埼玉県大宮市北袋町一丁目297番地 三菱 マテリアル株式会社中央研究所内 (72)発明者 降屋 久 埼玉県大宮市北袋町一丁目297番地 三菱 マテリアル株式会社中央研究所内 (72)発明者 島貫 康 埼玉県大宮市北袋町一丁目297番地 三菱 マテリアル株式会社中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiichi Horiguchi 1-297 Kitabukuro-cho, Omiya City, Saitama Prefecture Central Research Laboratory, Mitsubishi Materials Corporation (72) Hisashi Furuya 1-297 Kitabukuro-cho, Omiya City, Saitama Prefecture Central Research Laboratory, Mitsubishi Materials Corporation (72) Yasushi Shimanuki, 297, Kitabukuro-cho, Omiya City, Saitama Prefecture Central Research Laboratory, Mitsubishi Materials Corporation
Claims (1)
格子間酸素を含有している単結晶シリコン基板を準備す
る工程と、 この単結晶シリコン基板の裏面に多結晶シリコン膜を形
成する工程と、 このシリコン基板を１２００℃以上で３０分間以上熱処
理する工程と、 このシリコン基板を１０００℃以下で２時間以上熱処理
する工程と、を有したことを特徴とするシリコン基板の
製造方法。1. A step of preparing a single crystal silicon substrate containing interstitial oxygen of 7.5 × 10 17 atoms / cm 3 or less, and forming a polycrystalline silicon film on the back surface of the single crystal silicon substrate. A method of manufacturing a silicon substrate, comprising: a step of heat-treating the silicon substrate at 1200 ° C. or higher for 30 minutes or more; and a step of heat-treating the silicon substrate at 1000 ° C. or lower for 2 hours or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3265366A JP2762183B2 (en) | 1991-09-17 | 1991-09-17 | Method for manufacturing silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3265366A JP2762183B2 (en) | 1991-09-17 | 1991-09-17 | Method for manufacturing silicon substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0574784A true JPH0574784A (en) | 1993-03-26 |
| JP2762183B2 JP2762183B2 (en) | 1998-06-04 |
Family
ID=17416183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3265366A Expired - Fee Related JP2762183B2 (en) | 1991-09-17 | 1991-09-17 | Method for manufacturing silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762183B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275436A (en) * | 1992-03-24 | 1993-10-22 | Shin Etsu Handotai Co Ltd | Heat treatment of silicon wafer |
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| EP1732114A2 (en) * | 2005-06-09 | 2006-12-13 | Sumco Corporation | Silicon wafer for IGBT and method for producing same |
| WO2010131412A1 (en) * | 2009-05-15 | 2010-11-18 | 株式会社Sumco | Silicon wafer and method for producing the same |
| US8617311B2 (en) | 2006-02-21 | 2013-12-31 | Sumco Corporation | Silicon single crystal wafer for IGBT and method for manufacturing silicon single crystal wafer for IGBT |
-
1991
- 1991-09-17 JP JP3265366A patent/JP2762183B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275436A (en) * | 1992-03-24 | 1993-10-22 | Shin Etsu Handotai Co Ltd | Heat treatment of silicon wafer |
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| EP0635879A3 (en) * | 1993-07-22 | 1996-10-23 | Toshiba Kk | Semiconductor silicon wafer and process for its production. |
| US5738942A (en) * | 1993-07-22 | 1998-04-14 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| EP1732114A2 (en) * | 2005-06-09 | 2006-12-13 | Sumco Corporation | Silicon wafer for IGBT and method for producing same |
| EP1732114A3 (en) * | 2005-06-09 | 2009-09-23 | Sumco Corporation | Silicon wafer for IGBT and method for producing same |
| US7846252B2 (en) | 2005-06-09 | 2010-12-07 | Sumco Corporation | Silicon wafer for IGBT and method for producing same |
| US8617311B2 (en) | 2006-02-21 | 2013-12-31 | Sumco Corporation | Silicon single crystal wafer for IGBT and method for manufacturing silicon single crystal wafer for IGBT |
| WO2010131412A1 (en) * | 2009-05-15 | 2010-11-18 | 株式会社Sumco | Silicon wafer and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2762183B2 (en) | 1998-06-04 |
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