JPH0573406A - Non-alignment data transfer device - Google Patents

Abstract

PURPOSE:To constitute the device so that a fact that it is necessary to transfer non-alignment data stored by stepping across a four-byte boundary by dividing it into two times, in the case data bus width is 32 bits up to the present can be executed by a single transfer. CONSTITUTION:When a memory selecting circuit 8 inputs the lower X addresses Al, AO in the head address and a byte size in the head addresses A32-AO and byte sizes of data to be transferred, outputted from a processor 1, through a byte designating bus 7 and discriminates them as non-alignment data, selecting signals 90-93 are applied to all unit memories for storing the data to be transferred, in unit memories 20-23, and also, the unit memory for storing partial data which does not go across a four-byte boundary is accessed by a Y address on an address bus 24 through address selectors 60-63 and simultaneously, the unit memory for storing the partial data which goes across the four-byte boundary is accessed by an address obtained by adding '1' to the Y address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for completing transfer of so-called unaligned data, particularly in one data transfer. In the following figures, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art FIG. 2 shows an example of the configuration of a memory which is the object of data transfer of unaligned data. In this example, the data bus,
The bit width of each address bus is 32 bits. In the figure, the areas DU numbered as # 0, # 1, ... Are 8-bit unit data areas, and the unit data area DU is 4 bytes (32 bytes) in the horizontal direction as in the example of this figure.
It can be considered that these 4 byte areas are stacked in the vertical direction. An area in which 4 bytes are continuously arranged in the horizontal direction becomes a data area which is transferred to the 32-bit data bus at one time.

At the beginning of each unit data area DU, 32-bit addresses are sequentially allocated in the order of # 0, # 1, # 2, ... Assuming that the address bits are given the symbols A31 to A0 from the beginning, the 4-byte unit data areas DU arranged in the horizontal direction (the beginning)
Can be sequentially specified by the last two address bits A1 and A0, and the 4-byte area that is vertically (vertically) stacked can be sequentially specified by the upper 30 address bits A31 to A2. Here, for convenience, the address bit A
An address composed of 1, A0 is called an X address, and an address composed of address bits A31 and A2 is called a Y address. Further, an end address of a 4-byte area having the same Y address (in one horizontal row) is called a 4-byte boundary or generally a Y address boundary for convenience.

The data stored in the memory of FIG. 2 consists of variable length data of 1 byte to 4 bytes, and this data is number # 0, # 1, of the unit data area DU of FIG.
The order of ... Is read into this memory. In this way, the variable byte length data area stored in the memory is designated by the head addresses A31 to A0 and the subsequent 2-bit byte sizes Siz1 and Siz0. FIG. 3 shows the relationship between the values of the byte sizes Siz1 and Siz0 and the byte size (represented by the number of bits in FIG. 3) in this example. By the way, the data (the code is DIR) including the unit data areas DU of thick black frames # 6 to # 9 in FIG. 2 has A31 ... A0 = 0 ... 0110 (that is, X) as the start address.
Address A1, A0 = 1, 0, Y address A31 ... A2
= 0 ... 01) Also, as the byte size following this, Siz
The data is the area specified by 1, Siz0 = 0, 0 (that is, 4 bytes long). The head side 2 bytes of this data DIR (areas # 6 and # 7) have Y addresses A31 ... A2 = 0.
.. 01, but the last 2 bytes (areas # 8 and # 9) are at the next adjacent Y addresses A31 ... A2 = 0. The data stored over the two (two) regions having different Y addresses in the memory is called unaligned data.

Conventionally, when a bus master as a data transfer activation source transfers the unaligned data DIR as described above, the data transfer is performed twice based on the above-described area designation of the unaligned data. It was That is, in the first data transfer, the bus master outputs the start addresses A31 to A0 of the access target data, and the 4-byte area of the same Y address as the start address (# 4 to # in the example of FIG. 2).
7 unit data area DU, that is, # 6, # from the beginning to the Y address boundary for the data DIR.
Data transfer (of unit data area DU of 7) is executed. Subsequently, the bus master outputs the address at a position beyond the 4-byte boundary as the second data transfer, and the 4-byte area of the next Y address (in the example of FIG. 2, the unit data area DU of # 8 to # 11, That is, the remaining data transfer (of the unit data areas DU of # 8 and # 9) is executed for the data DIR.

[0006]

As described above, the conventional unaligned data transfer method requires a plurality of data transfers from the bus master to the bus slave, and the access time is longer than that of the data transfer not crossing the Y address boundary. growing. In addition, when the data arrangement is changed, the number of non-aligned data transfers changes, resulting in a change in the data transfer performance of the same system. Therefore, it is an object of the present invention to provide a non-aligned data transfer device capable of transferring non-aligned data at one time.

[0007]

In order to solve the above-mentioned problems, the unaligned data transfer device according to claim 1 has a plurality of common unit widths (e.g., 8 bits) (e.g., 4 pieces) constituting a data bus. A memory group including unit memories (20 to 23, etc.) having the same structure, which are respectively connected to the unit data buses (30 to 33, etc.), and each data area (unit data area DU, etc.) in the unit memory of this memory group ), The lower addresses (X addresses A1, A0, etc.) of addresses (A31 to A0, etc., hereinafter referred to as group addresses) are sequentially allocated to the unit memory, and higher addresses (Y address A31) following the lower addresses of the group addresses are sequentially allocated. ~ A2 etc.) is shared between the unit memories and the memory group formed by sequentially allocating the addresses of the unit memories (hereinafter referred to as unit addresses) to the data. The transferred data having a length equal to or less than the width (32 bits, etc.) of the unit data bus and an integer multiple of the unit data bus, the group address (hereinafter referred to as the start address) indicating the start position of the transferred data. And the data length of the transferred data (byte size Siz1, Siz0, etc.) is specified, and the lower address in the start address and the data length of the transferred data are specified (byte specification). Whether the transferred data is non-aligned data (DIR, etc.) that is input over the bus 7 or the like and transferred across two adjacent areas of the unit address of the unit memory that constitutes the memory group. When it is determined that the data is non-aligned data, the unit memory having the same unit address as the head portion of the transferred data as the transfer destination on the head side of the transferred data is At the same time the upper address of the start address is accessed via the address bus 4, address selectors 60 to 63, etc., the unit memory having the unit address adjacent to the unit address as the transfer destination on the end side of the transferred data is ( A means for accessing with a higher-order address obtained by adding 1 (via adders 50-53, etc.) to the higher-order address in the start address concerned (by giving addition specification signals 100-103 to the address selectors 60-63, etc.) Memory selection circuit 8 etc.)
Shall be provided.

[0008]

When the bus master requests the unaligned data transfer, the bus slave is provided with a mechanism for incrementing the Y address by 1 for the data access exceeding the Y address boundary.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is a processor as a bus master, and the parts other than this processor 1 are bus slaves. Numerals 20 to 23 are data buses each having a 32-bit width as a whole, and each unit data bus 30 is provided for each byte.
Is a unit memory connected to the processor 1 via .about.33. Each area in the unit memories 20 to 23 is divided byte by byte in ascending order of addresses. The unit data buses 30, 31, 32 and 33 have data lines D31 to D4, D23 to D16, D15 to D8 and D7 to respectively.
It consists of D0. 4 is the above-mentioned Y address A31 of the 32-bit addresses A31 to A0 output by the processor 1.
Address bus for outputting ~ A2, 7 is also the processor 1 for the above-mentioned X addresses A1, A0 and byte size S
This is a byte designation bus for outputting iz1 and Siz0.

5 (50 to 53) are unit memories 20 to 50, respectively.
The Y address of the address bus 4 is incremented by 1 by the adder provided corresponding to 23. 6 (60 to 63) select the Y address on the address bus 4 or the Y address after the Y address has passed through the adders 50 to 53 (that is, are incremented by 1), and the corresponding unit memories 20 to 23 are selected. The address selectors 10 (100 to 103) given to the address selectors 60 to 63 are addition designation signals for causing the address selectors 60 to 63 to select the Y address incremented by +1. Numeral 8 determines whether the transfer data is unaligned data from the signal (address information) of the byte designation bus 7, and determines which of the memory selection signals 9 (90 to 93) corresponds to the required unit. Memory 2
0 to 23, and when it is unaligned data,
Any of the necessary addition designating signals 100 to 103 is output to the corresponding address selectors 60 to 63, respectively.

It is assumed that the starting address of the memory group consisting of the memory unit memories 30 to 33 is assigned to address 0, and the processor 1 has a size of 4 bytes from address 2 of 32-bit addresses A32 to A0 for the entire memory group. 2 is accessed, that is, address 2 of the memory group (# 2 area of the unit memory 22 in FIG. 2), address 3 (# 3 area of the unit memory 23 in FIG. 2), address 4 (diagram of the unit memory 20). # 4 area of 2), address 5 (unit memory 21
Consider the case where the non-aligned data DIR stored over the area # 5 in FIG. 2) is transferred. At this time, the processor 1 specifies this non-aligned data DIR by outputting its head address A31 ... A1, A0 = 0 ... 1,0 and byte sizes Siz1, Siz0 = 0,0 (4 byte size). Therefore, the lower 2 bits (X address) A1 and A
The byte size of 0 = 1,0 is output. In addition, the upper 3 bits of this start address are stored in the address bus 4.
0 bits (Y address) A31 ... A2 = 0 ... 0 are output. That is, of the 4 bytes of the unaligned data DIR, the former 2 bytes (addresses 2 and 3) of the Y addresses A31 to A2 are addresses 0, and the remaining 2 bytes (4
The Y address of the address, address 5) is address 1.

Now, in this data transfer, the processor 1
Since the lower two bits A1 and A0 of the address information output by the above function as the byte designation bus 7, the address bus 4 (that is, at the Y addresses A31 to A2 = 0) designates the previous two unit memories 22. And 23. In the conventional technique, only these two unit memories are accessed, and the access to the unit memories 20 and 21 is sent to the next data transfer. However, in the present invention, the memory selection circuit 8 makes all the memory selection signals 90 to 93 valid by judging from the information of the byte designation bus 7, and the address selectors 60, 61 corresponding to the unit memories 20, 21.
Only the addition designation signals 100 and 101 for are valid. Then, the unit memories 22 and 23 are directly accessed by the address output from the processor 1 to the address bus 4 (that is, the Y address = 0 address), and the unit memories 20 and 21 are accessed from the processor 1 to the address bus 4 by Y.
Since the address is accessed at the Y address obtained by adding 1 to the addresses A31 to A2 (that is, the Y address 1), the transfer of 4 bytes of the unaligned data DIR can be completed by one data transfer.

[0013]

According to the present invention, the bus master (processor) 1 receives the address information (X addresses A1, A0 and byte sizes Siz1, Siz0 in this example) output on the byte designation bus 7, and When it is determined that the transferred data is non-aligned data, the unit memory storing the data of the part that does not cross the Y address boundary of the other transferred data is output to the address bus 4 as it is ( The Y addresses A31 to A2 (as upper bits of the start addresses A31 to A0) are accessed, and at the same time as this access, the above Y address A31 is applied to the unit memory that stores the data of the portion of the transferred data that exceeds the Y address boundary. Since access is made at the Y address obtained by adding 1 to ~ A2, the speed of non-aligned data transfer is made equal to that of normal aligned data transfer. This improves the data transfer performance of the bus. Further, the performance is not significantly affected by the data arrangement, and stable data transfer performance can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration as an embodiment of the present invention.

FIG. 2 is a block diagram of a memory for explaining unaligned data.

FIG. 3 is an explanatory diagram of data specified by byte size.

[Explanation of symbols]

 1 processor (bus master) 20 to 23 unit memory 30 to 33 unit data bus 4 address bus 4 A31 to A2 Y address 50 to 53 adder 60 to 63 address selector 7 byte designation bus A1, A0 X address Siz1, Siz0 byte size 8 Memory selection circuit 90 to 93 Memory selection signal 100 to 103 Addition designation signal DU Unit data area DIR Unaligned data

Claims (1)

[Claims] 1. A memory group comprising unit memories of the same structure, each of which is connected to a plurality of unit data buses having a common unit width forming a data bus, wherein each data area in the unit memory of the memory group is Lower addresses of designated addresses (hereinafter referred to as group addresses) are sequentially allocated to the unit memory, and upper addresses following the lower addresses of the group addresses are shared by the unit memories as addresses of the unit memory (hereinafter referred to as unit addresses). Between the memory groups that are sequentially allocated, the length is less than the width of the data bus,
The transferred data having a length that is an integral multiple of the unit data bus is specified by specifying the group address (hereinafter referred to as the start address) indicating the start position of the transferred data and the data length of the transferred data. In the transfer device, the lower address in the start address and the data length of the transferred data are input, and the transferred data is spread over two adjacent areas of the unit address of the unit memory forming the memory group. If it is determined that the data is unaligned data that is transferred, the unit address that is the same as the beginning of the transferred data is used as the transfer destination on the leading side of the transferred data. At the same time as accessing the unit memory with an upper address of the start address, the unit address adjacent to the unit address is transferred to the transfer destination on the end side of the transferred data. Unaligned data transfer apparatus of the unit memory characterized by comprising means for accessing the upper address formed by adding 1 to the upper address in the start address of the to be.