JPH0573298A - Tag comparing mechanism - Google Patents

Abstract

PURPOSE:To easily and quickly compare only the prescribed bit of a tag part by setting the prescribed bit of the compared result outputted from a comparing part to the content decided beforehand by a compared result operating part and detecting the coincidence of a tag based on the compared result including the set bit. CONSTITUTION:This mechanism is provided with a comparing part EORG 1 to constitute the data of 1 unit of a value part and a tag part, compare the tag part of plural data for each bit to constitute the tag part and output plural compared results for each bit and a compared result operating part 5 to fix forcibly any compared result out of plural compared results to the content set beforehand. Based on the output of the compared result operating part 5, a coincidence detecting part (zero detector) 2 detects the compared result of the tag part. Here, a tag comparing enable register 3 and an AND gate 4 constitute the compared result operating part 5. Then, the increase of the degree of freedom of a program to use the tag part and the efficient use of the tag part can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tag section comparing mechanism for comparing tag sections of a plurality of data, each unit consisting of a value section and a tag section.

[0002]

2. Description of the Related Art One unit (1
The data format of the word) consists of only the value part where the data value is set, and in addition to this value part, the attributes of the data value set in the value part, such as floating point and fixed point, single There is a format provided with a tag part in which information (data type) for distinguishing precision and double precision and characters and numbers is set.

In a processor that handles data having such a tag portion and a value portion, for example, when performing comparison or addition / subtraction of a pair of data, it is necessary to compare the tag portions and check whether the data types match. There is. This is done in order to avoid a situation in which data values having different data types, for example, character values and numerical data values are compared or added / subtracted. Here, a mechanism that executes the process related to the comparison of the tag units will be referred to as a tag comparison mechanism.

FIG. 2 shows a block diagram of a conventional tag comparison mechanism. As shown in the figure, the conventional tag comparison mechanism 10
The exclusive-OR gate (EORG) 1 and the zero detector 2 consisted of a comparison unit. EORG1 performs an operation for each corresponding bit of a pair of data composed of n bits (bits), for example, 1st bit (0 bit), 2nd bit (1 bit), 3rd bit (2 bits), ... The result is output. For example, when n = 8, the total number of inputs is 16 bits and the output is 8
Become a bit.

The zero detector 2 is composed of, for example, a NOR circuit (logical sum negation circuit) for determining whether all the bits of the input data (output of EORG1) are "0". To the input of EORG1, n-bit data TagA of the tag part set in one data and n-bit data TagB of the tag part set in the other data are input. Data TagA
And the data TagB are calculated in EORG1 and input to the zero detector 2 as n-bit data TagC. In the zero detector 2, it is determined whether or not all the bits of TagC are "0", and if the result is affirmative, that is, if all the bits are "0", it is valid (content "1"). Output the tag judgment data TagEq.

The conventional tag comparison mechanism will be described below with reference to FIG. FIG. 3 shows an operation explanatory view of the conventional tag comparison mechanism. First, the data of the tag part TagA, TagB
Will be described as being composed of 7 bits (n = 7) of bits 0 to 6. Then, it is assumed that the content of the data TagA is “1100011” and the content of the data TagB is “1100011”.

When the operation of these data is carried out in EORG1, the data TagC having the content "0000000" becomes EORG1.
Is output from. Upon receiving the data TagC, the zero detector 2 determines whether all the n bits are zero. In this case, since all are zero, the tag determination data Ta with the content “1”
Output gEq. In the processor, this tag judgment data
When TagEq is recognized, it is assumed that the value parts of the data related to the data TagA and the data TagB have the same data type, and arithmetic processing such as comparison of the value parts is performed.

[0008]

Now, contents other than the data type of the value part in the tag part, for example, the 8th bit (7
Bit) may have information of Garbage Collection (GC). During the processing of the GC, the contents of the bits having the GC information may be different even if the data is in use. When there is a possibility that the GC processing and the comparison processing may be performed at the same time as in the parallel GC processing, there may occur a situation in which data (tag portions) having different bit contents having the GC information are compared with each other. .. In this state, if all the bits of the tag part are to be compared, even if the data types match, there is a problem that they are handled as value parts of different data types due to the difference in GC.

For this reason, conventionally, a GC bit mask (cut out of 0 to 6 bits) is performed and 7-bit data Ta is used.
A mechanism for generating gA, TagB was proposed, but a mask,
That is, there has been a problem that a complicated logic circuit is required to cut out a bit and that a special processing time is required in addition to the comparison of the tag portion. The present invention has been made in view of the above points, and provides a tag comparison mechanism capable of easily and quickly comparing only predetermined bits of a tag portion without spending a complicated logic circuit or special processing time. The purpose is to do.

[0010]

According to the tag comparison mechanism of the present invention, one unit of data is composed of a value part and a tag part, and the tag part of a plurality of the data is set for each bit forming the tag part. And a comparison result operation unit for forcibly fixing one of the comparison results of the plurality of comparison results to a preset content. And a match detection unit for detecting the comparison result of the tag unit based on the output of the comparison result operation unit.

[0011]

This mechanism sets a predetermined bit of the comparison result output from the comparison unit to the content determined in advance in the comparison result operation unit. The match detection unit detects a match between the tag units based on the comparison result including the bit newly set in the comparison result operation unit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of a tag comparison mechanism of the present invention. As shown in the figure, the tag comparison mechanism 1 of the present invention
1 is an exclusive-OR gate (EORG) 1, a zero detector 2,
It is composed of a tag comparison enable register (TCER) 3 and an AND gate (ANDG) 4. The EORG 1 and the zero detector 2 are the same as the conventional one described above with reference to FIG. The tag comparison enable register 3 and the AND gate 4 are collectively referred to as a comparison result operation unit 5 here.

TCER3 is a register for storing data SetTCER having the same number of bits as the number of bits forming the tag portion. Each bit of this TCER3 (data SetTCER) corresponds to each bit of TagC output from EORG1, and has a one-to-one correspondence from the most significant bit to the least significant bit. Further, in this case, in the data SetTCER, the bit corresponding to the bit of the data TagC forcibly setting the content to “0” (predetermined content) is set to the content “0”.
For example, when forcibly setting only the 8th bit corresponding to the GC of the data TagC to "0", the data SetTCER
The content of is "01111111". The outputs of EORG1 and TCER3 are input to ANDG4. The output of ANDG4 is input to the zero detector 2.

The tag comparison mechanism of the present invention will be described below with reference to FIG. FIG. 4 shows an operation explanatory diagram of the tag comparison mechanism of the present invention. First, the data of the tag part TagA, T
The description will be made assuming that agB is composed of 8 bits (n = 8) in which 1-bit GC is set at the most significant position. Then, the content of the data TagA is unmarked (GC = 0)
“01100011” indicating that the content of data TagB has been marked (G
It is assumed that it is “11100011” indicating C = 1). Furthermore,
It is assumed that the TCER3 stores the data SetTCER with the content "01111111".

First, when the operation of the data TagA, TagB is executed in EORG1, the data TagC of which the content is "10000000"
Is output from EORG1. The ANDG4 calculates the data TagC and the data SetTCER and outputs the data TagD having the content "00000000". Upon receiving the data TagD, the zero detector 2 determines whether all n bits are zero. In this case, since all are zero, the tag determination data TagEq with the content “1” is output. When the processor recognizes the tag determination data TagEq, it determines that the value parts of the data relating to the data TagA and the data TagB have the same data type, and performs arithmetic processing such as comparing the value parts. As described above, by setting the content of the data SetTCER stored in TCER to "0", the desired bit on the data TagD can be set to the content "0". There is no influence on the detection result, that is, the influence of setting the data TagEq to the invalid content “0”.

[0016]

As described above, according to the present invention,
Since only the arbitrary bits in the tag part can be meaningful as the target of comparison, contents other than the data type can be set in the arbitrary bits in the tag part, and the flexibility of the program that uses the tag part can be increased. It is possible to increase the number and efficiently use the tag part. In addition, a special logic circuit for cutting out a desired bit from the tag unit and a processing time are not required, and the tag units can be easily and quickly compared.

[Brief description of drawings]

FIG. 1 is a block diagram of a tag comparison mechanism of the present invention.

FIG. 2 is a block diagram of a conventional tag comparison mechanism.

FIG. 3 is an operation explanatory view of a conventional tag comparison mechanism.

FIG. 4 is an operation explanatory view of the tag comparison mechanism of the present invention.

[Explanation of symbols]

 1 exclusive-OR gate (comparison unit) 2 zero detector (match detection unit) 3 tag comparison enable register 4 AND gate 5 comparison result operation unit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Akira Yamamoto 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. In-house

Claims (1)

[Claims] 1. A unit of data is composed of a value part and a tag part, the tag parts of a plurality of the data are compared for each bit constituting the tag part, and a plurality of comparisons are made for each bit. A comparison unit that outputs a result, a comparison result operation unit that forcibly fixes one of the comparison results of the plurality of comparison results to a preset content, and based on the output of the comparison result operation unit A tag comparison mechanism comprising a match detection unit for detecting a comparison result of the tag unit.