JPH0572132B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to variable attenuators, particularly broadband variable attenuators using field effect transistors (FETs).

[Prior art and its problems] A variable attenuator is generally used to control the gain of a cascade amplifier. To obtain gain flatness (ie, uniformity of gain over different frequencies) and stability of the amplifier, the attenuator preferably has a low VSWR of the source and load, regardless of the attenuation value. It is also essential to maintain the impedance of the transmission line circuit constant. This precludes the use of reflective attenuators.

The classic Bridge T-type attenuator was introduced in 1968.
It is described in the 5th edition of Reference Data for Radio Engineers, published by ITT/Howard W. Sams & Company, and is shown in Figure 7A. In this circuit, a continuously variable absorbing attenuator can be obtained by changing the series resistance R1 and the parallel resistance R2 so as to satisfy the following equation (1).

R1R2=Z0 ² (1) where Z0 is the desired characteristic impedance. The degree of attenuation during matching is given by equation (2).

Attenuation (dB) = 20log ((R1/R2) ^1/2 + 1) = 20log ((R1/Z0) + 1) (2) To make the Bridge T-type attenuator a continuously variable type,
The series-parallel resistors R1 and R2 in FIG. 7A may be replaced with FETs operating in a linear region as shown in FIG. 7B.

However, in practice, conventional variable FET attenuators experience undesirable impedance changes as the degree of attenuation and operating temperature changes.

Other examples of variable attenuators are disclosed in R. Chattopadhyay et al., Proceedings RF Technology EXPO 86, January 1986, pages 573-574. This attenuator uses individual PIN diodes as variable resistors to provide an attenuator for the 1MHz to 500MHz band. The product of R1R2 is an exponential function as shown in the following equation.

R1R2=K1e(KT/V ₁ +V ₂ ) where K1 is a constant, T is temperature,
k is Boltzmann's constant. This circuit is temperature sensitive and in practice constants such as K1 will vary depending on the device used. Additionally, complex active and inductive DC control circuits are required to control and bias the current through the diode. Finally, this circuit is unlikely to work over a wide microwave frequency range.

Gallium arsenide (GaAs) monolithic microwave integrated circuits (MMICs) have recently entered the market from the development stage. Most MMICs currently on the market are gain blocks, with some exceptions.
An example of MMICs is L. Larson et al.'s Proc.1985 IEEE
"GaAs Differential Amplifier" in GaAs IC Symp. pp. 19-22, Proc. 1981 IEEE GaAsIC by J. Bouhaus et al.
"Monolithic Dual-Gate GaAsFET Digital Phase Filters" in Symp. Paper 35, "A New Particularly Monolithic Approach to Microwave Power Amplifiers" in D. Publicis et al., 1983 IEEE Microwave and Millimeter Wave Monolithic Circuits Symposium, pp. 54-58. , Y. Ayasri et al., March 1984 IEEE
Trans.Microwave Theory Tech.Vol.MTT−
32, pp. 290-295, “2-20 GHz GaAs Traveling Wave Power Amplifier” and K. Johns et al., Proc. 1985.
IEEE GaAsIC Symp., pp. 137-140, ``1-10 GHz Tapered Distributed Amplifier in Hermetic Surface Mount Package''. Additional microwave "building blocks" are not yet commercially available, primarily because microwave designs are application specific and not general purpose.
GaAs MMICs have a wide range of applications and bands, so MMICs with standard features must be carefully selected. Otherwise, the quantity of MMICs cannot be reduced to achieve low cost per unit, which is one of the main objectives of monolithic circuits.

Therefore, there is a need for improved variable attenuators, particularly radio frequency variable attenuators that have substantially constant impedance and low return loss over a wide microwave frequency range.

OBJECTS OF THE INVENTION Accordingly, one object of the present invention is to improve the operation of variable FET attenuators, particularly in the microwave frequency range.

Another object of the invention is to minimize the temperature dependence of variable RF attenuators.

Still another object of the present invention is to reduce the dependence of the RF variable attenuator on variations in the parts used.

Another object of the invention is to provide an economical variable attenuator with a wide range of applications.

SUMMARY OF THE INVENTION The variable attenuator of the present invention uses feedback within the control loop to automatically compensate for input/output return loss as the attenuator is varied by a control signal input. To properly match the input to the desired attenuation value, the series and parallel variable FETs must be set to the correct conductance. According to the invention, the second or reference attenuation circuit provides feedback control of the main attenuation circuit via an operational amplifier. This reference circuit is particularly relevant to impedance.
It is designed to be electrically equivalent to the main attenuation circuit. The control nodes, attenuation control inputs and operational amplifier outputs are the same, ensuring that the reference and main attenuation circuits operate similarly. This configuration eliminates the need for RF decoupling of the feedback loop from the attenuation circuit. If there is RF coupling, it will change the S-parameters of the attenuator, leading to undesirable results.

Preferably, the same circuit as the main attenuation circuit is used for the reference circuit. High precision matching is achieved when both circuits are fabricated on the same monolithic integrated circuit (IC) board along with the operational amplifier. Although the present invention is suitable for an attenuator using a bridge T-type variable attenuator, it may also be a symmetrical T-type or symmetrical π-type variable FET attenuation circuit. The variable attenuator configured in this way has temperature compensation and parallel
Performs automatic biasing of the FET gate voltage.

In a preferred embodiment, a wideband monolithic GaAs bridge-T variable attenuator is combined with a similar reference circuit to terminate at a characteristic impedance, yet approximately
By using on-chip GaAs with a stable band of 100 MHz and constructing it as described above, the internal input/output return loss can be optimized over the band of 1-10 GHz.

[Example] (Description of FET variable attenuator) Prior to explaining the present invention, a general FET variable attenuator will be briefly explained. The channel resistance of a linearly operating FET is determined by approximately 1/Gmsat depending on the gate-source voltage vgs. Here, Gmsat is the mutual conductance in the saturation region. Drain current Ids and drain voltage Vds
The relationship between is given by the following equation.

Ids=2β0(Vgs−vp)VdsW/L≈GmsatVds (3) Here, W and L are the gate width and length of the FET, respectively, and Vp is the pinch-off voltage.
For GaAsFETs, the transconductance parameter β 0 is given approximately by μ es /2a, where μ is the channel electron mobility, es is the dielectric constant of GaAs, and a is the channel thickness data. It can be seen from equation (3) that the channel resistance Vds/Ids depends on β0 and Vp related to the GaAs process.

The next task is to control the product of the series and parallel channel resistances to achieve the correct attenuation behavior.

For FETs of equal characteristics, maintaining the correct return loss at all degrees of attenuation requires the following relationship between the voltages applied to the GaAs FET of FIG. 7A, ie, the series and parallel gate voltages Vgs1 and Vgs2.

(Vgs2−Vp)=L ² /4W ² β ₀ ² Z ₀ ² (Vgs1−Vp) (4) At low frequencies, the attenuation of series and parallel FETs with equal characteristics that satisfy equation (4) is given by the following equation. Given.

Attenuation degree (dB) = 20LOG {(Vgs2−Vp/Vgs1−Vp) ^1/2 +
1} = 20log (L/2Wβ ₀ Z ₀ (Vgs1-Vp) + 1) (5) Fortunately, regardless of the variations in characteristics due to the FET manufacturing process and other factors, the input /
Feedback can be used to control output return loss.

Next, a description will be given based on a preferred embodiment of the present invention shown in FIG. The figure shows Bridge T-type attenuator cell 1.
0, a combination of a reference attenuation cell 12 and an operational amplifier 14. (Input protection and level shifting circuits for the control inputs are not shown.) The impedance of this circuit to the RF input and output signals is e.g.
Adjust the gate voltage of the parallel FET of the attenuation cell according to the change in the gate data voltage of the series FET so that the voltage becomes 50Ω.

This circuit has an attenuated signal input 16. This input 16 is coupled via a resistor 18 of the damping cell 10 to the gate of a series FET 20. Series FET
The source and drain of 20 are series capacitors 26
and 28 are symmetrically connected to the RF input/output terminals 22-24. These capacitors are for DC blocking, and the circuit performs appropriate level shifting (not shown) to allow operation from a single power supply. To extend the frequency band to low frequencies, these capacitors may be removed. series
Parallel from the source and drain of FET20 respectively
A pair of 50Ω resistors 30-3 at the drain of FET34
Connect 2. The source of the parallel FET 34 is connected to ground or a suitable reference voltage source (hereinafter referred to as ground). The attenuation cell 10 in this example has the same input/output characteristic impedance of 50Ω. parallel
The gate of FET 34 is connected to control signal line 38 via resistor 36. As discussed below, a control signal is applied via signal line 38 to the gate of parallel FET 34 to control its conductance in response to changes in the attenuator control signal. Resistors 18 and 36 are
It is for RF attenuation of FETs 20 and 34 and has no other significant effect on the operation of this attenuation circuit.

Reference (attenuation) cell 12 preferably has the same input/output characteristic impedance as variable attenuation cell 10 and is configured to be electrically equivalent. Ideally, this reference attenuation circuit 12 has the same configuration as the main attenuator, and the parameters of the parts used are also the same. The gate of series FET 40 is connected to control signal input 16, and the source and drain are connected to nodes 42 and 44, respectively. a pair of
50Ω resistors 50-52 are connected to the source node 42 and drain node 44 of the series FET 40 and the parallel FET, respectively.
It is connected between 54 and 54. The source of FET 54 is connected to ground or a suitable reference voltage source, and its gate is connected to control line 38. The source of the series FET 40 is a 50Ω resistor 5 connected between node 42 and ground.
6 terminates.

Operational amplifier 14 is a differential-to-single-ended conversion type amplifier, and its positive voltage input is connected to node 44 and its negative voltage input is connected to node 46.
A voltage source VDD 62 is connected to each node 44-46 through the same resistor 64-66. Additionally, node 46 is connected to ground through a 50Ω resistor 68 to node 4.
6. Determine the reference voltage. It also serves to terminate the bridge T attenuator reference cell 12 via amplifier 60. Amplifier 60 connects conductor 7 to voltage source VDD
It receives operating power from conductor 72 to 0 and negative supply -Vss.

Figure 2 shows the GaAs used in the attenuator design shown in Figure 1.
A circuit diagram of an operational amplifier 60 is shown. This amplifier 60
includes an input differential amplifier pair 74 with a common mode bias circuit 76, a pair of differential level shift stages 78, a differential-to-single-ended conversion stage (DSE) 80, and an output stage 8, as disclosed in U.S. Pat. No. 4,616,189.
2 and has an open loop gain of approximately 50 dB. DSE stage 80 is commonly used in NMOS designs,
GaAs daypresion mode technology has recently been established. Since high frequency performance is not the goal of this amplifier, sufficient pole compensation is used to limit the bandwidth to below 100MHz to improve stability.

This amplifier 60 outputs a control signal on output lead 38. The control signal is varied by the reference output signal at node 44 which is varied by an attenuated control signal applied to control terminal 16. The control signal on the output line 38 is fed back to the gate of the parallel FET 54 to control the reference circuit operation, and is further fed back to the gate of the parallel FET 54 via the resistor 36.
It is also applied to the gate of No. 34. This operational amplifier 60
operates such that the conductance of parallel FET 54 of reference cell 12 equalizes the voltages at nodes 44 and 46. As a result, the impedance of node 44 is made equal to that of node 46. The same control signal is also applied to FET 34, causing attenuation cell 10 to operate similarly to reference cell 12. That is,
The control signal controls the conductance of FET 34 so that the voltage at the source and drain of FET 20, which is connected to ground through FET 34, is equal to the voltage at node 44. This causes the input/output impedance of the main attenuator cell to be equal to the impedance of node 44 of reference cell 12, which in turn is equal to the constant impedance of node 46. Therefore, even if the degree of attenuation in the attenuator cell 10 changes due to the attenuation control signal, the input/output impedance of the attenuator cell 10 remains constant.

The concept of controlling the RF attenuation cell 10 using DC parameter feedback of the reference cell was initially developed using two
This was confirmed using a GaAsFET bridge T attenuator and a 741 type operational amplifier. Next, this concept is applied to the damping cell 1
0, reference cell 12 and operational amplifier 14 are integrated into a single
It was fabricated on a GaAs chip and implemented at the monolithic level. This GaAs integrated circuit is a high-yield
Using 1μm ion implantation technique, stable termination
NiCr resistors were used, and MIM capacitors were used for bypass and decoupling capacitors. The circuit is then mounted in an airtight surface mount package as disclosed in US Pat. No. 4,668,920. Using the DC parameter requires applying a sufficient voltage to the reference attenuation cell to obtain a signal level that the operational amplifier can detect, but at a value that does not cause the FET to deviate from its linear operating region. In this design, the FET source and drain voltages are
Preferably it is less than 200 mV and operates from a single 9-15V power supply with appropriate level shifting circuitry.

There are several considerations when using FETs as series and parallel devices. Select the gate width of the FET to be sufficiently large so that the insertion loss is small in the lowest attenuation state, but the parallel drain-source capacitance Cds
is selected such that it is possible to limit the amount of noise, so that isolation at high frequencies in the maximum attenuation state is sufficient. Therefore, we selected a series and parallel gate width of 300 μm. Maximum attenuation is in series
Since it depends most on the Cds of the FET, the number of gate comb teeth in the device was minimized to reduce the additional source-drain capacitance caused by interconnect parasitics in the comb-shaped device structure. Losses due to the metal resistance of the wide gate comb teeth do not affect the RF operation of the attenuator.

FIG. 3 shows the transmission characteristics of the packaged attenuator. The five characteristic curves shown here are each different5.
corresponds to two signal levels. The voltages shown here were level shifted to operate the attenuator from a single supply. The gain slope for the lowest attenuation is due to the skin effect loss due to the package and from the die edge to the RF attenuation cell.
This is caused by the synthesis of losses in the microstrip structure on GaAs. The minimum attenuation is 3.5dB at 1GHz and increases to 5dB at 10GHz. In this design, the gate-source voltage Vgs of both FETs must never become positive. If Vgs is made positive near the forward conduction point, the minimum attenuation is improved by about 1 dB.
The effect of the series FET on the maximum attenuation of Cds increases visibly at high frequencies. Attenuation range is 1GHz
17dB, which decreases to 10dB at 10GHz.

Figure 4 shows the case where an on-chip correction circuit is used.
The return loss of a packaged attenuator is shown as a function of frequency. Return loss exceeds 12dB in the 1-10GHz band. This shows that the circuit of FIG. 1 optimizes input/output return loss when varying the attenuation. The input/output voltage standing wave ratio (VSWR) of the packaged attenuator is better than 1.7:1 over the 1-10 GHz range.

Variations As mentioned above, the preferred embodiment of the present invention uses a bridge-T damping circuit and a reference circuit. However, the present invention should not be limited to such embodiments, and various modifications and changes can be made without departing from the gist of the present invention.

The invention can also be implemented using a symmetrical T-shaped circuit as shown in FIG. The general circuit configuration is similar to that of the attenuator shown in FIG.
A, a reference cell 12A and an operational amplifier 14A. Two FETs connected in series as series FETs
Using 20A, connect the source and drain to RF I/O2
Connect between 2A and 24A. The gate of each FET is
It is connected to the attenuation control input terminal 16 via an RF isolation resistor 18A. Parallel FET34A is 2
It has a drain and a source connected between the connection point of the series FETs 20A and ground, respectively. The same goes for the reference cell 12A, which has two series FETs.
It has 40A and parallel FET54A. The output 38 of the operational amplifier 60 is connected to the FET 34 via a resistor 36A.
It is connected to the gate of FET 54A as well as to the gate of FET 54A. As yet another embodiment, an example of a symmetrical π-type variable attenuator is shown in FIG. In this circuit, both the attenuation cell 10B and the reference cell 12B have one series FET 20B and 40B and two parallel FETs.
34B and 54B are used to form a symmetrical π-type circuit configuration. The output 38 of the operational amplifier 60 is connected to the resistor 36B.
It is connected to the gates of both FETs 34B and also to the gate of the parallel FET 54B.

In each of these other embodiments, the specific impedance between the RF I/O of the attenuator and the ground is used as the reference attenuation cell 12B.
It is maintained at a constant value determined by the impedance Z0 between node 46 and ground.

The circuit parameters shown in Figure 1 are the third and fourth
This is a specific example of obtaining the test results shown in the figure. Of course, this parameter can be freely changed depending on the application. As mentioned above, electrical equalization between the attenuation cell and the reference cell is preferred to obtain the same characteristic impedance and equalize the circuitry of each cell. Equalization can also be achieved by appropriately scaling the FET width and characteristic impedance between both cells. For example, the 50Ω resistor in FIG. 1 may be a 100Ω resistor, and the width of the FET of the reference cell 12 may be 150 μm.

The concept of using DC parameter feedback of reference cell 12 to control attenuation cell 10 is in no way limited to the use of the output of operational amplifier 60 to control the gates of parallel FETs. If the attenuator control signals are parallel
Those skilled in the art will readily understand that the same principles can be used to control the gates of series FETs if applied to the gates of the FETs.

[Effects of the Invention] As is clear from the above description, according to the variable attenuator of the present invention, at least two FETs are inserted into the series and parallel signal paths, respectively, and the attenuation amount is made continuous or stepwise by controlling the gate voltage. When changing to
Using a similar reference cell to which the same control signal is applied, supplying the output of the reference cell to the non-inverting input terminal of an operational amplifier and the constant voltage across a resistor of a given impedance to the inverting input terminal, its output is applied to the gates of the parallel FETs of the attenuator cell and the reference cell. As a result, the characteristic impedance can always be maintained equal to the impedance of the resistor regardless of changes in the amount of attenuator in the attenuator cell.
This has the remarkable effect of providing an attenuator with stable characteristics over a wide range of 10 GHz or more.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a preferred embodiment of a variable attenuator according to the present invention, FIG. 2 is an example of a circuit of an operational amplifier used in FIG. 1, and FIGS. Measurement results of electrical characteristics, Figures 5 and 6 are circuit diagrams of other embodiments of the variable attenuator of the present invention, Figure 7A
and FIG. 7B show principle diagrams of conventional fixed and variable attenuators. In the figure, 10 is an attenuator cell, 12 is a reference cell, and 2
0 is the first series FET, 30 and 32 are the first signal paths,
34 is the first parallel FET, 40 is the second series FET, 5
0, 52 is the second signal path, 54 is the second parallel FET,
60 is an operational amplifier, and 68 is a resistor.

Claims (1)

[Claims] 1. A first series FET whose source and drain serve as signal input and output terminals, respectively, and whose gate is supplied with an attenuation control signal, a first parallel FET whose source is connected to a reference potential source, and the first parallel FET whose source is connected to a reference potential source. a first signal path forming a characteristic impedance with respect to the reference potential source from the source and drain of one series FET through the first parallel FET, and attenuating the input signal by an attenuation amount according to the attenuation control signal; an attenuator cell, a first series FET whose gate is supplied with the attenuation control signal, a second parallel FET whose source is connected to the reference potential source, and a source and drain of the second series FET connected to the second parallel FET; a second signal path forming a characteristic impedance with respect to the reference potential source via the FET, and outputting a reference signal from the second series FET in accordance with the attenuation control signal; an operational amplifier in which the reference signal is supplied to a non-inverting input terminal, a constant voltage generated in a resistor of a predetermined impedance is supplied to an inverting input terminal, and an output signal is supplied to the gates of the first and second parallel FETs; The output signal of the operational amplifier controls the first parallel FET to make the voltage level of the reference signal equal to the constant voltage of the resistor, and the voltage level of the output terminal of the attenuator cell. The second parallel connection is made equal to the voltage level of the reference signal.
A variable attenuator characterized by controlling a FET.