JPH0571190B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a MIS transistor and a method for manufacturing the same. (Prior art) Miniaturization of MIS transistors, especially short channelization, is the most effective way to realize high-performance LIS. However, in a MIS transistor with a normal structure, the electric field _Ex along the channel is not constant within the channel, and is highest at the drain end and lowest at the source end. For example, the distribution of E _x at the time of pinch-off follows the following equation.

[C] Due to the operating principle of MIS transistors, the current is determined by E _x at the source end, so this uneven distribution of E _x is not desirable in order to obtain more current. do not have. Furthermore, the high electric field generated at the drain end increases the carrier energy more than necessary, leading to a decrease in long-term reliability due to the so-called hot carrier effect, such as fluctuations in threshold voltage and decrease in mutual conductance. In recent years, LDD has been used to suppress these problems, especially the hot carrier effect.
MIS transistors with modified drain structures, typically the (Lightly Doped Drsin) structure, have been proposed. Although these methods make it possible to weaken the electric field at the drain end, the effect is weak because only the impurity distribution is changed at the drain end. Therefore, _Ex in the channel near the source, which determines the current, does not become very high. Moreover, most of the drain voltage must be supported only in the low concentration region at the drain end, and as a result of the length of the low concentration region, parasitic resistance increases and no increase in current can be expected. (Problems to be Solved by the Invention) As described above, in the conventionally structured MIS transistor, the electric field concentrates at the drain end even in the on state, so the hot carrier effect is abnormally emphasized and the originally high electric field is There was a problem that the required source was not available. In addition, new structures such as LDDs provide some improvement in the hot carrier effect, but it is not necessarily sufficient. An object of the present invention is to make _Ex in the channel almost uniform under desired bias conditions, to suppress abnormal hot carrier effects, and to efficiently flow a large current under the bias conditions. The purpose of the present invention is to provide a MIS transistor and its manufacturing method. (Means for Solving the Problems) In the MIS transistor of the present invention, impurities, which become donors in the case of an n-channel and acceptors in the case of a p-channel, are introduced from the source side on the semiconductor surface where a channel between the source and drain is to be formed. It is characterized by being doped so that the concentration gradually increases toward the drain side. The manufacturing method of the present invention involves forming a gate insulating film and a gate electrode, and then using a focused ion beam method to introduce impurities into the source, drain, and channel while controlling the implantation energy and amount.
It is characterized in that it is carried out all at once.
This makes it easy to manufacture MIS transistors. (Operation) Next, the principle of the present invention will be explained. For convenience, an n-channel MIS transistor will be described here.
In an MIS transistor, the areal density n _S of carriers at the gate interface is qn _S = C _OX (V _G - V(x)) Q _B (x) + Q _D (x) (1). Here, C _OX is the gate capacitance, V _G is the gate voltage, V (x) is the channel electrification, Q _B (x) is the depletion layer charge due to acceptors under the channel, and Q _D
(x) is the areal density of donors doped on the surface.
As a first approximation, assuming that Q _B (x) does not depend on the channel potential, the surface potential measured from the substrate when the inversion layer is formed is considered to be approximately the same as the potential of the p-n junction, so Q _D ( Q _B can be considered to be constant regardless of x). On the other hand, if E _x in the channel is to be kept constant, n _S must be constant from the condition of continuous current. Therefore, if V(x)=Q _D /Lx, equation (1) becomes qn _S0 = C _OX (V _G -Q _D /Lx)Q _B0 +Q _D (x)...(2). In other words, the distribution along the channel of Q _D is
If it can be set according to equation (2), E _x in the channel can be made constant as shown in FIG. 2 at certain settings of V _D and V _G. At the source end, Q _D is used to prevent punch-through.
(0/) is preferably zero, so n _SO is
It is sufficient to set n _SO =C _OX /qV _G −Q _B0 . When V _G is zero, the inversion layer disappears near the source, so the off state can be set like a normal MIS transistor. (Example) Next, a typical example of the present invention will be described using a series of process diagrams shown in FIGS. 1a to 1c. In the following description, an n-channel MISFET is assumed for convenience of explanation, but a p-channel MISFET is also used in the same manner, except that the types of impurities handled are different, and this is naturally included in the present invention. Figure 1a shows a state where a gate oxide film 4 is grown to a thickness of 200 Å on a p-type Si substrate 1, and then phosphorus-doped polysilicon is grown to a thickness of about 2000 Å, and then a gate electrode 5 is formed by etching. . Figure 1b
Using a focused ion beam of _As , 5×10 ¹⁵ /cm ² of _As is implanted at 50 keV into the source/drain regions where no gate electrode exists, and the gate electrode is used for the channel area. 5
The figure shows where A _s was implanted with an acceleration energy of 500 keV through the wafer, controlling the beam current, that is, the implantation amount, according to equation (2) so that the concentration gradually increased from the source side to the drain side. Figure 1c shows an interlayer insulating film 7 made of SiO ₂ or the like with a thickness of approximately
After estimating the thickness of 5000 Å, contact holes were opened and metal wiring 8 was applied. FIG. 1c shows a typical embodiment of the structure of the present invention. (Effects of the Invention) Abnormality As explained above, in the MIS transistor of the present invention, the distribution of carriers along the channel becomes constant under a certain bias condition, that is, under a bias condition suitable for the circuit. Therefore, E _x is also constant and the most efficient carrier transport can be achieved. Therefore, the on-state current can be larger than that of an MIS transistor with a normal structure, and at the same time, no abnormal hot carrier occurs. On the other hand, if V _G is zero, the transistor is completely off, and if a drain voltage is applied, n
Since the type region (the region where As is implanted) is completely depleted, no abnormal high electric field region occurs even in the off state. Therefore, in many cases, if the A _s distribution in the channel is determined so that (2) holds at a specific bias point according to a specific operating mode,
While sufficiently suppressing the hot carrier effect,
It enables faster operation than MIS transistors. According to the manufacturing method of the present invention, since a focused ion beam is used, it is possible to easily form an optimal intra-channel _As distribution for each transistor.
In addition, since the positioning accuracy of the focused ion beam is high, if the edge of the gate electrode is detected in advance using a weak ion or electron beam, the overlap between the source/drain and gate can be avoided in a normal polysilicon gate MIS transistor. It can be shorter than that.

[Brief explanation of the drawing]

1A to 1C are cross-sectional views showing the order of steps for explaining the manufacturing method of the present invention, and FIG. 2 is an electric field distribution diagram for explaining the principle of the present invention. 1... p-type Si substrate, 2... source, 3... drain, 4... gate oxide film, 5... gate electrode,
6... A _s driven into the channel surface, 7...
Interlayer insulating film, 8...metal wiring.

Claims (1)

[Claims] 1. If the channel between the source and drain is to be formed on the semiconductor surface, if it is an n channel, a donor, a p
In the case of a channel, the impurity Q _D that becomes an acceptor is Q _D (x) = qn _S0 + Q _B0 −C _OX (V _G −V _D /LX) (Here, V _G and V _D are the gate voltage and drain voltage used, Q _B0 is the depletion layer charge under the channel, C _OX is the gate insulating film capacitance, L is the channel length,
x is the distance from the source end, and n _S0 is the carrier surface density at the source end for a given V _G . ) A MIS transistor characterized by being doped so that the concentration gradually increases from the source side to the drain side according to the formula described by 2. After forming a gate insulating film on the semiconductor region that is to become a channel, forming a gate electrode on it, and then using a focused ion beam method,
Impurities are introduced into the source, drain, and channel all at once while controlling the implantation energy and amount, and the semiconductor surface where the channel is to be formed is a donor for an n-channel and a donor for a p-channel. The impurity Q _D that becomes an acceptor is Q _D (x) = qn _S0 + Q _B0 −C _OX (V _G −V _D /LX) (Here, V _G and V _D are the gate voltage and drain voltage used, and Q _B0 is the channel Lower depletion layer charge, C _OX is gate insulating film capacitance, L is channel length,
x is the distance from the source end, and n _S0 is the carrier surface density at the source end for a given V _G . ) A method for manufacturing an MIS transistor, characterized in that doping is performed so that the concentration gradually increases from the source side to the drain side according to the formula described in .