JPH0571115B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an image memory suitable for image signal processing.

[Background of the invention]

As a conventional example of image memory used in image signal processing for TVs and VTRs, for example, "Field memory for TVs and VTRs" by Hara Nagami in Nikkei Electronics, February 11, 1985, No. 362.
There is a document entitled ``A serial input/output type dynamic memory dedicated to images with a 320 row x 700 column configuration''.

FIG. 3 shows a block diagram of an example of an image-only dynamic memory of the field memory discussed in this document. In this image memory, a data register 117 with a capacity for one line (one line is one horizontal scanning line) is provided, and an input terminal 101 is provided here.
Continuous serial data is inputted for one line at high speed, and outputted to the output terminal 102 at high speed. In this case, 120 is a data buffer,
Data input/output is controlled by a serial control signal from terminal 110 and a write enable signal from terminal 109. 118 is a select circuit which connects data register 1 to data buffer 120 by a serial control signal shifted by shift register circuit 119;
17 addresses are defined. This one line data register 117 and field memory cell 1
Transfer between 15 and 15 is performed through gate circuit 116 and is controlled by a row address strobe signal from terminal 108 and a write enable signal from terminal 109. By doing this,
It is possible to reduce the transfer speed between the data register 117 and the field memory cell array 115, and it is possible to increase the speed of inputting and outputting serial data to the image memory without increasing the operation speed of the field memory cell array 115.

In addition, in one embodiment of FIG. 3, the terminal 103
Refresh address counter 111 controlled by a refresh control signal from
INC, downclock signal, reset signal
Row address counter 112 controlled by RCR
The field memory cell 115 is automatically refreshed and row addressed through a multiplexer 113 and a decoder 114, and is designed to be conveniently used as an image memory.

However, the memory actually used for image processing is one memory rather than one field unit.
It is often used in frame units such as a frame or two frames, and the conventional example described above uses a large number of memory ICs and requires complex external control signals.

[Purpose of the invention]

The purpose of the present invention is to solve the problems of the conventional example described above.
It is an object of the present invention to provide an image memory that has a capacity in frame units of one frame or two frames and is convenient for use as a memory for image signal processing.

[Summary of the invention]

In order to achieve the above object, in the present invention, the capacity of the image memory is set in frame units of 1 frame or 2 frames, and for example, in the case of 1 frame, 1 field delay output is output, and in the case of 2 frames, 1 field or 1 frame is output. An intermediate tap such as a frame delay output is provided, and an address control circuit is provided in the image memory that can arbitrarily set the read address and write address positions of the memory cell by external synchronization, for example.

[Embodiments of the invention]

FIG. 1 shows an embodiment of an image memory using the present invention. In this embodiment, the capacity of the image memory is 1
The explanation will be made assuming that the frame is a frame and a one-field delayed output signal is derived as an intermediate tap output.

In Figure 1, 1 is an input terminal for n-bit image digital data, 2 is an output terminal for image data delayed by 1 field, 3 is an output terminal for image data delayed by 1 frame, and 4 is an input terminal for, for example, vertical synchronization VD. , 5 is an input terminal for horizontal synchronization HD, for example.
6 is an input terminal for a clock signal whose phase is synchronized with the data sampling clock, 7 is a frame memory cell, 15 to 17 are data buffers, 9 to 11 are data registers, and 12 to 14 are addresses of each data register 9 to 11. Each data buffer 15
8 is a select circuit that determines whether to transfer data between data registers 9 to 11 and which column address of frame memory cell 7, and 18 is a frame memory cell. 7 row address, block unit column address of select circuit 8, and select circuit 12~
This is a timing and address control circuit that generates column addresses for each of the 14 dots. The circuit operation will be briefly explained below.

The n-bit serial image digital data from input terminal 1 is transferred to data buffer 15 and select circuit 1.
2 and is led to the data register 9 at one end. A control signal specifying which address in the data register 9 is to be transferred is obtained by decoding the output of the dot counter 27 in the timing & address generation circuit 18 using the decoding circuit 28. If this data register 9 is filled with, for example, N dots, the data of N dots is treated as one block, and the data is transferred to the frame memory cell 7 in units of blocks through the select circuit 8. The control signal that specifies to which column address of the frame memory cell this block unit data is transferred is N.
It is obtained by decoding the output of a block counter 25, which counts dots as one block, in a decoding circuit 26. When this column address becomes full with, for example, M blocks, the row address is changed. The control signal that specifies this row address is M
It is obtained by decoding the output of the write address counter 22, which counts blocks as one column, through the multiplexer 23 and the decoding circuit 24. The data written in frame memory cell 7 as described above is transferred to data registers 10 and 11 in blocks through select circuit 8. The control signal that specifies which row of data in the frame memory cell 7 is to be transferred is a signal obtained by decoding the output of the read address counter 21 and a circuit 20 that provides an offset of one field to the output of the read address counter 21. Give the decoded output of . That is, the row address signal of the data transferred to the data register 10 is given by the output of the field offset address circuit 20, and the row address of the data transferred to the data register 11 is given by the output of the read address counter 21. Further, a control signal specifying which column of data in the frame memory cell 7 is to be transferred is given by the block counter 25 in the same manner as in writing. The data in blocks that are delayed by one field relative to the input data to the data register 10 and the data in blocks that are delayed by one frame to the data register 11 are transferred through select circuits 13 and 14. , are converted into serial data in the opposite manner to the writing, and are guided to data buffers 16 and 17, respectively, and output from terminals 2 and 3.

As described above, the feature of the embodiment of the present invention shown in FIG. 1 is that data is transferred between the data register 9 for writing and the frame memory cell 7 and between the data registers 10 and 11 for reading and the frame memory cell 7 in block units. At the same time, during this one block period, reading from frame memory cell 7 is performed twice with different row addresses, data is transferred from data registers 10 and 11, and data is transferred from write data register 9 to frame memory cell 7. It must be done once. In this way, when data is written to the frame memory cell 7 once, the data is read twice with the row address different by one field, thereby outputting data delayed by one frame and data delayed by one field. can be easily obtained as.

In the above embodiment of the present invention shown in FIG. 1, for example, how to perform refresh, how to correct the time delay in block units due to data registers 9 to 11, etc. can be obtained by reading twice during one block period. 1 field delayed data and 1
There are problems such as what to do with the time difference in dot units with frame-delayed data.

First, as a refresh method, a refresh address 19 is provided in the timing and address generation circuit 18, and refresh is applied in the column direction every block period, for example, so that refresh can be performed automatically. The time delay in blocks caused by the data registers 9 to 11 can be solved by, for example, providing two block counters 25, one for reading and one for writing.
This can be handled by changing the transfer address between 11 and 11. 1 field delayed data and 1
For example, when the data delayed by one field is read out from the frame memory cell 7 first, the time difference in dot units with the frame-delayed data is 1
Since frame-delayed data lags behind one-field-delayed data, this can be handled by providing a delay circuit (for example, a shift register) on the data side that is one-field-delayed by the amount of delay. Also,
For example, a shift register is provided between the data registers 10, 11 and the select circuits 13, 14, and from the shift registers 10, 11, data buffers 16,
This can be handled by changing the selection timing to 17 between the output side delayed by one field and the output side delayed by one frame.

FIG. 2 shows an embodiment of the present invention including the countermeasure circuit described above. In this embodiment, the specific size of the frame memory cell 7 will be explained as 910 columns x 525 rows.

In NTSC, if the clock frequency is set to 4sc (sc is the chroma subcarrier frequency), one line will be 910 dots. Also, one frame has 525 lines. In this case, for example, the dot counter 40
The count number of block counter 37 is selected to be 35 dots, the unit of one block of data transfer between data registers 9 to 11 and frame memory cell 7 is set to 35 dots, the count number of block counter 37 is selected to be 26 blocks, and the count number of frame memory cell 7 is selected to be 35 dots. Assuming that the number of dots in one row is 35 dots x 26 blocks = 910 dots, each row of frame memory cells 7 corresponds to just one line, and there is an advantage that row addresses can be specified in line units. .

In FIG. 2, 29 and 30 are shift register circuits, and the select circuit 12 when writing data.
The select positions of the select circuits 13 and 14 at the time of reading are made different, for example, the select circuit 12
is a control signal obtained by decoding the output of the dot counter 40, and the select circuit 13
The select circuit 14 similarly outputs the L ₂ dot data 41 using a control signal obtained by decoding the output with an offset of L ₁ dot obtained by mixing the output of the L 1 dot data 38 with the output of the L ₁ dot data 38 in the subtracter 39. By selecting the output with an offset of _L2 dots obtained by the subtracter 42 using the decoded control signal, the timing of the output delayed by one field and the output delayed by one frame can be matched in dot units. . 35 is K block data, and by mixing it with the output of the block counter 37 in the subtracter 36, an output having an offset of K blocks with respect to the output of the block counter 37 is obtained. These outputs are selected by the multiplexer 43 at the time of writing and reading,
By using the decoded output as a control signal for the select circuit 8, it is possible to switch the column address of the transfer data during writing and reading, and it is possible to correct the time delay error in blocks caused by the data registers 9 to 11. can. 31 is
This is 262 line data, and by mixing it with the read address counter output that counts 525 lines in the subtracter 32, an output with an offset of 262 lines corresponding to one field from the 525 lines is obtained, and this output is decoded. By using this control signal as a row address, it is possible to switch between the row address of data delayed by one field and the row address of data delayed by one frame.

The above is an example in which a one-frame memory cell is used as the memory cell 7, and data delayed by one field is output as an intermediate tap output.
However, the present invention is not limited to the case where the memory cell 7 is a one frame memory cell, but may be a two frame memory cell or a three frame memory cell, for example. Also, as an intermediate tap output, for example 2
In the case of a frame memory cell, data delayed by one field, data delayed by one frame, or data delayed by three fields may be used, and intermediate tap outputs may be provided for multiple data.

In addition, in the explanation of one embodiment in FIG. 2, in the case of the NTSC system, the clock is 4sc, and one block is 35
Although the cell size is 525 lines x 910 dots, the present invention is not limited to these television systems or clock frequencies; for example, the PAL system may be used. Also, the clock frequency may be 3sc. Further, one block unit may be 26 dots, 52 dots, 64 dots, etc. as desired.

Next, as an embodiment of the present invention in which m memory cells of about 1 field are provided as n memory cells,
An example will be explained in which two fields each having approximately one field are provided.

FIG. 4 shows an embodiment of this invention. This embodiment differs from the embodiments in FIGS. 1 and 2 in that it has two field memory cells 49, 50;
Can be used as field memory by connecting in parallel, and can be used as frame memory by connecting in serial.

In FIG. 4, 44 and 45 are input terminals for n-bit image digital data, 46 and 47 are output terminals, 48 is an input terminal for a control signal that switches the input data of the select circuit 65, and 53 to 56 are data registers; 51 and 52 are select circuits that designate data transfer between each field memory cell 49 and 50 and data registers 53 to 56 in block units; 61 to 64 are data buffers; 57 to 60
The select circuit for specifying data transfer between each data register 53-56 and data buffer 61-64 in units of dots and other features are the same as in the embodiment shown in FIG.

The feature of this embodiment is that it has two data input terminals 44 and 45 and a select circuit 65. When used in the field memory cell mode, the select circuit 65 selects data from the input terminal 45 through a data buffer 62. , to the select circuit 58, each input terminal 44, 45, field memory cell 49, 50, and output terminal 46, 4
7 are connected in parallel, and data delayed by one field from input terminals 44 and 45 is led to output terminals 46 and 47, respectively. When used in the frame memory mode, the select circuit 65 selects the data delayed by one field from the data buffer 63 and leads it to the select circuit 58, so that the input terminal 44, the field memory cell 49, the input terminal 46, and the field memory Cell 50, output terminal 47
is connected serially. As a result, data delayed by one field is introduced to the output terminal 46, and data delayed by one frame is introduced to the output terminal 47.

In this way, by providing a plurality of memory cells for approximately one field and providing a select circuit that switches the input/output of each field memory cell, it is possible to easily switch the image memory between the field memory mode and frame memory mode using an external signal. can. Furthermore, when used in frame memory mode, unlike the embodiment of FIG. 1, it is possible to easily obtain a signal with no delay error between field-delayed data and frame-delayed data.

FIG. 5 shows an example of the timing and address control circuit 18 used in the embodiment of the present invention shown in FIG. Here, similar to the embodiment in FIG. 2, NTSC
Now, a case where one row of field memory cells 49 and 50 corresponds to one line will be explained.

In Figure 5, 66 is a refresh address, 67 and 68 are 262 lines and 263 lines for each field.
This is an address counter whose count number changes depending on the line; when one counts 262 lines, the other counts 263 lines, and the counter is reset by vertical synchronization VD from terminal 4. 69 is a block counter, horizontal synchronization from terminal 5
The counter is reset in HD and counter 6
The output of address counter 9 is led as a clock for address counters 67 and 68. A dot counter 70 counts, for example, N dots using the clock CK from the terminal 5, and its output is clocked by a block counter 69 and led thereto. Decode circuits 71 to 75 decode the respective counter outputs, the output of the decode circuit 74 is led as a control signal for selection of the select circuits 51 and 52, and the output of the decode circuit 75 is used for selection of the select circuits 57 to 60. Derived as a control signal. 76 and 77 are multiplexers, which connect refresh counters 66 and 2.
The signals obtained by decoding the outputs of two address counters 67 and 68 are switched and guided as refresh and address signals for field memory cells 49 and 50, respectively. 78 is a multiplexer switching signal generator, for example, the field memory cell 4
9 and 50 are connected in parallel and used in field memory mode, the same signal is output as the output of the two multiplexers 76 and 78. When connected serially and used in frame memory mode, the address signals derived from the two address counters 67 and 68 output signals that are opposite to each other. A determination signal is sent from the terminal 48 to the switching signal generator 78 to determine whether to use the field memory mode or the frame memory mode.
The signals guided to the two multiplexers 76 and 78 can be easily switched between being the same or having opposite sources. The terminal 79 is an input terminal for a control signal for switching, for example, whether the field memory amount is 262 lines or 263 lines when used in the field memory mode. for example
In the case of 262 lines, the read address counter for odd fields is set to 262 lines, the write address counter is set to 263 lines, and vice versa for even fields. If it is 263 lines,
The opposite is true for 262 lines. This also makes it possible to switch the field memory output to 262 lines or 263 lines, for example, when used in frame memory mode.

Although FIG. 5 has been described in the case of the NTSC system, the present invention is not limited to the television system. For example, in the PAL system, the delay amount in the field memory mode can be switched between 312 lines and 313 lines. In addition, in the case of the two-frame configuration of the NTSC system, both the two address counters 67 and 68 are
525 line counter, and the same one can be used.

FIG. 6 shows an embodiment in which a masking function is added to the embodiment of the present invention shown in FIG.

In FIG. 6, 80 and 81 are input terminals for masking control signals, and 82 to 85 are shift registers. In the embodiment shown in FIG. 4, a select circuit is used to select the address to the data register. Serial data is converted into block-by-block parallel data or parallel data is converted into serial data, but in this embodiment, shift registers 82 to 85 are used to directly input serial data to shift registers 85 and 86. Data registers 53 and 54 in parallel in blocks
As an example, serial data is converted to parallel data by leading to , and parallel data is similarly converted to serial data. 85-8
Reference numeral 8 denotes a select circuit, which converts data guided to input terminals 44, 45 and output terminals 46, 47 to control signals from terminals 80, 81, respectively, to a decoding circuit 8.
Switching is performed using signals a, b, c, d, and e decoded at 9.

FIG. 7 shows a specific example of the decoding circuit 89 shown in FIG. 6. Further, FIG. 8 shows a select circuit 8 controlled by the decoding circuit 89 shown in FIG.
5 to 88 and which data is guided to the two field memory cells 49 and 50 by the timing and address control circuit 18.

In FIG. 7, 90 is an exclusive NOR circuit,
Assuming that the control signals shown in FIG. 8 (“H” indicates High and “L” indicates Low) are input from the two terminals 80 and 81, the output signal a of the decoding circuit 89
~e is as shown in the figure. Also, in Figure 6,
When the select signals b to e from the decode circuit 89 are "H", the select circuits 85 to 88 select the left input signal, and the signal a from the decode circuit 89 to the timing & address control circuit 18 is "H". When the signal is "L", the field memory mode is set, and when the signal is "L", the frame memory mode is set, then the data shown in FIG. 8 is guided to each field memory cell 49, 50, respectively. That is,
When both terminals 80 and 81 are "H", field memory mode is entered, and field memory cell 4
Current field data from input terminals 44 and 45 are led to input terminals 9 and 50. Furthermore, when the terminals 80 and 81 are both "L", the frame memory mode is set, and the field memory cell 49 has the input terminal 44.
The current field data from the field memory cell 50 is guided to the field memory cell 50, and the previous field data from the output terminal 46 is introduced to the field memory cell 50. This is the same as the embodiment shown in FIG. Next, when the terminal 80 is "L" and the terminal 81 is "H", it becomes field memory mode.
And the field-by-field masking function works,
Data delayed by one field from output terminals 46 and 47 is led to field memory cells 49 and 50, respectively. When the terminal 80 is "H" and the terminal 81 is "L", the frame memory mode is set, and the masking function is operated in units of frames, and the field memory cell 49 receives one signal from the output terminal 47.
Data delayed by one field from the output terminal 46 is guided to the field memory cell 50 .

As described above, by using the embodiment shown in FIG. 6, a masking function can be easily added from the outside, and the field memory mode and frame memory mode can be easily used.

As described above, in the embodiment of the present invention shown in FIG. Although a shift register is used in the embodiment shown in the figure, the present invention is characterized in that it includes such a conversion means, but the specific method of the means may be a select circuit, a serial circuit, or any other method. good.

In addition, in the embodiment shown in FIGS. 4 and 6, data delayed by one frame and data delayed by one field are output in parallel. The data delayed by two frames and the data delayed by two frames may be output in parallel. Although not shown, similarly,
Data delayed by 1 field, data delayed by 1 frame, data delayed by 3 fields, and data delayed by 2 frames may be simultaneously output in parallel. It is also possible to provide a select circuit on the output side and arbitrarily switch and output data delayed in units of these fields using an external signal.

〔Effect of the invention〕

By using the present invention, it is possible to realize an image memory that is capable of high-speed serial input/output and that can simultaneously obtain, for example, data delayed by one frame and data delayed by one field just by inputting a clock signal and a synchronization signal. This has the effect of simplifying the digital processing of image signals from TVs, VTRs, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image memory showing one embodiment of the present invention, FIG. 2 is a block diagram of an image memory showing another embodiment of the invention, and FIG. 3 is an embodiment of a conventional image memory. FIG. 4 is a block diagram of an image memory showing another embodiment of the present invention, and FIG. 5 is an example of the timing and address control circuit 18 used in the embodiment of the present invention shown in FIG. FIG. 6 is a block diagram of an image memory showing another embodiment of the present invention, and FIG. 7 is a decoding circuit 8 used in the embodiment of the present invention shown in FIG.
FIG. 8 is a circuit diagram showing an example of the decoding circuit 89 shown in FIG. 7, and is a diagram illustrating the operation of the embodiment of the present invention shown in FIG. 6 when the decoding circuit 89 shown in FIG. 7 is used. Explanation of symbols: 1, 44, 45, 101...Image data input terminals, 2, 3, 46, 47, 102...
Image data output terminal, 4... Vertical synchronization VD input terminal, 5... Horizontal synchronization HD input terminal, 6... Clock signal input terminal, 7... Frame memory cell array, 8, 51, 52... Between memory cell and data register. Select circuits for transferring 9 to 11, 5
3-56...Data register, 12-14, 57-
60, 118... Select circuit for transferring between data buffer and data register or shift register, 15-17, 61-64, 120... Data buffer, 18... Timing & address control circuit, 19, 66, 111... Refresh address counter, 20...Field offset address circuit, 21, 33...Read address counter, 2
2, 34...Write address counter, 23, 4
3, 76, 77, 113...Multiplexer, 2
4, 26, 28, 71 to 75, 89, 114...decode circuit, 25, 37, 69...block counter, 27, 40, 70...dot counter, 29,
30,82-85,119...Shift register, 3
1...262H data, 32,36,39,42...Subtractor, 35...K block data, 38,41...Dot data, 48,79-81,103-10
6,108-110...Control signal input terminal, 4
9, 50, 115... Field memory cell array, 65, 85-88... Selection circuit for switching input/output signals, 67, 68, 112... Address counter, 78... Switching signal generator for multiplexers 76, 77, 116... Field memory cell A gate circuit that transfers data between the
107...Synchronization output terminal.

Claims (1)

[Claims] 1 Equipped with n memory cell arrays (n is an integer) having a memory capacity of m times the memory capacity of approximately 1 field (m is an integer) or m×n memory cell arrays each having a memory capacity of approximately 1 field, n×k (k is an integer) data registers,
means for transferring data between the memory cell array and the data register in parallel in block units; means for inputting serial data from n input terminals to at least n data registers among the data registers; means for outputting serial data from 2n data registers to at least 2n output terminals, a signal for controlling at least a row address of the memory cell array, a means for transferring data between the memory cell array and the data register, and the data; It is equipped with a circuit that generates a signal for controlling data transfer between a register and an input/output terminal, uses at least a clock signal and a synchronization signal of an image signal or a signal equivalent to a synchronization signal as input signals of the circuit, and uses the 2n Among the output terminals, data delayed by about m fields is led to n output terminals, and data delayed by about m fields is sent to the other n output terminals (m-
1) An image memory characterized in that data that is less than a field and delayed by an integral multiple of about a field unit is simultaneously led.