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JPH0567008U - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0567008U
JPH0567008U JP601792U JP601792U JPH0567008U JP H0567008 U JPH0567008 U JP H0567008U JP 601792 U JP601792 U JP 601792U JP 601792 U JP601792 U JP 601792U JP H0567008 U JPH0567008 U JP H0567008U
Authority
JP
Japan
Prior art keywords
lead
semiconductor device
package
solder
shape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP601792U
Other languages
Japanese (ja)
Inventor
正博 平岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP601792U priority Critical patent/JPH0567008U/en
Publication of JPH0567008U publication Critical patent/JPH0567008U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】 本考案は、目視および光学系による半田付け
特性の確認が容易で、信頼性の高い実装を行うことので
きる半導体装置を提供することを目的とする。 【構成】 本考案では、パッケージから導出される部分
のリード形状を逆J字型にした構造としている。
(57) [Summary] [Object] An object of the present invention is to provide a semiconductor device in which soldering characteristics can be easily checked visually and by an optical system and which can be mounted with high reliability. [Structure] In the present invention, the lead shape of the portion led out from the package has an inverted J shape.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、半導体装置にかかり、特にそのリード形状に関する。 The present invention relates to a semiconductor device, and more particularly to a lead shape thereof.

【0002】[0002]

【従来の技術】[Prior Art]

近年、半導体集積回路の高密度実装における軽薄短小高機能化の傾向は高まる 一方である。そこで半導体装置の実装構造においても、半導体基板表面にリード を面接触させて接続するいわゆる表面実装構造をとるものが多くなってきている 。このような表面実装構造の半導体装置のリード形状としては、ガルウィング型 と呼ばれるL字形状のもの、ストレート型のもの、J字型のものが広く用いられ てきている。 In recent years, the trend toward light, thin, short, small, and high functionality in high-density packaging of semiconductor integrated circuits has been increasing. Therefore, even in the mounting structure of the semiconductor device, the so-called surface mounting structure in which the leads are brought into surface contact with the surface of the semiconductor substrate to be connected is increasing in number. As the lead shape of the semiconductor device having such a surface mounting structure, an L-shaped shape called a gull-wing type, a straight type, and a J-shaped type have been widely used.

【0003】 このような半導体装置をプリント基板1表面に実装する場合、図2(a) および (b) に示すようにプリント基板1に形成された配線パターン3上にリード4を半 田5を介して固着する方法がとられるが、パッケージ2の外方向のリード表面に は、半田5の量が少なく、目視および光学系による半田付け性の確認が困難であ る。 そこで半田量を多くすることも考えられるが、リード肩部のウィッキング現象 により、パッケージの信頼性低下等の問題が生じる。 このため、半田量の増大は難しく、目視および光学系による半田付け性の確認 には、検査作業時間の増加および品質の低下等の問題があった。When mounting such a semiconductor device on the surface of the printed board 1, as shown in FIGS. 2A and 2B, the leads 4 and the solder 5 are formed on the wiring pattern 3 formed on the printed board 1. However, the amount of the solder 5 is small on the outer lead surface of the package 2, and it is difficult to visually confirm the solderability by an optical system. Therefore, it is conceivable to increase the amount of solder, but the wicking phenomenon of the lead shoulder causes a problem such as deterioration of package reliability. For this reason, it is difficult to increase the amount of solder, and there are problems such as an increase in inspection work time and a deterioration in quality when visually confirming solderability by an optical system.

【0004】[0004]

【考案が解決しようとする課題】[Problems to be solved by the device]

このように、従来の実装方法では、確実に固着するのが困難であり、半田目視 および光学系による半田付け性の確認には、検査作業時間の増加および品質の低 下等の問題があった。 As described above, in the conventional mounting method, it is difficult to firmly fix the solder, and there are problems such as an increase in inspection work time and deterioration of quality in visually checking the solder and checking the solderability by the optical system. .

【0005】 本考案は、前記実情に鑑みてなされたもので、目視および光学系による半田付 け特性の確認が容易で、信頼性の高い実装を行うことのできる半導体装置を提供 することを目的とする。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device in which soldering characteristics can be easily checked visually and by an optical system, and highly reliable mounting can be performed. And

【0006】[0006]

【課題を解決するための手段】[Means for Solving the Problems]

そこで本考案では、パッケージから導出される部分のリード形状を逆J字型に した構造としている。 Therefore, in the present invention, the lead shape of the portion led out from the package has an inverted J-shaped structure.

【0007】[0007]

【作用】[Action]

上記方法によれば、パッケージから導出される部分のリード形状を逆J字型に した構造としているため、パッケージ外方向のリード表面の半田量を増大させて もリード肩部へのウィッキング現象は問題にならず、パッケージ外方向のリード 表面の半田量を増大することができ、信頼性の向上をはかるとともに目視および 光学系による半田付け性の確認が容易となる。 このようにして、検査作業時間の短縮および品質の安定化をはかることができ る。 According to the above method, since the lead shape of the part led out from the package has an inverted J-shape, even if the amount of solder on the lead surface in the package outer direction is increased, the wicking phenomenon on the lead shoulder does not occur. There is no problem and the amount of solder on the lead surface in the package outer direction can be increased, which improves reliability and facilitates visual inspection and solderability confirmation with an optical system. In this way, inspection work time can be shortened and quality can be stabilized.

【0008】[0008]

【実施例】【Example】

次に、本考案の実施例について、図面を参照しつつ詳細に説明する。 図1は、本考案実施例の半導体装置を示す図である。 図1に示すように、この半導体装置はリード4をパッケージ2の外側領域部分 で逆J字型に成形したことを特徴とするものである。 Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, this semiconductor device is characterized in that the leads 4 are formed in an inverted J shape in the outer region portion of the package 2.

【0009】 プリント基板1は、積層基板上に銅箔を貼着しこれをパターニングして配線パ ターン3を形成したもので、このプリント基板1上に半導体装置のパッケージ2 を搭載し、配線パターン3の上に逆J字型のリード4を載置し、半田5を介して 固着することによって実装がなされる。The printed circuit board 1 is formed by adhering a copper foil on a laminated board and patterning the copper foil to form a wiring pattern 3. A semiconductor device package 2 is mounted on the printed circuit board 1 and a wiring pattern is formed. Mounting is carried out by placing an inverted J-shaped lead 4 on top of 3 and fixing them via solder 5.

【0010】 かかる構造によれば、パッケージ外方向のリード表面には半田5が十分に付着 せしめられ、半田量を増大させても、リードの外側からJ字の凹部に半田が流れ 込み、信頼性よく固着せしめられる。従って、半田量を増大させても、リードか らのウィッキング現象によるパッケージの信頼性低下等の問題はなくパッケージ 外方向のリード表面には半田フィレットが容易に目視できるように形成される。 また、検査工程においても、検査作業時間の短縮および品質の向上をはかるこ とができる。 なお、リードの形状はほぼ逆J字型をなすように形成すればよく、適宜変形可 能である。According to this structure, the solder 5 is sufficiently adhered to the lead surface in the package outer direction, and even if the amount of solder is increased, the solder flows into the J-shaped recess from the outside of the lead, and the reliability is improved. Can be firmly fixed. Therefore, even if the amount of solder is increased, the reliability of the package is not deteriorated due to the wicking phenomenon from the lead, and the solder fillet is formed on the lead surface in the package outer direction so as to be easily visible. Also, in the inspection process, the inspection work time can be shortened and the quality can be improved. The lead may be formed so as to have a substantially inverted J shape, and can be appropriately modified.

【0011】 また前記実施例ではプリント基板として積層基板を用いたが、ガラス基板やセ ラミック基板、樹脂基板等を用いてもよく、さらに配線パターンについても銅箔 に限定されることなく適宜変更可能である。Further, in the above-mentioned embodiment, the laminated substrate is used as the printed circuit board, but a glass substrate, a ceramic substrate, a resin substrate or the like may be used, and the wiring pattern is not limited to the copper foil and can be changed appropriately. Is.

【0012】[0012]

【考案の効果】[Effect of the device]

以上説明したように、本考案では、パッケージから導出される部分のリード形 状を逆J字型にした構造としているため、半田固着性についての検査作業時間の 短縮および品質の安定化をはかることができる。 As described above, in the present invention, since the lead shape of the part led out from the package is an inverted J-shape, it is possible to reduce the inspection work time for solder sticking property and stabilize the quality. You can

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案実施例の半導体装置のプリント基板への
実装例を示す図
FIG. 1 is a diagram showing an example of mounting a semiconductor device according to an embodiment of the present invention on a printed circuit board.

【図2】従来例の半導体装置のプリント基板への実装例
を示す図
FIG. 2 is a diagram showing an example of mounting a conventional semiconductor device on a printed circuit board.

【符号の説明】[Explanation of symbols]

1 プリント基板 2 パッケージ 3 配線パターン 4 リード 5 半田 1 Printed circuit board 2 Package 3 Wiring pattern 4 Lead 5 Solder

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 複数のリードを有するリードフレームと
前記リードフレームに搭載されかつ前記複数のリードの
少なくとも1つに電気的に接続された半導体チップと前
記半導体チップと前記リードの一部とを覆う樹脂パッケ
ージとを具備した半導体装置において前記リードが前記
パッケージの外で逆J字型をなすように構成されたこと
を特徴とする半導体装置。
1. A lead frame having a plurality of leads, a semiconductor chip mounted on the lead frame and electrically connected to at least one of the plurality of leads, the semiconductor chip and a part of the lead are covered. A semiconductor device comprising a resin package, wherein the lead is formed in an inverted J shape outside the package.
JP601792U 1992-02-17 1992-02-17 Semiconductor device Pending JPH0567008U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP601792U JPH0567008U (en) 1992-02-17 1992-02-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP601792U JPH0567008U (en) 1992-02-17 1992-02-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0567008U true JPH0567008U (en) 1993-09-03

Family

ID=11626932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP601792U Pending JPH0567008U (en) 1992-02-17 1992-02-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0567008U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015022745A1 (en) * 2013-08-15 2015-02-19 松尾電機株式会社 Chip-type fuse

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015022745A1 (en) * 2013-08-15 2015-02-19 松尾電機株式会社 Chip-type fuse

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