JPH0566994A - Multiprocessor system - Google Patents

Abstract

(57) [Abstract] [Purpose] To construct a high-performance multiprocessor system that can be used for high-speed 3D image processing. [Structure] A plurality of processor modules, a system bus connecting them, and a bus arbiter for controlling the right to use the bus. A memory having a required internal structure is arranged in each processor module, and a processor address decoder receives an address from the processor and a memory access request signal, and a system bus address decoder receives an address from the system bus and an address switch. A memory access request signal is output to the memory arbiter when it matches the area specified by. The memory arbiter receives these signals and performs arbitration.
One of the two bus buffers is exclusively controlled and opened to access the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system suitable for processing a large amount of data such as a three-dimensional image at high speed.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration example of a conventional multiprocessor system. The multiprocessor system includes a plurality of processor modules 101, a large-capacity data memory 102, and a system bus 103 for data transmission.
And the system bus 103 to each processor module 10
Bus arbiter 1 that controls the usage status when 1 uses
04. Further, each processor module 101 includes a processor 105, a local memory 106, and a system bus control circuit 107. Here, the local memory 106 has a configuration that can be accessed only by the processor 105 and cannot be accessed by processors of other processor modules. In this technical sense, the memory 106 is called "local memory". When handling a large amount of data, the system bus 10
3, data is partially transferred from the large-capacity data memory 102 to the local memory 106, processing is performed, the result is transferred via the system bus 102, and the data is again written to the data memory 102. When a plurality of processor modules 101 are used and a multiprocessor configuration is adopted, each processor module 101 performs the same processing, so that the processing speed of the entire system can be improved.

[0003]

However, in the conventional multiprocessor system composed of a plurality of processor modules 101, as the number of processor modules 101 increases, the data traffic on the system bus 103 increases, which becomes a bottleneck. The improvement of will reach the ceiling. Particularly in image processing, since data access frequently occurs, data traffic on the system bus 103 often becomes a bottleneck. For example, when calculating 256 ³ image data with 16 unit processor modules, each processor module has 256 × 25
The 6 × 16 data area is mainly operated, but all the data in the data memory 102 is temporarily moved to the local memory 102 for the operation, or the operation is performed while directly accessing the data memory 102. In either case, when the 16 units of the processor module 101 concentrate access to the data memory 102 and the processing performance of the processor module 101 is sufficiently fast, the data transfer on the system bus 103 occupies most of the processing time. Become.

An object of the present invention is to provide a high-performance multiprocessor system constructed so as to solve the above-mentioned bus neck problem and to fully utilize the high-speed processing performance of each processor module.

[0005]

A multiprocessor system according to the present invention is configured as follows to achieve the above object. 1. A multiprocessor system including a plurality of processor modules having a processor and a system bus control circuit for accessing an external memory connected to the system bus through the system bus, wherein each of the plurality of processor modules comprises: Providing an internal memory accessible from the internal processor,
This internal memory and the processor are connected via a bus buffer, the internal memory and the system bus are connected via another bus buffer, and access requests from the processor side and the system bus side are detected, A memory arbiter that exclusively controls the two bus buffers to establish a connection is provided.
The internal memory can be accessed from the system bus side. That is, a large-capacity data memory is divided, the divided memories are mounted in each processor module, and each processor competes with other processors on the system bus for the memory in the processor module. To be able to access without. This allows
Similar to the above example, when calculating 256 ³ image data with 16 unit processor modules, each processor module mainly calculates a 256 × 256 × 16 data area, so this data area is stored in each processor module. If it is allocated to the memory at, most of the data access can be performed in each processor module in the closed state, and the bus neck can be eliminated. However, for some data access to the data located in the boundary area between each memory, the memory of another process module may be accessed via the system bus, but the problem of the bus neck does not occur at all. .. 2. In the first configuration, preferably, an address changing unit that changes an address location of the internal memory when accessing from the system bus side is provided, and a plurality of processor modules of the same type are mounted while shifting the address locations. , Construct a structure in which these internal memories can be regarded as one memory having a continuous address space through the system bus. The address changing means is composed of a module number included in the address information (bit information) output from the processor, an address switching means as a reference, and a comparing means for comparing the data of both. In this case, the module number is preferably placed at the front of the internal memory address as a bit position on the address information. 3. In the second configuration, more preferably, the internal memory is divided into a plurality of smaller areas, and the address changing means is individually provided in each of the plurality of areas, and each area has a separate address location. In addition, the entire system is configured to form a large continuous area without overlapping. In this case, the address changing means
The module number is located in the internal memory address in the address information. 4. In the second or third configuration, preferably, the internal memory has two address locations as seen from the processor, and when accessing at one address location, an internal fixed address irrelevant to the address changing means is provided. When accessed at the other address location, the address space of the continuous area is configured to be the space designated by the address changing means. 5. In the second or third configuration, preferably, when the processor accesses a memory on a continuous address space extending over a plurality of processor modules, the setting of the address changing unit is determined, and the memory in its own processor module is determined. When you decide to access the location. It is configured not to be accessed via the system bus control circuit but to be accessed through a bus buffer between the internal memory and the processor. 6. In the third configuration, preferably, the address changing means is changed by software. Specifically, the bit number of the module number in the address information can be changed by software.

[0006]

In the multiprocessor system according to the present invention,
The internal memory is arranged in the processor module, and the internal memory and the processor and the internal memory and the system bus are connected by separate bus buffers, and the memory arbiter is arranged from the processor side or the system bus side. When the access request is detected and the two bus buffers are exclusively controlled and opened, the internal memory can be accessed from both the processor side and the system bus side. Internal memory contention occurs only when a processor is accessing the internal memory and at the same time there is a memory access from another external processor through the system bus, but most data access is within each processor module. Since it occurs, it occurs only slightly. When the processor attempts to access the internal memory of another processor module through the system bus and the internal memory of the processor is accessed by another processor, the bus arbiter of the system bus performs arbitration of the system bus. At this time, when the other processor obtains the right to use the bus, the memory arbiter operates, but since that processor has not issued a request to access the internal memory of its own processor module, the other external processor can use the memory. Access is guaranteed and deadlock does not occur.

Internal memory of a plurality of processor modules has a continuous address space through the system bus 1
By constructing a structure that can be regarded as one memory, software can be created in each processor in the same manner as the conventional large-capacity memory without regard for the processor module including the memory.

Further, the internal memory is divided into smaller areas, and each area is provided with an address changing means,
Each area has a separate address location,
In addition, by allowing a large continuous area to be created in the entire system without duplication, the optimal processor allocation is possible even for image data of different data sizes, and the source data and destination data are allocated continuously to each processor. can do.

Further, as seen from the processor, the internal memory of its own processor module has two address locations.
One of them has an internal fixed address irrelevant to the address changing means when accessed by one address location, and has a space specified by the address changing means of the above continuous address space when accessed by the other address location. As a result, if the data can be stored in the internal memory, the internal memory can be used without fail by accessing the former address, and the program can be operated under the same condition in any processor module.

When a processor of a certain processor module accesses a memory in a continuous address space that spans a plurality of processor modules, the setting of the address changing means is determined, and it is determined that the memory location in the processor module is accessed. If a mechanism to access via a bus buffer between a memory and a processor is provided instead of accessing via a system bus control circuit, a bus neck when accessing a large capacity memory in a multiprocessor configuration without any awareness of software is created. It can be resolved.

Further, by making it possible to change the address changing means by software, the address can be changed dynamically according to the data size to be handled.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In FIG. 1, the multiprocessor system according to the present invention comprises a plurality of processor modules 1, a system bus 2 connecting the processor modules 1, and a bus arbiter 3 for controlling the right to use the system bus 2. Each of the plurality of processor modules 1 includes a processor 4, a memory 5, and a system bus control circuit 6. The memory 5 is an internal memory arranged in the processor module 1.

The processor 4 and the memory 5 are connected by a bus via a bus buffer 7, and the memory 5 and the system bus 2 are connected by a bus via a bus buffer 8. The opening / closing operation of the bus buffers 7 and 8 is controlled by the memory arbiter 9, and when contention occurs, one of the bus buffers is opened. Access to the memory 5 from the processor 4 side or the system bus 2 side is exclusively selected by the memory arbiter 9 having the adjusting function.
Reference numeral 10 is a processor address decoder, and 11 is a system bus address decoder. For each of the processor address decoder 10 and the system bus address decoder 11, a change in address handling is executed based on the specified contents of the address switch 12 whose specified contents are changed in response to a command from the processor 4. It

The operation when the processor 4 accesses the memory 5 is as follows. The processor 4 outputs the memory address to the processor bus 13. The processor address decoder 10 receives the memory address and outputs the memory access request signal 14a to the memory arbiter 9 when it matches the area designated by the address switch 12 or when the address area is locally assigned to this memory. To do. The memory arbiter 9 receives the memory access request signal 14a, performs arbitration, waits immediately when the memory 5 is not used on the system bus 2 side, waits for the end when the memory 5 is used, and waits for the bus buffer. 7 is opened, and the processor 4 is made to access the memory. When the memory access from the processor 4 side is completed, the memory arbiter 9 closes the bus buffer 7.

The operation when an external processor belonging to another process module accesses the memory 5 through the system bus 2 is as follows. The external processor outputs the memory address to the system bus 2.
The system bus address decoder 11 receives this memory address and outputs a memory access request signal 14b to the memory arbiter 9 when it matches the area designated by the address switch 12. The memory arbiter 9 receives the access request signal 14b, performs arbitration,
Immediately when the memory 5 is not being used on the processor 1 side, and when the memory 5 is being used, the end of the memory 5 is awaited and the bus buffer 8 is opened to allow an external processor to access the memory. When the memory access from the system bus 2 side by the external processor is completed, the memory arbiter 9 closes the bus buffer 8.

When the access request signal 14a and the access request signal 14b are generated at the same time, the memory arbiter 9
Opens a bus buffer with a higher priority according to a predetermined priority, and after the memory access is completed, opens a bus buffer with a lower priority to perform another memory access.

The operation when the processor 4 accesses the internal memory of another processor module will be described. The processor 4 outputs the external memory address to the processor bus 13. The processor address decoder 10 receives the external memory address and outputs a system bus access request signal 15 to the system bus control circuit 6. The system bus control circuit 6 issues a bus use request to the system bus arbiter 3, obtains the bus use right from the system bus arbiter 3, and accesses the internal memory of another processor module. At this time, the same arbitration as described above is performed based on the memory arbiter provided inside the processor module of the other party.

As an application example, an example of performing filter calculation of 3 ³ matrix on 256 ³ image data will be described below. If 1 data is 2 bytes, the total amount of image data is about 32 Mbytes. Therefore, if the number of processor modules 1 is 16, one processor module requires at least 2 Mbytes of internal memory. Therefore, in this embodiment, the capacity of the internal memory per processor module is set to 8 Mbytes, and the memory area is divided into four banks.
The structure of the system bus address bits is assigned as shown in FIG. In the configuration of the system bus address bits, A section (2 ^{20-2 0)} is used in the bit position of the data representing the bank address, B section (2 ^{24-2 21)}
Is used for the bit position of the data (corresponding to the module numbers 0 to 15) to be compared with the contents of the address switch 12, and the C section (2 ²⁶ to 2 ²⁵ ) is the data for bank switching (to the bank numbers 0 to 3). Corresponding) bit position. In the system bus address bit configuration,
Further, it has a plurality of bits in the upper order. It is also possible to use these high-order bits to determine how to handle the B section. That is, based on the contents of the upper bits,
If desired, the data contents of part B can be used or can be arranged to be ignored. When using the data contents of the B section, the comparing section is made to input the B section data and the designated data of the address switch 12, and the comparing section compares the two data.

The contents of the portion B to be compared with the contents designated by the address switch 12 can be made variable by software technology. That is, the module number bit can be made variable by the selector controlled by software, and the address can be dynamically changed according to the data size to be handled.

When the allocation is performed as described above, as shown in FIG. 3, each processor module (PR0 to P0) is physically located.
The memory portion of banks 0 to 3 arranged in the internal memory of R15) is logically arranged such that banks having the same number in each processor module are arranged side by side. In FIG. 3, the physical memory arrangement and the logical memory arrangement are shown in contrast.

System bus address 0 to 33,554,431 (0
~1FFFFFF: 16 hex) to put 256 ³ of the original image data, the system bus address 33,554,432～67,108,864 (20
If the image data of 256 ³ is put in (00000 to 3FFFFFF: hexadecimal), 256 × 256 × 16 data for each of the original image data and the image data for calculation result will be stored in bank 0 and bank 1 of each processor module. It will be. In the filter calculation of this example, the calculation result image data of the pixel is obtained by multiplying the original image data of 3 ³ = 27 around a certain pixel by a certain count and adding them. Therefore, in the majority of operations, each processor performs an operation using the data in bank 0 of the internal memory of its own processor module and stores the result in bank 1, so that the processing can be executed without interfering with each other. However, 256 × 25 at the boundary between processor modules
Only when the data of 6 is calculated, the data of the internal memories of the adjacent processor modules are used. This state is shown by 16 in FIG.

Comparing the number of data accesses between the access to the internal memory and the access to the external memory,
The image data that one processor accesses for calculation is the original image data: 256 × 256 × 16 × 27 = 28,3
11,552 Calculation result image data: 256 × 256 × 16 = 1,04
8,576, and the total number of accesses is 29,360,128.

Referring to FIG. 4, among the above-mentioned access counts, the access to the external memory is as follows: Original image data: 256 × 256 × 9 × 2 = 1,179,
Only 648 times, which is about 4% of the total.

In the above configuration, the memory 5 in the processor module 1 of the processor 4 is
It has two address locations depending on whether or not to use the data contents of the copy, and when accessing at one address location, it becomes an internal fixed address irrelevant to the address switch 12, and when accessing at the other address location, the above continuous address Of the spaces, the space specified by the address switch 12 can be used.
As a result, if the data can be stored in the memory 5, the internal memory can be used without fail if the former address is accessed, and the program can be operated under the same condition in any processor module.

Further, when the processor 4 of the processor module 1 accesses a memory on a continuous address space which extends over a plurality of processor modules, the setting of the address switch 12 is judged and it is judged that the memory location in the processor module is accessed. In this case, the access is not made via the system bus control circuit 6, but is made through the bus buffer 7 between the memory 5 and the processor 4. As a result, the bus neck when accessing a large-capacity memory with a multiprocessor configuration can be eliminated without the software being aware of it.

The multiprocessor system having the above configuration is particularly suitable for data processing in image processing of the MRI apparatus. According to this system, it is possible to perform various high-speed processing on three-dimensional image data.

[0027]

As is apparent from the above description, according to the present invention, the bus neck of memory access can be eliminated at the time of parallel operation of multiprocessors, and the performance of each processor module can be fully utilized. Therefore, the system performance can be significantly improved. Also, if this multiprocessor system is applied to an image processing apparatus, sufficiently high-speed three-dimensional image processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system according to the present invention.

FIG. 2 is a diagram showing a configuration of a system bus address bit.

FIG. 3 is a diagram showing a correspondence relationship between a physical memory arrangement and a logical memory arrangement.

FIG. 4 is a diagram for explaining a 3 ³ matrix filter calculation.

FIG. 5 is a block diagram showing a configuration of a conventional multiprocessor system.

[Explanation of symbols]

 1 processor module 2 system bus 3 bus arbiter 4 processor 5 memory 6 system bus control circuit 7, 8 bus buffer 9 memory arbiter 12 address switch

Claims (6)

[Claims] 1. A multiprocessor system comprising a plurality of processor modules having a processor and a system bus control circuit for accessing an external memory through which the processor is connected to the system bus, wherein a plurality of the processor modules are provided. In each of the, provided with an internal memory accessible from the processor inside,
The internal memory and the processor are connected via a bus buffer, the internal memory and the system bus are connected via another bus buffer, and access from the processor side and the system bus side is performed. A multiprocessor system characterized in that a memory arbiter for detecting a request and exclusively controlling the two bus buffers for connection is provided so that the internal memory can be accessed from the system bus side. 2. The multiprocessor system according to claim 1, further comprising address changing means for changing an address location of said internal memory when accessing from the side of said system bus, and addressing said plurality of processor modules of the same type. A multiprocessor system characterized in that the internal memory of each processor module is constructed through the system bus so that it can be regarded as one memory having a continuous address space by implementing by shifting the location. 3. The multiprocessor system according to claim 2, wherein the internal memory is divided into a plurality of smaller areas, and the address changing means is provided individually in each of the areas, and each of the areas includes: A multiprocessor system characterized by taking large address areas apart from each other and forming a large continuous area in the entire system without duplication. 4. The multiprocessor system according to claim 2 or 3, wherein, when looking at the internal memory in its processor module from the processor, this internal memory has two address locations, and if one of the address locations is accessed, The multiprocessor system is characterized in that it has an internally fixed address irrelevant to the address changing unit, and when accessed at the other address location, it becomes a space designated by the address changing unit in the address space of the continuous area. 5. The multiprocessor system according to claim 2 or 3, wherein when the processor accesses a memory on a continuous address space extending over a plurality of processor modules, the setting of the address changing unit is determined. When you decide to access a memory location in your processor module. A multiprocessor system characterized by being accessed not through the system bus control circuit but through the bus buffer between the internal memory and the processor. 6. The multiprocessor system according to claim 3, wherein the address changing means provided corresponding to each of the plurality of small areas is configured to be changed by software. ..