JPH056661A - Image memory - Google Patents

Abstract

PURPOSE:To enable a window-shifting operation when a title item is used for an image display device for multi-window display and speeding up of screen erasure operation to be coped with. CONSTITUTION:A serial register B 13 which is capable of bi-directional shift for achieving data transfer in units of row with a memory array 1 as a transfer of internal data is provided in addition to a serial register 3 for serial output for a dual-port type memory array 1 with a random port and a serial port. A data of the serial register B13 is shifted by a required amount and only an arbitrary bit is transferred to the memory array 1 by using a transfer mask which is output from a write transfer mask generation circuit 14, thus enabling a window to be shifted at a high speed in an arbitrary direction while a background screen is saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port type image memory composed of a semiconductor memory device.

[0002]

2. Description of the Related Art An image display device for displaying image data such as figures and characters created on a computer on the screen of a raster scan type CRT requires an image memory called a frame buffer for storing display image data. As the image memory, a random port for writing image data generally generated on a CRT created on a computer and a serial port for reading continuous data required for display on the CRT are provided. Dual port memory is used.

This dual port memory is described, for example, in "Nikkei Electronics" p195-219 dated May 20, 1985, Nikkei McGraw-Hill, and has a configuration shown in FIG. In the figure, 1 is a memory array composed of memory cells designated by a row address and a column address for storing image data corresponding to a display screen, 3
Is a serial register for temporary storage of data for serial reading and writing of the memory array 1, and 2 is a transfer gate for data transfer between the memory array 1 and the serial register 3. Reference numerals 4 and 5 respectively denote a row decoder and a column decoder for decoding a row address and a column address to access a specific memory cell,
6 is an output data buffer, 7 is an input data buffer, 8 is an address buffer for address input, 9
Is a read circuit of the memory array 1, 10 is a write circuit of the memory array 1, and 11 is a controller. The row decoder 4, the column decoder 5, the buffers 6, 7 and 8, the read circuit 9 and the write circuit 10 constitute a random input / output port for the memory array 1, and the transfer gate 2 and the serial register 3 provide serial input / output for the memory array 1. The port is configured. The controller 11 outputs a control signal for internally controlling the operation of both ports. 20 to 24 are input / output signals and control signals of this dual port memory, and random data input / output 20 and address input 21 are random port signals and serial clock 23.
The serial data input / output 24 is a serial port signal. Further, the control signal 22 is input to the controller 11.

In the operation of writing image data to an arbitrary position in the memory array 1 through the random port, the row address and the column address of the memory array 1 to be accessed are given as an address input 21 in a time division manner. The row address and the column address are fetched by the address buffer 8 under the control of the control signal from the controller 11 and then input to the row decoder 4 and the column decoder 5, and as a result, the row address and the column address are obtained. An arbitrary memory cell in word units in the memory array 1 designated by and is accessed corresponding to a pixel on the screen. The image data given to the data buffer 7 as the random data input / output 20 is stored in the controller 11
It is taken into the data buffer 7 by the control signal from and is written in the accessed memory cell through the write circuit 10.

In the operation of reading image data from the memory array 1 through the random port, an arbitrary memory cell in word units in the memory array 1 is accessed by the address input 21 as in the writing operation, and the read circuit 9 is used. The read data is output from the data buffer 6 as the random data input / output 20.

During the serial data write operation through the serial port, first, the serial data input as the serial data input / output 24 is converted into the serial clock input 2
The data is sequentially sent to the serial register 3 based on the number 3.
Then, for the memory cells of one row of the memory array 1 selected by the row address for the memory array 1 given as the address input 21, the control signal 22 is received and the serial register 3 is generated by the control signal generated by the controller 11. Is transferred via the transfer gate 2.

In the serial data read operation through the serial port, first, the data for one row of the memory array 1 is selected by the row address for the memory array 1 given as the address input 21. The data for one row selected is transferred to the transfer gate 2 by the control signal generated by the controller 11 upon receiving the control signal 22.
Through the serial register 3. By sequentially outputting the data of the serial register 3 by the serial clock 23, the data of one row transferred to the serial register 3 is sequentially output as the serial data input / output 24.

FIG. 8 is a diagram showing an operation timing chart for reading serial data from the serial port.
As the control signal 22, a RAS signal that controls the input timing of the row address, a CAS signal that controls the input timing of the column address, and a D signal that controls the data transfer as shown in FIG.
WB / which controls the direction of T / OE signal and data transfer
The WE signal is input. The row address A1 of the memory array 1 that performs read transfer as the address input 21 at the timing t1 of the falling edge of the RAS signal, a signal of logic "0" indicating the transfer cycle as the DT / OE signal, and the WB / WE signal If a signal of logic "1" indicating a read transfer cycle is input as DT /
The data for one selected row of the memory array 1 is transferred to the serial register 3 at the timing t3 when the OE signal rises. Then, the data in the serial register 3 is sequentially shifted by the serial clock 23 to read data as the serial data input / output 24. Moreover, since the image data can be written to the memory array 1 from the random port even during the data reading from the serial port, the drawing speed of the image data is improved. However, the serial port was exclusively used for continuous transfer of display data to and from the CRT.

[0009]

In recent years, multi-window display is generally used in image display devices, and image data such as figures and characters created on a computer in arbitrary areas called a plurality of windows on the display screen. The ability to display is needed. The characteristics of multi-window display are
By displaying a plurality of windows, it is possible to perform a plurality of operations at the same time and to freely perform operations such as enlarging, reducing and moving the windows. In particular, moving windows is an operation that is frequently performed in a work environment with multi-window display, and improvement of window moving speed is strongly demanded to improve work efficiency. There is also a demand for erasing the screen within one window and speeding up the erasing of the entire display screen.

However, when the above-mentioned conventional image memory is used in an image display device for multi-window display, a random port must be used for window moving operation and screen erasing operation, and therefore access to memory cells is required. Not only does the number of operations become huge and the speed of these operations slows, but there is also the problem of requiring a complicated circuit outside. In other words, when moving a window, first read the display data from the random port, perform the shift operation outside the image memory, and then write this to the destination address in word units for the entire area of the window. I was doing it repeatedly. Further, even when the screen is erased, writing to a necessary area from the random port was repeatedly performed in word units.

In view of the above circumstances, an object of the present invention is to provide an image memory capable of coping with speeding up of window moving operation and screen erasing operation.

[0012]

In order to solve the above problems, the present invention employs a structure in which a transfer serial register is provided separately from the serial output register, and data in the image memory is moved at high speed in units of rows. did.

More specifically, the invention of claim 1 is as follows.
Assuming that the image memory has a memory array having a random access function based on a row address and a column address, it is possible to transfer data in units of rows to and from the memory array, and at least a serial output function. In addition to the first serial register, the second serial register capable of row-wise data transfer with the memory array is adopted.

According to a second aspect of the present invention, the second serial register in the first aspect of the present invention is composed of a shift register so as to correspond to a lateral movement of the window.
Further, a shift amount input means for inputting the shift amount data of the second serial register, a shift amount register for storing the shift amount data, and a counter for counting the shift clock given to the second serial register. And a comparator for comparing the contents of the shift amount register and the contents of the counter, and a shift control means for controlling the shift clock given to the second serial register based on the output of the comparator. Is.

According to a third aspect of the present invention, in order to realize high-speed movement of the window while preserving the background screen, in the first aspect of the present invention, the row-wise data transferred from the second serial register to the memory array is transferred. And a transfer mask generating means for outputting a transfer mask for designating whether or not to prohibit each bit, and transferring only bits of the contents of the second serial register which are not prohibited by the transfer mask to the memory array. And a transfer mask designating means for inputting a signal for determining the contents of the transfer mask to the transfer mask generating means.

According to a fourth aspect of the present invention, the second serial register is formed of a shift register in the first aspect of the present invention in order to realize a high-speed horizontal movement of the window while saving the background screen. Further, a shift amount input means for inputting the shift amount data of the second serial register, a shift amount register for storing the shift amount data, and a counter for counting the shift clock given to the second serial register. A comparator for comparing the contents of the shift amount register with the contents of the counter; shift control means for controlling the shift clock given to the second serial register based on the output of the comparator; and a memory from the second serial register. Output a transfer mask to specify for each bit whether to prohibit transfer of row-wise data transferred to the array. Transfer mask generating means, a data transfer means for transferring to the memory array only the bits of the contents after the shift of the second serial register that are not prohibited to be transferred by the transfer mask, and the transfer mask generating means for transferring the contents of the transfer mask. And a transfer mask designating means for inputting a signal for determining.

According to a fifth aspect of the present invention, the window can be moved to either the left or right direction. In the second or fourth aspect of the invention, the second serial register is formed of a shift register capable of bidirectional shift. Is.

A sixth aspect of the present invention relates to the structure of the data transfer means according to the third or fourth aspect of the present invention, wherein the data transfer means transfers the contents of the second serial register to the memory array. It is composed of the same number of transfer gates as the number of bits per row of the memory array, and transfer control means for determining opening / closing of each transfer gate by a transfer mask.

The invention of claim 7 is the invention of claim 3, 4 or 6.
Of the second serial register so that only data having an arbitrary bit width from an arbitrary bit of the contents of the second serial register is transferred to the memory array, the data in units of rows transferred from the second serial register to the memory array is transferred. A configuration is adopted in which signals for designating both ends of consecutive bits that do not prohibit transfer are input to the transfer mask generation means by the transfer mask designating means as signals for determining the contents of the transfer mask.

[0020]

According to the first aspect of the present invention, the image data of any one row written in the memory array is displayed even during the period in which the screen display is performed on the CRT using the first serial register having the serial output function. It can be read transferred to the second serial register and written transferred to another row of the memory array. Therefore, by using the row-by-row read transfer from the memory array to the second serial register and the row-by-row write transfer from the second serial register to the memory array, the inside of the image memory is moved when the window is moved in the multi-window display. It is possible to realize high-speed data movement only by itself. In addition, after the erase data is written in an arbitrary row of the memory array by using the random access function, the erase data is transferred to other rows by using the read transfer and the write transfer in row units between the memory array and the second serial register. Since the data can be duplicated in rows, the entire screen and the deletion in one window area can be executed at high speed.

According to the second aspect of the invention, in order to move the window laterally by a desired amount, the data read from the memory array to the second serial register is shifted in the second serial register, and the shift is performed. Later data is written and transferred from the second serial register to the memory array. Moreover, the start and end of the shift in the second serial register are internally controlled. For this purpose, first, the data of the required shift amount of the second serial register inputted through the shift amount input means is stored in the shift amount register. When the shift amount register stores the shift amount data, the contents of the shift amount register become larger than the contents of the counter which is reset in advance. Therefore, the comparator and the shift control means operate to shift the shift clock to the second serial register. The shift of the data in the second serial register is started. The shift clock supplied to the second serial register is counted by the counter, and when the count value reaches the content stored in the shift amount register, the comparator and the shift control means are activated to generate the second clock.
The shift in the serial register of stops automatically.

According to the invention of claim 3, in order to move the window to a desired position while saving the background screen,
A transfer mask is applied to the data read from the memory array to the second serial register, and this is written and transferred to the memory array. Therefore, the transfer mask generating means outputs the transfer mask based on the signal input through the transfer mask designating means. This transfer mask specifies, for each bit, whether or not to prohibit the transfer of the row-unit data transferred from the second serial register to the memory array, and the data transfer means is the second serial register. Only the bits of which the transfer is not prohibited by the transfer mask are transferred to the memory array.

According to the fourth aspect of the present invention, it is possible to shift the data in the second serial register by an arbitrary amount and transfer only the arbitrary bit to the memory array using the transfer mask. Moreover, the start and end of the shift in the second serial register are internally controlled.

According to the invention of claim 5, the data in the second serial register is shifted to the left when the window is moved to the left, and the data in the second serial register is moved to the right when the window is moved to the right. Shift to.

According to the invention of claim 6, the data transfer means for transferring to the memory array only the bits of the contents of the second serial register which are not prohibited by the transfer mask are transferred per row of the memory array. It is composed of transfer gates of the same number as the number of bits, and transfer control means for determining opening / closing of each transfer gate by a transfer mask. Only the transfer gate opened according to the contents of the transfer mask will perform the write transfer from the second serial register to the memory array.

According to the seventh aspect of the present invention, the transfer mask designating means provides signals for designating both ends of consecutive bits which do not inhibit the transfer of the row-unit data transferred from the second serial register to the memory array. Only by inputting to the transfer mask generating means, a transfer mask is created based on this signal, and only the data of any bit to any bit width of the contents of the second serial register is transferred to the memory array. Therefore, it is easy to specify the moving destination of the window.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, an image memory is provided with a serial register for transferring one row of data written in a memory array to another arbitrary row, in addition to a serial output register. 1 is a block diagram showing the configuration of an embodiment of the image memory of the present invention. In the figure, the memory array 1, the transfer gate 2, the serial register 3, the row decoder 4, the column decoder 5, the buffers 6, 7 and 8, the read circuit 9 and the write circuit 10 have the same configurations as those of the conventional configuration shown in FIG. A dual port memory having a function and having a random port and a serial port is configured. Further transfer gate B for high-speed internal data transfer
12, a serial register B13 and a write transfer mask generation circuit 14 are provided. Serial register B
Reference numeral 13 denotes a memory array 1 via a transfer gate B12 having a configuration similar to that of the transfer gate 2 like the serial register 3.
Is a serial data register having a storage capacity for one row of the memory array 1 capable of parallel write transfer and read transfer. Reference numeral 14 is a write transfer mask generation circuit, which is a circuit for generating a transfer mask for controlling the transfer gate B12 to transfer only an arbitrary bit when writing and transferring the data of the serial register B13 to the memory array 1. is there. The write transfer mask generation circuit 14 generates mask data corresponding to the output bit of the serial register B13 from the data of the transfer start position and the transfer end position given as the random data input / output 20, and this circuit is a general combination. Since it can be realized by a circuit, details are not described. The controller 11 outputs a control signal for internally controlling the operations of the random port, the serial port and the internal data transfer. 20 to 25 are input / output signals of this dual port memory, signals for internal data transfer and control signals, and random data input / output 20 and address input 21 are random port signals, serial clock 23 and serial data input / output. Reference numeral 24 is a serial port signal, and shift clock 25 is a signal given to the serial register B13 at the time of internal data transfer. Further, the control signal 22 is input to the controller 11.

The operation of writing and reading image data to and from the memory array 1 through the random port and the reading and writing of serial data as the serial data input / output 24 has the conventional structure shown in FIG. The detailed description is omitted here, and one row of data is read from the memory array 1 and transferred to the serial register B13, and the contents of the serial register B13 are shifted. The operation of the internal data transfer for writing and transferring to will be described.

An operation timing chart of this internal data transfer is shown in FIG. As the control signal 22 given to the controller 11, the RAS signal for controlling the input timing of the row address, the CAS signal for controlling the input timing of the column address, the DT / OE signal indicating the data transfer cycle, the data transfer as shown in FIG. WB / that controls the direction of
In addition to the WE signal, two serial registers 3 and 1
D which controls which of the three is the data transfer destination
The TC signal and the SFT signal that controls the direction of data shift in the serial register B13 are input.

From memory array 1 to serial register B1
In the read transfer cycle to 3, the row address A of the memory array 1 which transfers data as the address input 21 at the timing t1 of the falling edge of the RAS signal.
1, a signal of logic "0" indicating a data transfer cycle as the DT / OE signal, a signal of logic "1" indicating the read transfer of the memory array 1 as WB / WE, DTC
By inputting a signal of logic "1" indicating that the transfer cycle is a transfer to the serial register B13 and a signal indicating the direction of data shift as the SFT signal, the timing t3 of the rising edge of the DT / OE signal is input.
Then, the selected row of data in the memory array 1 is transferred to the serial register B13. After the transfer is completed, the number of shift clocks 25 corresponding to the required shift amount is applied to shift the data transferred to the serial register B13. The direction of data shift is determined by the value of the SFT signal given at the timing t1.

When the shift operation of the serial register B13 is completed, the write transfer cycle from the serial register B13 to the memory array 1 is started. In this transfer operation, the falling timing t4 of the RAS signal
The address input 21 is the row address A2 of the transfer destination to the memory array 1, the random data input / output 20 is the data D1 indicating the transfer start position for the storage data of the serial register B13, and the DT / OE signal is the logic indicating the data transfer cycle. A signal of "0", a signal of logic "0" that indicates write transfer to the memory array 1 as WB / WE, and a logic "1" that indicates that the transfer cycle is transfer from the serial register B13 as a DTC signal. And the data D2 indicating the transfer end position for the stored data of the serial register B13 is given as the random data input / output 20 at the timing t5 of the fall of the CAS signal. Serial register B
The data D1 at the write transfer start position and the data D2 at the write transfer end position for 13 are given to the write transfer mask generation circuit 14, and write transfer is prohibited except for the bit sandwiched between the write transfer start position and the write transfer end position. Write transfer mask data is created by the write transfer mask generation circuit 14. The contents of this transfer mask are given to the transfer gate B12, and the data of the serial register B13 corresponding to the bit which can be written and transferred at the rising timing t6 of the DT / OE signal is transferred to the selected one row of the memory array 1. .

FIG. 3 is an operation explanatory diagram when the window moving operation is performed by using the image memory of the present embodiment described above in the image display device of the multi-window display. FIG. 10A shows the entire display screen, and consider the case where the window displayed at the position A is moved to the position B. First, as shown in FIG.
The data in the row in which the data in the upper window A is written is read out and transferred to the serial register B13. Then, the data in the serial register B13 is right-shifted by a required amount, so that the data in the window A is moved to a position corresponding to the destination window B, as shown in FIG. The data of the serial register B shown in FIG. 7C is transferred to the row of the memory array 1 corresponding to the window B. At this time, the data is transferred only to the area of the window B, as shown in FIG. The write transfer mask shown in is used. Write transfer is performed after setting the write transfer mask so as to prohibit transfer of data other than the data corresponding to the position of the window B. By repeating the above operation over all the rows of the window A, the window A moves to the window B in the upper right direction.

Since the operation of moving the data written in the memory array 1 to another position can be executed in the row unit of the memory array 1 by using the serial register B13, only the high speed movement becomes possible. Instead, by writing from the random port to only one row of the memory array 1 and copying the written data to another row using the serial register B13, the entire display screen is erased, the window area is erased, and the wide area is widened. It is possible to perform high speed filling of various areas.

FIG. 4 shows an example of the circuit configuration of the transfer gate B12 and the serial register B13 for the internal data transfer. 30 to 32 are the control signals 22
It is an internal control signal generated from. The serial register B13 is a flip-flop 13a-1 to 13a-n.
To store the data. Reference numerals 13c-1 to 13c-n are selection circuits for selecting, by the shift direction control signal 32, which of the left and right flip-flop outputs the data to be input to the flip-flops 13a-1 to 13a-n during the shift operation. The direction of shift by the shift clock 25 is controlled. 13b-1 to 13b-n are flip-flops 13a-1
Selection circuit 13c-1 to 1 to input data to 13a-n
It is a switching circuit for switching between the output of 3c-n and the output of the memory array 1, and the output of the memory array 1 during the read transfer and the selection circuit 13c-1 during the shift operation.
It is controlled by the read transfer control signal 31 so as to select each of the outputs of .about.13c-n. Reference numeral 33 denotes an OR gate, which is used to output the read transfer control signal 31 during read transfer and the shift clock 25 during shift operation.
Are applied as clocks to the flip-flops 13a-1 to 13a-n, respectively. By adopting such a configuration,
During a read transfer operation, the output of the memory array 1 is flip-flop 13a-1 ...
13a-n, the data of the flip-flops 13a-1 to 13a-n are written to the shift clock 25 during the shift operation.
To shift left or right.

The transfer gate B12 includes transfer gates 12a-1 to 12a-n and AND gates 12b-1 to 12b-n.
Composed of and. By the signal from the write transfer mask generation circuit 14, the write transfer control signal 30 is given only to the transfer gate corresponding to the write transferable bit, and only the necessary bit of the serial register B13 is transferred to the memory array 1.

Now, in the embodiment shown in FIG.
As can be seen from the operation explanatory diagram shown in (1), it is necessary to externally control the number of shift clocks 25 given to the serial register B13 in accordance with the required shift amount. FIG. 5 is a block diagram showing another embodiment of the present invention in which the start and end of shift in the serial register B13 are internally controlled only by giving continuous shift clocks if shift amount data is given in advance. . In the figure, a memory array 1, a transfer gate 2, a serial register 3, a row decoder 4, a column decoder 5, buffers 6, 7 and 8, a read circuit 9, a write circuit 10, a transfer gate B12, a serial register B13 and a write transfer mask generation. Circuit 14
Has the same function as the configuration shown in FIG. 1
6 is a shift amount register for storing the data of the shift amount given as the address input 21 through the address buffer 8, 18 is a counter for counting the shift clock given to the serial register B13, 17 is the contents of the shift amount register 16 and the counter 18 Comparing with the contents of the above, reference numeral 15 is an AND gate. A controller 11 internally controls the operations of the random port, the serial port, and the internal data transfer, and outputs a control signal for resetting the shift amount register 16 and the counter 18.

An operation timing chart of internal data transfer corresponding to FIG. 2 is shown in FIG. Explaining with reference to FIG. 5 and FIG. 6, in the read transfer cycle from the memory array 1 to the serial register B13, the timing t of the fall of the RAS signal as the address input 21
Row address A of memory array 1 for data transfer at 1
1, and the shift amount A3 of the serial register B13 is given at the timing t2 when the CAS signal falls. The other signals give the same values as in FIG. The shift amount register 16 and the counter 18 are both reset to 0 at this time point, and the output of the comparator 17 is logic "0". Therefore, at this point, AND gate 15
Shift clock 25 applied to one input terminal
Is not given to the serial register B13.

Shift amount A3 of serial register B13
Is transferred from the address buffer 8 to the shift amount register 16 at the timing t3 when the transfer operation from the memory array 1 to the serial register B13 is completed. When the shift amount register 16 stores the transferred shift amount A3, the content of the shift amount register 16 becomes larger than the content (0) of the counter 18, so that the output of the comparator 17 becomes logic "1" and the AND gate. The shift clock 25 is given to the serial register B13 via 15 and the serial register B1
3 starts the shift operation. The shift clock supplied to the serial register B13 is counted by the counter 18, and when the counted value matches the shift amount held in the shift amount register 16, the output of the comparator 17 becomes logic "0" again. Therefore, the AND gate 15 is closed and the shift operation of the serial register B13 is stopped (timing t7). The output of the comparator 17 is shift status 2
6 is output to the outside, and the write transfer cycle from the serial register B13 to the memory array 1 is started by observing this signal. The write transfer cycle after the timing t4 is performed in the same manner as the above-described operation shown in FIG.

[0039]

As described above, according to the first aspect of the invention, in the dual port memory having the random port and the serial port, the first serial output memory is provided.
In addition to the serial register of the second, the second unit capable of row-wise data transfer with the memory array for internal data transfer.
Since the configuration in which the serial register is provided is adopted in the image display device for multi-window display, read transfer and write transfer in row units between the memory array and the second serial register are performed. Using this, you can perform window moving operations and screen clearing operations at high speed.

According to the invention of claim 2, in the invention of claim 1, the second serial register is constituted by a shift register, and shift amount input means for inputting the data of the shift amount of the second serial register. A shift amount register for storing shift amount data, a counter for counting a shift clock given to the second serial register, a comparator for comparing the contents of the shift amount register with the contents of the counter, Since the shift control means for controlling the shift clock given to the second serial register based on the output of the comparator is adopted, the data read from the memory array to the second serial register is stored in the second serial register. It is possible to move the window in any direction by shifting and writing and transferring to the memory array. That. Moreover, if the required shift amount data is given in advance, the start and end of the shift in the second serial register are internally controlled only by giving a continuous shift clock.

According to the invention of claim 3, in the invention of claim 1, it is possible to specify, for each bit, whether or not the transfer of the data in units of rows transferred from the second serial register to the memory array is prohibited. Transfer mask generating means for outputting a transfer mask; data transfer means for transferring only the bits of the contents of the second serial register which are not prohibited to be transferred by the transfer mask to the memory array; Since the structure further comprising a transfer mask designating means for inputting a signal for determining the content is adopted, the data read from the memory array to the second serial register is masked with a transfer mask and then written and transferred to the memory array. By doing so, the window can be moved to a desired position while saving the background screen.

According to the invention of claim 4, in the invention of claim 1, the second serial register is constituted by a shift register, and the shift amount data of the second serial register is further inputted. Shift amount input means,
A shift amount register for storing shift amount data, a counter for counting the shift clock given to the second serial register, a comparator for comparing the contents of the shift amount register with the contents of the counter, and a second Shift control means for controlling the shift clock given to the serial register based on the output of the comparator, and designation for each bit as to whether or not the transfer of row unit data transferred from the second serial register to the memory array is prohibited Transfer mask generating means for outputting a transfer mask for performing transfer, a data transfer means for transferring to the memory array only bits that are not prohibited by the transfer mask in the shifted contents of the second serial register, and a transfer mask. And a transfer mask designating means for inputting a signal for determining the content of the transfer mask to the generating means. Since the data in the second serial register is shifted by an arbitrary amount and only the arbitrary bits are transferred to the memory array using the transfer mask, the window can be displayed in any direction while preserving the background screen. It can be moved at high speed. Moreover, the start and end of the shift in the second serial register are internally controlled.

According to the invention of claim 5, in the invention of claim 2 or 4, the second serial register is composed of a shift register capable of bidirectional shift, so that the window can be moved in either left or right direction. It is possible.

According to the invention of claim 6, the same number as the number of bits per row of the memory array for transferring the contents of the second serial register to the memory array by the data transfer means in the invention of claim 3 or 4. The transfer gate and the transfer control unit that determines the opening and closing of each transfer gate by the transfer mask are configured, so that the configuration of the data transfer unit is simplified.

According to the invention of claim 7, in the invention of claim 3, 4 or 6, only data of any bit width from any bit of the contents of the second serial register is transferred to the memory array. Further, the transfer mask designating means transfers signals for designating both ends of consecutive bits of the row unit data transferred from the second serial register to the memory array, which do not inhibit the transfer, as signals for determining the contents of the transfer mask. Since the configuration input to the mask generation means is adopted, it becomes easy to specify the destination of the window.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an image memory of the present invention.

FIG. 2 is an operation timing chart diagram of internal data transfer of the image memory of FIG.

3A and 3B are operation explanatory views when a window moving operation is performed by using the image memory of FIG. 1 in an image display device of multi-window display, in which FIG. 3A is a display screen and FIG. The data in the window A immediately after being read and transferred is shown in (c) to the serial register B right-shifted to a position corresponding to the destination window B.
Of data, and (d) shows the data of the write transfer mask.

4 is a circuit diagram showing an example of a circuit configuration of a transfer gate B and a serial register B in FIG.

FIG. 5 is a block diagram showing the configuration of another embodiment of the image memory of the present invention.

6 is an operation timing chart diagram of internal data transfer of the image memory of FIG.

FIG. 7 is a block diagram showing a configuration of a conventional dual port type image memory.

8 is an operation timing chart diagram of serial data reading of the image memory of FIG. 7. FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory array 2 ... Transfer gate 3 ... Serial register (first serial register) 4 ... Row decoder 5 ... Column decoder 6, 7 ... Data buffer (transfer mask designating means) 8 ... Address buffer (shift amount inputting means) 9 ... Read circuit 10 ... Write circuit 11 ... Controller 12 ... Transfer gate B (data transfer means) 12a-1 to 12a-n ... Transfer gates 12b-1 to 12b-n ... AND gate (transfer control means) 13 ... Serial register B (Second serial register) 14 ... Write transfer mask generation circuit (transfer mask generation means) 15 ... AND gate (shift control means) 16 ... Shift amount register 17 ... Comparator 18 ... Counter

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G09G 5/36 8121-5G

Claims (7)

[Claims] 1. An image memory having a memory array having a random access function based on a row address and a column address, capable of row-by-row data transfer with the memory array, and at least serial. An image memory comprising a first serial register having an output function and a second serial register capable of row-wise data transfer with the memory array. 2. The image memory according to claim 1, wherein the second serial register is a shift register that operates by receiving a shift clock, and further, the shift amount data of the second serial register is input. A shift amount input means, a shift amount register for storing the shift amount data, a counter for counting a shift clock given to the second serial register, a content of the shift amount register and a content of the counter. And a shift control means for controlling the shift clock given to the second serial register based on the output of the comparator. 3. The image memory according to claim 1, wherein a transfer mask for designating, for each bit, whether or not transfer of the row unit data transferred from the second serial register to the memory array is prohibited. Of the contents of the second serial register, data transfer means for transferring only the bits of the contents of the second serial register that are not prohibited to be transferred by the transfer mask to the memory array, and the transfer mask generating means An image memory further comprising transfer mask designating means for inputting a signal for determining the contents of the transfer mask. 4. The image memory according to claim 1, wherein the second serial register is a shift register that operates by receiving a shift clock, and further input data of a shift amount of the second serial register. A shift amount input means, a shift amount register for storing the shift amount data, a counter for counting a shift clock given to the second serial register, a content of the shift amount register and a content of the counter. For comparing the shift clock given to the second serial register based on the output of the comparator, and a row unit transferred from the second serial register to the memory array. A transfer mask that outputs a transfer mask for specifying for each bit whether transfer is prohibited for data Generating means, data transfer means for transferring to the memory array only those bits of the contents after shifting of the second serial register that are not prohibited by the transfer mask, and the transfer mask for the transfer mask generating means. An image memory, comprising: a transfer mask designating means for inputting a signal for determining the content of the. 5. The image memory according to claim 2, wherein the second serial register is a shift register capable of bidirectional shift. 6. The image memory according to claim 3 or 4, wherein the data transfer means transfers the content of the second serial register to the memory array by the number of bits per row of the memory array. An image memory having the same number of transfer gates and transfer control means for determining opening / closing of each transfer gate by the transfer mask. 7. The image memory according to claim 3, 4 or 6, wherein only data having an arbitrary bit width from an arbitrary bit of the contents of the second serial register is transferred to the memory array. , The transfer mask designation is a signal for designating both ends of consecutive bits of the row unit data transferred from the second serial register to the memory array, which does not inhibit the transfer, as a signal for determining the contents of the transfer mask. An image memory which is input to the transfer mask generation means by means.