JPH0562463A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] Direct sense dynamic RAM
It is intended to increase the data read speed and reduce the access variation due to the address. [Structure] A common I / O line is separated into a read line and a write line, and a shared MOS is provided on a data line. When the shared MOS is used, a sense amplifier other than the read common I / O line is read. After the write I / O, precharge MOS, etc. are separated from the data line and read by the direct sense method, the shared MOS is turned on and the sense amplifier amplifies the level difference of the data line,
Rewrite the selected memory cell. [Effect] The data line capacity at the time of reading can be reduced, and the data line signal amount increases, so that there are effects of high-speed access and reduction of access variations due to addresses. Furthermore,
It is possible to improve the performance and reliability of the memory without increasing the chip area and the cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to a circuit system of a semiconductor memory device, and more particularly to a technique effectively applied to a dynamic RAM of a direct sense system.

[0002]

2. Description of the Related Art As a data read method in a conventional dynamic RAM, a data line is precharged to Vcc / 2 level in advance, and a sense amplifier connected to a data line at an appropriate timing after a word line rises. There is a Vcc / 2 precharge system in which the Y-system switch is turned on to connect to the main amplifier via the common I / O line after driving the signal to amplify the potential difference generated in the data line.

On the other hand, in recent years, by turning on the Y-system switch before driving the sense amplifier and connecting it to the main amplifier via the common I / O line, the direct sense for increasing the read speed is achieved. System dynamic RAM
Has been put to practical use (Hitachi, 4 megabit BI
CMOS dynamic RAM: HM574000).

[0004]

The data line capacitance Cd in this type of dynamic RAM is determined by the wiring capacitance of the data line itself, the sense amplifier, and the connection switch MO to the I / O.
It is the sum of the load capacitances of circuits connected to the data lines such as S and precharge MOS, and the ratio occupied by the components other than the wiring capacitances of the data lines is about 1/3 of the whole in the dynamic RAM. Met. As a condition for high-speed access and reduction in access variation in the direct sense system, a large data read signal, that is, the memory cell accumulated charge capacity Cs
It is important that the ratio of the data line capacitance Cd to the data line capacitance Cd is large. However, as the dynamic RAM is highly integrated and has a large capacity, a processing technique is required to increase the information storage charge capacitance Cs.
There are limits in terms of layout.

Therefore, in a dynamic RAM which is required to have a high degree of integration and a large capacity, in order to obtain a large read signal amount for high speed access, a memory cell using a trench capacitor or the like is provided in a three-dimensional manner or a data memory. -Although a means of subdividing the wire has been taken, it results in impeding the yield and the cost reduction such as the limitation of the processing technology and the increase of the chip area. In the present invention, even if the information storage charge capacity Cs cannot be made large due to restrictions on the processing technology, chip area, etc.,
It is possible to increase the amount of data read signals, enable high-speed access and reduce access variations, and improve the performance and reliability of the memory without increasing the chip area and cost.

[0006]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. The present invention relates to a dynamic RAM using a direct sense method for reading data,
Paying attention to the fact that a sense amplifier having a relatively large parasitic capacitance is not required at the time of reading data, the common I / O line is separated into a read I / O line and a write I / O line, and a switch MOSFET (hereinafter referred to as a shared MOS) on the data line. The shared MOS is used to separate the sense amplifier other than the common I / O line for reading, the write I / O, the precharge MOS, etc. from the data line at the time of reading, and the read is performed by the direct sense method. The shared MOS is turned on, the level difference of the data line is amplified by the sense amplifier, and rewriting (rewriting) is performed on the selected memory cell.
It is something that allows you to. Also, shared MOS
Turn on and off two sets of shared MOSs provided on the data line, including sense amplifiers other than the read common I / O line, common write I / O line, precharge MOS, etc. Are shared by the two memory arrays.

[0007]

According to the above means, by turning off the shared MOS at the time of reading the data, the circuit connected to the data line can be made only the common I / O line for reading, and at the time of reading the data. It is possible to reduce the apparent data line capacitance Cd,
As a result, a large amount of data line signal can be obtained at the time of reading without increasing the information storage charge capacity Cs in the memory cell. As a result, it becomes possible to perform high-speed access and reduce access variations, and it is possible to improve the performance and reliability of the memory without increasing the chip area and cost.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a dynamic RAM will be described below with reference to FIGS.
FIG. 1 is a block diagram of the entire dynamic RAM to which the present invention is applied, and FIG. 2 is a circuit diagram showing a set of data lines sharing a sense amplifier in FIG. In FIG. 1, the dynamic RAM according to the embodiment is not particularly limited, but includes two memory arrays ARY0 and ARY1, and correspondingly, X decoders XDEC0, XDEC1 and Y decoders YDEC0, YDEC1. .. In addition, the read I /
ORI / O0 and RI / O1 are arranged, and the sense amplifier S.A and the write I / O are provided between the read I / O RI / O0 and RI / O1 via the shared MOS SHR0 and SHR1. Circuits such as / OWI / O0, WI / O1, and precharge MOSFET circuit PCMOS are arranged as a common circuit. Incidentally, IOC is a data input / output buffer circuit, and I / O is a common data input / output terminal.

The X address buffer XAB receives the X signal from the timing generator TG which is operated by the clock signal.
Addresses from the outside are taken in at the rising timing of the address take-in signal XL, and X decoders XDEC0, XDEC
At 1, the word line drive signal is formed and one corresponding word line is selected, and the level is changed to the selected level for reading and writing data. Similarly, the Y address buffer YAB takes in the address at the timing of the Y address take-in signal YL from the timing generator TG, and the Y decoder Y
A set of data lines is selected by DEC0 and YDEC1,
Re-domain amplifier R.P. MA or Light Main Amplifier W. Connected to MA.

The word lines WL in the memory arrays ARY0 and ARY1 are arranged vertically as shown in FIG. 2, and the data lines DL and DL 'are arranged horizontally.
The memory cells MC are arranged at their intersections. QD
01 and QD02 are differential MOSFETs provided for detecting the level difference between the data lines DL and DL 'of the left memory array ARY0, and QD11 and QD12 are data lines DL and DL' of the right memory array ARY1. Of the differential MOSFETs QD01, QD02 and QD11, Q provided for detecting the level difference of
The gate terminal of D12 is connected to the data lines DL and DL ', respectively, and the common source terminal is connected to the ground point of the circuit.

Further, the differential MOSFETs QD01, QD
The drain terminal of 02 is a column switch Qy0 for read.
1, I / O line RI / O0 for read via Qy02,
The drain terminals of the differential MOSFETs QD11 and QD12 are connected to the read I / O lines RI / O0 and RI / O1 via column switches Qy11 and Qy12, respectively. At the other ends of the read I / O lines RI / O0 and RI / O1, the main read amplifier R.O. MA is connected. Furthermore, the left and right memory arrays ARY0, A
The data lines DL and DL 'in RY1 are provided with two sets of switches M.
Shared MOS Qs01, Qs consisting of OSFET
02, Qs11, Qs12, and the shared MOS Qs01, Qs02, and Qs1.
Left and right memory arrays ARY0, AR between 1 and Qs12
A common sense amplifier S.Y. A and a Vcc / 2 precharge circuit PCMOS are arranged.

Further, the sense amplifier S. A and Vcc / 2
Precharge circuit PCMOS and shared MOS Qs
Between 01, Qs02 and Qs11, Qs12,
Light column switches Qw01, Qw02 and Qw1
1 and Qw12 are arranged, and these write column switches Qw01, Qw02 and Qw11, Qw12 are arranged.
The data lines DL and DL ′ in the left and right memory arrays ARY0 and ARY1 are respectively connected via the write I / O line WI /
It is connectable to O0 and WI / O1. I for light
/ O lines RI / O0 and RI / O1 are connected to the write main amplifier W. MA is connected. Note that among the MOSFETs shown in FIG. 2, the one with an arrow is a P-channel type and is distinguished from the N-channel type MOSFET without an arrow.

The operation of the dynamic RAM of this embodiment will be described below. In the standby mode, the shared signals SHR0 and SHR1 are both set to the high level (Vcc level), and the shared MOS Qs01 and Qs on both sides are shared.
02, Qs11 and Qs12 are turned on. Further, the data line is precharged to Vcc / 2 by fixing the precharge signal PC to the high level. At the time of data read, as shown in FIG. 3, the shared signals SHR0 and SHR.
Since both HR1 are changed to the low level, the shared MOS Qs01, Qs02 and Qs11 on both sides,
Qs12 is turned off. As a result, the data line capacity is limited to the wiring capacity of the memory array section and the gate capacity of the read column switch.

When the memory array ARY0 is selected by taking in the X address signal by the address buffer XAB, the accumulated charge capacity Cs of the selected memory is shared MO.
Data line capacitance C reduced by SQs01 and Qs02
By redistributing with d, a relatively large data line read signal output can be obtained and high-speed direct sensing becomes possible. Read main amplifier R. When the sensing by MA is completed, rewriting is performed. This rewrite is performed by the logic of the address Xi and the shared signal SHR0, and the shared MOS Qs01, Qs on the selected side.
02 is turned on at a voltage higher than the (Vcc + Vth) level,
Sense amplifier S. By connecting to A, the data line D
This is done by amplifying the small level difference between L and DL '.
(Vth is the threshold voltage of the MOSFET). At the time of precharging the data line, as shown in FIG. 4, the shared signals SHR0 and SHR1 are changed to the Vcc level instead of the (Vcc + Vth) level and the shared MOS Qs0 is changed.
1, Qs02 or Qs11, Qs12 may be turned on. In this embodiment, since the precharge of the data line is at Vcc / 2 level, the output level of the amplifier can be set sufficiently to the data lines DL and D at the time of rewriting or writing.
This is because there is no need to inform L '. The shared signal SHR is a chip select signal C supplied from the outside.
E (RAS in this embodiment) and the write enable signal W
E and the address signals X0 to Xi.

When writing data, the shared M on the selection side
OS Qs01, Qs02 or Qs11, Qs12 is turned on at a voltage higher than (Vcc + Vth) level, and the data lines DL, DL 'are connected to the write I / O line WI / O0 or WI / O1. W.
Data is written in the selected memory cell by MA. In the above embodiment, two sets of shared MOS are used.
Between Qs01 and Qs02 or Qs11 and Qs12, the sense amplifier S. Only A and the precharge circuit PCMOS are provided as a common circuit, and the write column switch Qw0
1, Qw02 and Qw11, Qw12 and write main amplifier W. The MA is provided for each memory array, but the write column switch and the write main amplifier may be shared between the two memory arrays.

In the above embodiment, the read main amplifiers R.O. and R.O1 are connected to the other ends of the read I / O lines RI / O0 and RI / O1, respectively. Although the MA is connected, the above share also exists on the read I / O lines RI / O0 and RI / O1.
A switch MOSFET similar to the de-MOS is provided and the main amplifier R. The MA may be shared by the two memory arrays. Further, in the above-mentioned embodiment, the type in which each memory array has a read I / O line in the dynamic RAM composed of two memory arrays has been explained, but in the dynamic RAM composed of an even number of memory arrays such as four or eight memory arrays. One read I / O line can be shared between two memory arrays. In that case, as shown in FIG. 5, four memory arrays ARY0, ARY1, ARY2, and ARY3 are arranged in the horizontal direction, and the read I / O line RI / O and the main amplifier MA are provided between the memory arrays ARY1 and ARY2. You may make it shared. Furthermore, read column switches Qy01, Qy02 and Qy11, Qy12 and write column switches Qw01, Qw02 and Qw11, Qw.
By forming the signal line for transmitting the signal YS for controlling ON / OFF of 12 and the data lines DL and DL ′ in different wiring layers, respectively, the pitch of the memory array can be reduced and the chip area can be reduced. good.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a semiconductor memory device such as a dynamic RAM. (1) In a dynamic RAM for reading data by direct sense, the sense amplifier, write I / O, precharge MOS, etc., which are not directly related to the read operation, are separated by the shared MOS, and thus the data line The capacity can be reduced and a large data read signal can be obtained. Therefore, it is possible to obtain an effect that high-speed access and access variation are reduced. (2) Since the sense amplifier, the write I / O, the precharge MOS, etc. which are not directly related to the read operation are shared between the two arrays by the shared separation method, the chip area can be reduced. ..

Although one embodiment of the present invention has been specifically shown above, the present invention is not limited to the above embodiment,
It goes without saying that various changes can be made without departing from the spirit of the invention. For example, in the above embodiment, the shared M
Depending on the OS, the sense amplifier S. A and precharge circuit PC
Although the MOS is configured to be separable from the data lines of the two memory arrays, the parasitic capacitance of the data line is caused by the sense amplifier S.S. Since A is the largest, only the sense amplifier may be configured to be separable from the data line when reading data. In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
Although the one applied to the AM has been described, it can be used for general read circuits of semiconductor memory devices.

[0019]

The outline of typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, Cd / Cs can be lowered without increasing the memory cell accumulated charge capacity Cs by separating unnecessary circuit portions by the shared MOS at the time of data reading, so that the amount of data read signal is increased. It becomes possible and high-speed access can be realized. Further, the access variation due to the address is reduced by the sufficient data read signal. Further, since the sense amplifier, the write I / O, the precharge MOS and the like can be shared between the two memory arrays, the chip area can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a direct sense dynamic RAM to which the present invention is applied.

FIG. 2 is a circuit diagram showing a circuit configuration example in data line units in the dynamic RAM of FIG.

FIG. 3 is a time chart showing the timing of signals at the time of reading data in the dynamic RAM shown in FIG.

4 is a time chart showing another example of the level of a precharge signal at the time of precharging a data line in the dynamic RAM of FIG.

FIG. 5 is a block diagram showing another embodiment of a mat structure of a memory array of a direct sense dynamic RAM to which the present invention is applied.

[Explanation of symbols]

ARY0, ARY1 Memory array SHR0, SHR1 Shared MOS YAB Y address buffer XAB X address buffer YDEC0, YDEC1 Y decoder XDEC0, XDEC1 X decoder RI / O0, RI / O1 Read I / O WI / O0, WI / O1 I / OS for writing. A sense amplifier PCMOS precharge MOS TG timing generator R.A. MA re-domain amplifier W. MA write main amplifier IOC data input / output circuit Qs01, Qs02 shared MOS (for left array) Qs11, Qs12 shared MOS (for right array)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8728-4M H01L 27/10 325 V

Claims (3)

[Claims] 1. In a semiconductor memory device in which a sense amplifier is provided for each data line pair and a main amplifier for detecting a level difference between the data line pairs is connectable via a Y-system switch, a common I / O line is re-connected. -Separate between the one for the light and the one for the write, and provide the switch MOSFET on the data line,
At the time of data reading, at least the sense amplifier is separated from the data line by the switch MOSFET, and after reading by the direct sense method, the switch MOSF
A semiconductor memory device characterized in that ET is turned on, a level difference of a data line is amplified by a sense amplifier, and rewriting is performed in a selected memory cell. 2. A switch M provided on the data line.
2. A sense amplifier, a write I / O, and a precharge circuit can be shared between two memory arrays by turning on and off the OSFET.
The semiconductor storage device described. 3. A switch M provided on the data line.
In a semiconductor memory device in which a sense amplifier and a precharge MOS can be shared between two memory arrays by turning on and off the OSFET, the switch MOSFETs on both sides are turned on during the precharge period of the data line to read. Sometimes, the switch MOSFETs on both sides are once turned off, and after direct sensing, the switch MOSFETs of the memory array on the selected side are turned on by a signal having a level higher than the power supply voltage to perform rewriting. Alternatively, the semiconductor memory device according to claim 2.