JPH0556065A - Switch synchronization changeover system - Google Patents

Abstract

(57) [Abstract] [Purpose] A switch switching method of an ATM switch having a duplex configuration is intended to synchronize and switch the cell flow of the duplex switch at the time of regular switching. [Structure] First and second switches 1 configured in duplex
In the ATM switch that periodically switches a and 1b in the selection unit 2 provided on the outgoing line 4 side, the cells input from the incoming line 3 are monitored at the time of regular switching, and a preset test cell is used instead of the empty cell. For inserting test cell 5 for inserting
Between the switches 1a and 1b and the selector 2
First and second test cell extraction units 6a and 6b for monitoring the cells output from b and extracting the test cells, and the test cell extraction unit
The input times of the test cells extracted by 6a and 6b are compared, and if there is a difference in the input times, control is performed to delay the cell output to the switch that outputs the input test cell earlier, and both test cells are synchronized. The cell flow synchronization control unit 7 is configured to control switching of the selection unit 2 when input.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch switching system for an ATM switch having a duplex structure, and more particularly to a switch switching system for an ATM switch which regularly switches and uses a switch having a duplex structure.

Recently, ATM (Asynchronous Transfer Mod)
e, Asynchronous transfer mode) type exchanges are rapidly being put into practical use. The ATM switch uses a switch called a cell for switching fixed length packets (usually 53 bytes) as a unit (hereinafter, such a switch is referred to as an ATM switch), but the ATM switch is redundant to improve reliability. It is common to adopt a (duplex) configuration. In addition, it is often the case that such a switch having a duplex configuration is not only switched at the time of a failure, but also periodically (for example, once a day) to always confirm that there is no potential failure. ..

In the conventional time-division type circuit switch, when switching the switches of the duplex configuration, the phases of the bit level clock (for example, 2 MHz, 8 MHz, etc.) and the frame synchronization signal of 8 kHz match between the switches of both systems. If so, the switching between the switches can be executed without any interruption, and the problem of the synchronous switching is solved by providing the confounding of the clocks between the switches.

Similarly, in switching between ATM switches, it is possible to perform synchronization switching at the cell boundary by matching the bit-level clock with the cell frame synchronization indicating the cell boundary.

On the other hand, an ATM switch generally has a structure in which a plurality of buffer memories for waiting are arranged in a matrix. As this buffer memory, a memory that outputs in the order of input in a FIFO (First-In First-Out) format is usually used. However, since the throughput of the switch is high (for example, 155 MHz or more), the buffer memory There may be a difference in the timing at which the same cell is temporarily stored in the buffer memories of the switches of both systems due to characteristics such as variation in delay time.
For this reason, it is not guaranteed that cells input at the input line portion at the same time are output simultaneously from the output line portions of the switches of the duplicated systems.

As described above, in the conventional ATM switch, the synchronization of the cell flows is not guaranteed, so that the cells may be duplicated or dropped when switching is performed. For this reason, there is a need for a switch-synchronous switching method in which cells do not overlap or drop during regular switching.

[0007]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional duplex switch. In FIG. 3, cells are multiplexed and input to the incoming line 23, but the input cell is the 0-system switch 21.
It is input to a and the 1st system switch 21b at the same time. These cells are FIFOs in the switches 21a and 21b, respectively.
The data is temporarily stored in the buffer memories 28a and 28b of the format and then output from the respective output lines.

0-system switch 21a and 1-system switch 21b
The cells output from the output line of are input to the selection unit 22,
In the selection unit 22, only one input is output to the output line 24. For example, 0 system switch 21
When a is the operating system and the 1-system switch 21b is set as the standby system, the cells output from the 0-system switch 21a are sent to the outgoing line 24 via the selection unit 22.

However, in the configuration as shown in FIG. 3, for example, the 0-system switch 21a is not normally operated as an operating system, but is normally operated so as to be alternately an operating system. .. This is because if one system is not always used as a standby system for a long period of time, it may not operate satisfactorily when switching due to a failure, etc. In addition, it is common to switch the switch periodically for operation. This regular switching is executed, for example, by switching the selection unit 22 once or more a day.

However, the buffer memory 28 in FIG.
The a and 28b are not limited to those shown in the figure, but are generally configured in multiple stages, and since the ATM switch has a high throughput, there is a difference in the characteristics of the constituent elements inside the switch, and so on from the incoming line 23 at the same time. The input cells are not always output from the output line of the switch 21a and the output line of the switch 21b at the same time. That is, even if the output of the duplexed ATM switch is synchronized with the bit level clock and the cell frame, the synchronization of the cell flow is not guaranteed.

Therefore, in the configuration of FIG. 3, even if the selection unit 24 is switched in synchronization with the bit-level clock and the cell frame, cells may be duplicated or dropped at the time of switching.

[0012]

DISCLOSURE OF THE INVENTION In the prior art,
Even if the bit-level clock and the cell frame are synchronized between the switches of the duplex configuration, the cell flow is not guaranteed to be synchronized, so that there is a possibility that cells may be duplicated or dropped during periodic switching.

An object of the present invention is to prevent quality deterioration due to cell duplication or cell drop by synchronizing and switching the cell flows of the duplicated switches at the time of regular switching.

[0014]

FIG. 1 is a basic block diagram of the present invention. In the figure, 3 is an input line into which multiplexed cells are input, 4 is an output line from which cells exchanged in an ATM switch are output, 1a and 1b are duplicated first and second switches, and 2 is First and second switches 1a, 1b
Is a selection unit for selecting one of the outputs of and output to the output line 4.

Reference numeral 5 is the first and second switches 1a, 1
When an instruction to execute the periodical switching of b is input, the cells input to the first and second switches 1a and 1b from the incoming line 3 are monitored, and when an empty cell is detected, the empty cell Instead, it is a test cell insertion means for inserting a preset test cell.

6a and 6b are provided between the first and second switches 1a and 1b and the selection unit 3, respectively.
And first and second test cell extracting means for monitoring the cells output from the second switches 1a and 1b and extracting the test cells.

Numeral 7 inputs the test cells respectively extracted by the first and second test cell extracting means 6a and 6b and compares the input times, and if there is a difference in the input times, the test cells input earlier. The output of the cell is controlled to be delayed by the switch which has output, and when both test cells are input in synchronization, control is performed to switch the selecting section 2 and the test cell is inserted into the test cell inserting means (5). Cell flow control means for controlling the insertion of the cell flow.

[0018]

In the configuration of FIG. 1, the switch 1a and the switch 1b have the same configuration (details are not shown), and one of them is an operating system,
The other operates as a standby system, but is periodically switched so that the operating system and the standby system alternate.

In FIG. 1, cells input from the incoming line 3 are input to the switches 1a and 1b, and are output to the outgoing lines corresponding to the destinations in the switches 1a and 1b, respectively. In this case, switch 1 from incoming line 3 at the same time
The cells input to a and 1b are output to the selection unit 2 from the corresponding outgoing lines of the switches 1a and 1b. However, when the switch 1a is set in the operating system, the selection unit 2 switches to the switch 1
Since the cells output from a are switched to be output to the output line 4, only the cells output from the switch 1a are output to the output line 4.

Switch 1 is switched from the above state by periodical switching.
When switching b to the operating system, an instruction to execute periodical switching is input to the test cell inserting means 5 from an operation unit (not shown). As a result, the test cell inserting means 5 causes the incoming line 3
The input cell is monitored, and when a vacant cell is detected, a preset test cell is inserted in place of the vacant cell so that it can be distinguished from a normal cell.

The inserted test cell is output to the output line through the first and second switches 1a and 1b, respectively, and input to the first and second test cell extracting means 6a and 6b. The first and second test cell extraction means 6a and 6b monitor the cells output from the first and second switches 1a and 1b, respectively, and when the test cell is detected, the cell is extracted to the cell flow control means 7. send.

The cell flow control means 7 compares the input times of the test cells input from the first and second test cell extracting means 6a and 6b, and if there is a difference in the input time, the test cell input earlier is selected. The output switch is controlled to delay the output switch. The test cell inserting means 5 continues to insert test cells even after the above control, and the first and second test cell extracting means 6a and 6b also continue to extract test cells.

The cell flow control means 7 inputs the test cells each time the first and second test cell extraction means 6a, 6b are extracted, compares the input times, and performs the same control as described above. As a result of repeating this control,
When the test cells are simultaneously input from the second test cell extraction means 6a and 6b, the cell flow control means 7 controls the selection section 2 to switch the outgoing lines of the switches 1a and 1b and causes the test cell insertion means 5 to operate. On the other hand, control to stop the insertion of the test cell is performed.

As a result, the switch switching is completed and the test cell insertion by the test cell inserting means 5 is stopped, but the above-mentioned switching is such that the simultaneously input test cells are simultaneously output from the duplicated switches 1a and 1b. That is, since cell flows are performed in a synchronized state, cells do not overlap or drop out.

[0025]

FIG. 2 is a block diagram of an embodiment of the present invention. In FIG. 2, the same objects as those in FIG. 1 are indicated by the same symbols. In the figure, 5 _{-1 to} 5 _-3 are the respective parts constituting the test cell insertion part 5,
_Reference numeral 5 _-1 is an empty cell detection unit, 5 _-2 is a test cell generation unit, and 5 _-3 is a selector (SEL1).

Further, 7 _-1a, 7 _-1b, 7 _-2 , 7 _-3 are respective parts constituting the cell flow control section 7, 7 _-1a, 7 _-1b are test cell input sections, and 7 _-2 is a test cell comparison section. The section _7-3 is a control section. 8
a, respectively 8b switch 1a, the buffer memory in 1b (BM), 9a, 9b is a control line controller 7 _-3 of cell flow control unit 7 for controlling the cell output timing of the buffer 8a, 8b, 10 control unit 7 _-3 control lines for controlling the switching of the selector (SEL2) constituting a selector, 11 is the control unit 7 _-3 of cell flow control unit 27 requests the stop of the test cell inserted into the test cell insertion unit 25 It is a control line.

Although FIG. 2 will be described below, the description overlapping with the operation of FIG. 1 will be omitted. In FIG.
The cell input from the incoming line 3 is input to the selector 5 _-3 via the empty cell detection unit 5 _-1 in the test cell insertion unit 5. Since the selector 5 _-3 is normally connected to input the cells input from the incoming line 3 to the switches 1a and 1b,
Each cell is input to the switches 1a and 1b.

The cells input to the switches 1a and 1b are temporarily stored in the buffer memories 8a and 8b, respectively, and then output to the output lines in the input order by the FIFO method. At this time, if the selector 2 is set to connect the outgoing line of the switch 1a to the outgoing line 4, the cells output from the switch 1a are sent to the outgoing line 4.

In the above-mentioned state, the regular switching time comes, and the selector 2 switches the output line of the switch 1b to the output line 4.
When a regular switching execution instruction for switching to connect to the test cell is issued, the instruction is input to the test cell insertion unit 5 from an operation unit (not shown) or the like, and the empty cell detection unit 5 _-1 is first input to the incoming line 3. The empty cells are detected from among the cells that exist.

The empty cell detector 5 _-1 requests to sending the test cell to the test cell generating unit _5-2 and detects the empty cell. A test cell is preset in the test cell generation unit _5-2 , but the test cell is, for example, a header part (not shown).
By storing a code different from a normal cell, it is possible to identify a test cell only by looking at the header part.

The test cell generator 5 _-2 is an empty cell detector 5 _-1.
In response to the request, the test cell is transmitted and the selector 5 _-3 is switched to output the test cell to the switches 1a and 1b. The empty cell detection unit _5-1 is provided with a buffer memory (not shown), and the cell sending timing is adjusted until the test cell can be sent by switching the selector _5-3 from the empty cell detection. A test cell is inserted in the cell portion and output. After sending the test cell, the selector 5 _-3 is restored and the cell from the incoming line 3 is sent to the switches 1a and 1b.

The test cell extraction units 6a and 6b monitor the cells sent to the outgoing lines of the switches 1a and 1b, respectively, and when the header unit detects the test cell, sends the test cell to the cell flow control unit 7. In the cell flow control unit 7, the test cell input units 7 _{-1a and} 7 _-1b receive the test cells and send them to the test cell comparison unit 7 _-2 .

In the test cell comparison unit 7 _-2 , the test cell input unit 7
_When test cells are simultaneously input from _{-1a and 7-1b} , a control signal is sent to the control line 10 to switch the selector 2 and the output line of the switch 1b is connected to the output line 4.

In the ATM switch, when cells input at the same time are not output at the same time by the switch having the duplex configuration, a time difference is generated in units of the frame period of the cell. In the test cell comparison unit 7 _-2 , the test cell input unit 7 _{-1a. ,} 7
_When no test cells are input at the same time from _-1b, time counting is started by a clock or the like from the time when one is input, and the time until the other test cell is input is counted.

As a result, the test cell comparison section 7 _-2 can detect how many frames of cells the time difference between the test cells of both systems is, but here, as a basic function, it is possible to determine whether or not the test cells are simultaneously input. In the case where they are not simultaneous, it is assumed that only the switch from which the test cell is input first can be identified.

Now, for example, assuming that the test cell is output before the switch 1a, the test cell comparing section 7 _-2 identifies this, and the control cell 9a sends the control cell to the control line 9a via the control section 7 _-3 . Send control information that delays cell transmission. This control information is input to the buffer 8a of the switch 1a, and the buffer 8a delays the temporarily stored cell by, for example, one cell frame and outputs the delayed cell.

Since the test cell inserting section 5 continues to insert the test cell, the test cell extracting section 6a, 6b continues the extraction of the test cell after the above control is performed, and the test cell comparing section 7 is the same as described above. Comparison of test cells is made at _-2 . This comparison is repeated until the test cells are simultaneously input from the test cell input units 7 _{-1a and} 7 _{-1b ,} and when it is detected that the test cells are input at the same time, the test cell comparison unit 7 _-2 is sent to the control unit 7 _-3 . Notifying that the test cells are synchronized, the control unit 7 _-3 controls the switching of the selector 2 via the control line 10.

At the same time, the control section _7-3 controls the test cell insertion section 5 to stop the insertion of the test cell through the control line 11, and completes the switch switching. As described above, in the configuration of FIG. 2, the selector 2 is switched after confirming that the test cells that are input at the same time are output simultaneously from the switches of both systems in the duplicated configuration, so that cells may overlap when switching. It does not fall off.

Although the embodiment of the present invention has been described above with reference to FIG. 2, FIG. 2 merely illustrates one embodiment of the present invention, and the configuration of the present invention is not limited to FIG. Needless to say. Moreover, it is easy to provide a function other than the functions described above with the configuration of FIG.

For example, in the above description, the test cell inserting section 5 continues to insert the test cell until the cell flow control section 7 controls the cell. However, when the empty cells are continuous, the test cell is inserted. Since the same test cell is continuously inserted, even if the same test cell is output from the switch 1a and the switch 1b with a time difference of, for example, one cell or more, the cell flow control unit 7 may erroneously determine that they are input simultaneously.

For this, for example, the test cell insertion part 5
When inserting a test cell, a method may be considered in which the header part or the data part of the test cell to be inserted includes the information that can identify the insertion order after receiving the instruction to execute the regular switching. In this method, when the test cell is input from the test cell extracting units 6a and 6b, the cell flow control unit 7 checks whether or not there is a difference in the input time between the test cells having the same insertion order. This makes it possible to easily prevent the erroneous determination of synchronization as described above.

As another method, the test cell insertion part 5
It is conceivable to insert the test cell only once when the regular switching execution instruction is received. In this case, when the cell flow control unit 7 that inputs the test cell through the test cell extraction units 6a and 6b determines that there is a difference in the input timing, the test cell insertion unit 5 is tested via the control line 11. Request additional insertion of cells. Also, the test cell insertion unit 5 inserts one test cell each time a test cell insertion request is received. By this method, it is possible to easily prevent erroneous determination of synchronization due to different test cells, but unlike this method, there is no need to confirm the insertion order of test cells.

In the configuration of FIG. 2, the method of inserting the test cell from the test cell inserting section 5 and extracting the test cell by the test cell extracting sections 6a and 6b at the outgoing lines of the switches 1a and 1b is the switch 1a, It has a lot in common with the continuity test function of 1b. Therefore, the present invention can be partially shared with the continuity test function of the ATM switch, and the present invention can be economically realized by sharing the continuity test function. The present invention does not exclude sharing with the continuity test function.

[0044]

As described above, according to the present invention,
At the time of periodic switching in an ATM switch that regularly switches and uses redundant switches, it is necessary to confirm that simultaneously input cells are output from both switches at the same time. The cells do not overlap or drop out, and a significant effect is exerted in preventing deterioration of cell quality at the time of periodic switching of the switch having such a duplex configuration.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a prior art duplex switch configuration diagram.

[Explanation of symbols]

 1a, 1b Switch 2 Selector 3 Incoming line 4 Outgoing line 5 Test cell inserting means 6a, 6b Test cell extracting means 7 Cell flow control means

Claims (1)

[Claims] 1. An ATM switching system in which the first and second switches (1a, 1b) configured in a duplex configuration are periodically switched and used in a selection section (2) provided on the outgoing line (4) side, When an instruction to execute switching is input, the cell input from the incoming line (3) is monitored, and when a vacant cell is detected, a preset test cell is inserted instead of the vacant cell. Means (5), the first and second switches (1a, 1b), and the selection unit (2)
Between the first and second switches (1a, 1b) respectively
The first and second test cell extracting means (6a, 6b) for monitoring the cells output by the test cell and extracting the test cell, and the first and second test cell extracting means (6a, 6b) for extracting The input test cells are input and the input times are compared, and if there is a difference in the input times, the control that delays the cell output is performed for the switch that outputs the input test cell earlier,
When both test cells are input in synchronization, the selection section (2)
And control means for switching the test cell insertion means
The cell flow control means (7) that controls the insertion of the test cell to (5) is provided, and the cell flows are synchronized and switched when the redundant switches (1a, 1b) are periodically switched. Switch-synchronized switching method, which prevents overlapping and dropping of cells during switching.