JPH0554691A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve a defective product relief rate without increasing the number of redundant memory cells provided in a semiconductor storage device. CONSTITUTION:Redundant memory cells MCR1 to MCR4 are placed so as to commonly use two sets of data input/output lines I01 and the inverse of I01 and I02 and the inverse of I02. Switching transistors QR1 to QR4 connect data lines DR1, the inverse of DR1, DR2, the inverse of DR2 to one side of the data input output lines I01 and the inverse of I01 and switching transistors QR1' to QR4' connect the data lines DR1 to the inverse of DR2 to the other side of the data input output lines I02 and the inverse of I02. By switching these two sets of switching transistors QR1 to QR4 and QR1' to QR4', plural defective memory cells are replaced to redundant memory cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a dynamic random access memory device having redundant memory cells.

[0002]

2. Description of the Related Art In general, semiconductor memory devices, especially one-transistor type dynamic random access memory devices, have come to have redundant memory cells provided on a semiconductor substrate as the number of memory elements increases. The purpose thereof is to replace a defective memory cell with a redundant memory cell and relieve a semiconductor memory device, which should be originally a defective product, as one having a function equivalent to that of a non-defective product.

FIG. 2 is a plan view showing an arrangement of a one-transistor type dynamic random access memory device having such a redundant memory cell. In FIG. 2, memory cell array regions 1a, in which memory cells are arranged in rows and columns,
Redundant memory cell array regions 2a to 2 so as to surround 1d.
d, sense amplifier area 3 is a to 3d, X decoder area 5
a to 5d and Y decoder regions 4a and 4b are provided. Further, outside these areas, a peripheral circuit area in which circuits for generating various control signals and bonding pads 6a-6b are arranged is provided.

In FIG. 2, four memory cell array regions 1a are provided.
Although ~ 1d is arranged, it is not limited to 4 actually,
In some cases, 8 or 16 are arranged.

FIG. 3 is a circuit diagram specifically showing the area A surrounded by the broken line in FIG. In FIG. 3, the memory cell MC1
1, MC12, ..., MC41, MC42 are memory cells arranged in 1a of the memory cell array region. MCR1, M
CR2, MCR3, MCR4 are redundant memory cell array regions 20
And redundant memory cells arranged inside.

Now, focusing on the memory cell MC11 in the memory cell region 1a in FIG. 3, the case of reading the data in the memory cell MC11 will be described. First, the X decoder 5a selectively activates the word line WL1. Word line W
Since memory cells MC11, MC21, MC31, MC41 and redundant memory cells MCR1, MCR3 are connected to L1,
Data line D for each data connected to each
Read to 1, D2, ..., DR2.

Next, the peripheral circuit T sense amplifiers SA1 and SA
2, ..., Generate signals for activating SA5, SA6,
Activated sense amplifiers SA1, SA2, ..., SA
5, SA6 amplifies the read data.

Then, the switching transistors Q1 and Q12 are operated by the selection signal φ1 to read the data amplified by the sense amplifier SA1 to the complementary data input / output lines IO1 and IO1 (overline).

The data read to the data input / output lines IO1 and IO1 (overline) is amplified by an amplifier circuit provided in the peripheral circuit area and then output to a bonding pad. The selection signal .phi.1 is a signal that is selectively activated in response to an externally designated address, and its generation circuit is provided in the Y decoders 4a and 4b regions. In addition, two sets of data input / output lines complementary to each other (IO
1, IO1 (overline) and IO2, IO2 (overline)) are provided because it is necessary to provide the selection signal φ1 generation circuit for each data line pair because the area on the layout increases. One selection signal circuit is provided for each line pair, and two bits are simultaneously used for data input / output lines IO1, IO1 (overline) and IO.
2, read to IO2 (overline), and further 2 externally
This is because the configuration is such that one of the bits is selected.

Further, when writing data, the data is written to the memory cell MC11 by a route opposite to that of the previous reading.

Next, the case of replacing the defective memory cell of the semiconductor memory device shown in FIG. 3 with a redundant memory cell will be described. In the following description, it is assumed that the memory cell MC11 becomes defective. At this time, when the structure of the internal circuit is changed by means of blowing a fuse connected to the selection signal φR and the word line WL1 is activated and data is read from the defective memory cell MC11, the selection signal φ1 Instead, the selection signal φR is activated so that the data is read to the data line DR1 of the redundant memory cell MCR1.

As described above, when the defective memory cell is in the memory cell array region 1a, the redundant memory cells MCR1 and MCR are provided.
R2, MCR3 and MCR4 are used. By replacing a defective memory cell with a redundant memory cell by such a method, the entire semiconductor memory device becomes a defective product, which can be relieved.

The same applies even when the numbers of input / output data lines, memory cells, redundant memory cells, word lines, data lines, sense amplifiers, switching transistors, and selection signals in FIG. 3 change.

[0014]

However, in the conventional one-transistor type dynamic random access memory device described above, if the number of defective memory cells increases, the redundant memory cells become insufficient, and even if replacement is performed, it cannot be repaired as a good product. There was a problem.

For example, the memory cells MC11 and MC31 of FIG.
If one of the defective memory cells is defective, one of them can be replaced with the redundant memory cell MCR1 to be relieved as a non-defective memory cell, but the other defective memory cell has no replaceable redundant memory cell and two or more defective memory cells are generated. Then, eventually, the semiconductor memory device cannot be repaired as a good product.

In order to solve such a problem, the number of redundant memory cells may be increased so that all of them can be replaced with redundant memory cells even if the number of defective memory cells increases. However, increasing the number of redundant memory cells leads to an increase in the area of the pellet, and therefore the redundant memory cells cannot be increased to a sufficient number.

[0017]

SUMMARY OF THE INVENTION The gist of the present invention is to provide a plurality of memory cells, a plurality of data lines connected to the plurality of memory cells, a plurality of redundant memory cells, and a plurality of redundant memory cells. A plurality of redundant data lines, a plurality of input / output data lines, a plurality of data lines, and a first switching transistor for connecting each of the plurality of redundant data lines to one of the plurality of input / output data lines. In the semiconductor memory device including, each of the redundant data lines is
That is, a second switching transistor connected to an input / output data line different from the input / output data line connected to the first switching transistor is provided.

[0018]

When a plurality of defective memory cells occur in the memory cell, the data is replaced with the plurality of redundant memory cells, and the data read from the redundant memory cell is passed through either the first or second switching transistor. Is transferred to the input / output data line of.

[0019]

Embodiments of the present invention will now be described with reference to the drawings. The parts having the same functions as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The difference from the conventional one-transistor type dynamic random access memory device shown in FIG. 3 is that the data lines (DR1, DR1 (overline); DR2, connected to the redundant memory cells (MCR1, MCR2; MCR3, MCR4); DR (over line) and data input / output lines (IO1, IO1 (over line); IO
2 to IO2 (overline)) and another switching transistor (QR1 ', QR2'; QR3 ', in addition to the switching transistors (QR1, QR2; QR3, QR4) provided between
QR4 ') to provide another data input / output line (IO2, IO2;
IO1 and IO1 (overline)) can be connected.

With this structure, the memory cell MC11 can be replaced with the redundant memory cell MCR1 and the memory cell MC31 can be replaced with the redundant memory cell MCR3.

That is, when the defective memory cell MC11 is selected, instead of activating the selection signal φ1, the selection signal φR1 is activated to select the redundant memory cell MCR1.
When selecting the defective memory cell MC31, the selection signal φ
Instead of activating 2, the selection signal φR4 may be activated to select the redundant memory cell MCR3. In this way, even if two defective memory cells occur, they can all be relieved.

In the embodiment shown in FIG. 1, the switching transistors QR1 ', QR2', QR3 ', QR4' and the selection signals .phi.R2, .phi.R3, .phi.R4 are increased, but the redundant memory cells are located at the end of the memory cell array region. Because it is provided in the section,
Switching transistors QR1 ', QR2', QR3 ', Q
Adding R4 'can be done easily. The selection signal generating circuit related to the redundant memory cells is generally provided in the peripheral circuit area outside the memory cell array areas 1a to 1d and the decoder areas 5a to 5d, 4a and 4b shown in FIG. , ΦR3, φR4 can be easily added. Therefore, substantially the same effect can be achieved with an increase in the pellet area which is smaller than the case where the number of redundant memory cells is simply increased.

FIG. 4 is a plan view showing a second embodiment of the present invention. In FIG. 4, the memory cell array area is divided into two (for example, 1a and 1a ′ in the figure), and the data in one of the memory cell array areas 1a ′ to 1d ′ in the figure is read and written from the upper side in the figure and the other memory cell array is shown. Area 1a-1d
The data inside is read and written from the lower side in the figure. Such a configuration is adopted in a semiconductor memory device that simultaneously reads and writes 4-bit or 8-bit data when bonding pads used for reading and writing data are arranged at both ends across a memory cell array region. This is because the arrangement of circuits becomes easy from the viewpoint of data flow. The redundant memory cell array regions 2a to 2h are divided into two memory cell array regions 1a,
It is provided at the boundary between 1a 'to 1d, 1d'.

FIG. 5 is a block diagram more specifically showing the region B surrounded by the wiring of the semiconductor memory device shown in FIG. The components corresponding to those in the first embodiment are designated by the same reference numerals. The data line DR1 connected to the redundant memory cell MCR1 and the complementary data line DR1 (overline) are connected to the first data input / output line IO via the first switching transistors QR1 and QR2.
1 and IO1 (overline), and a second switching transistor QR1 ', QR2'
Are connected to the data input / output lines IO2 and IO2 (overline). In addition, the first data input / output lines IO1 and IO1 (overline) are provided on one side 1 of the memory cell array region divided into two.
Used for reading and writing data in a '. The second data input / output lines IO2 and IO2 (overline) are used for reading and writing data in the other side 1a of the divided memory cell array region.

In the semiconductor memory device according to the second embodiment, when the upper two memory cells MC11 and MC21 are defective memory cells, the selection signals φR1 and φR1 are generated.
By using R4, the redundant memory cells MCR1 and MCR3 can be replaced. Further, even when the memory cell MC11 on the upper side and the memory cell MC51 in the memory cell array region on the lower side become defective, the redundant memory cells MCR1 and MCR3 can be replaced by using the selection signals φR1 and φR3.

As described above, in the second embodiment, the redundant memory cells corresponding to the memory cell regions divided into two are shared, so that even if the number of defective memory cells increases, the semiconductor memory device is regarded as a good product. I can salvage. In the above description of the embodiment, the case where two data input / output lines are connected to one data line via the switching transistor has been described, but one data line is connected to the switching transistor via the switching transistor. The number of data input / output lines connected is not limited to two, and four or eight data input / output lines may be connected. It is apparent that the present invention is not limited to the one-transistor type dynamic memory as the crotch semiconductor memory device, and that the present invention is applied to other types of semiconductor memory devices.

[0028]

As described above, according to the present invention, even if a plurality of memory cells are defective, the defective memory cells can be replaced with redundant memory cells, and the semiconductor memory device can be manufactured without increasing the pellet area. The effect of being able to relieve

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment.

FIG. 2 is a plan view showing a conventional example.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a plan view showing a second embodiment.

FIG. 5 is a block diagram showing a second embodiment.

[Explanation of symbols]

IO1, IO1 (overline), IO2, IO2 (overline) I / O data lines MC11, MC12, ..., MC41, MC42 Memory cells MCR1, MCR2, MCR3, MCR4 Redundant memory cells WL1, WL2 Word lines SA1, SA2 ,, SA5, SA6 sense amplifiers Q11, Q12, ..., QR4, QR5 switching transistors φ1, φ2, φR1, ..., φR4 selection signals 1a, 1b, 1c, 1d memory cell array regions 2a, 2b, 2c, 2d Redundant memory cell array area 3a, 3b, 3c, 3d Sense amplifier area 4a, 4b Y decoder area 5a, 5b, 5c, 5d X decoder area

Claims (2)

[Claims] 1. A plurality of memory cells, a plurality of data lines connected to the plurality of memory cells, a plurality of redundant memory cells, and a plurality of redundant data lines connected to the plurality of redundant memory cells, A semiconductor memory device comprising: a plurality of input / output data lines; and a first switching transistor connecting each of the plurality of data lines and the plurality of redundant data lines to one of the plurality of input / output data lines, A semiconductor memory device comprising: a second switching transistor for connecting each of the redundant data lines to an input / output data line different from the input / output data line connected to the first switching transistor. 2. The plurality of memory cells are divided into a first memory cell group and a second memory cell group, and the redundant memory cell is arranged between the first memory cell group and the second memory cell group. The plurality of input / output data lines are the first input / output data line and the second input / output data line assigned to the first memory cell group.
The second switching transistor is divided into the second input / output data line assigned to the memory cell group, and the second switching transistor is connected to the second input / output data line when the first switching transistor is connected to the first input / output data line. 2. The semiconductor memory device according to claim 1, which is connected to.