JPH0553808A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To execute a processing without fail even when an instruction having the arbitrary number of instruction codes is inputted. CONSTITUTION:This unit is equipped with a descripter number register 11 to designate a number (n) of descripters required for storing entire instruction codes C1-Cn of the inputted instruction. When there are any excess ALU exceeding the number of descripters instructed by the descripter number register 11, this instruction is made invalid. When the number of descripters is lacked, all the instruction codes are divided into plural parts and processed by using the ALU plural times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit for performing high speed arithmetic processing using a plurality of ALUs (logical operation units).

[0002]

2. Description of the Related Art A general microprocessor is provided with one ALU, which decodes an input instruction,
The data stored in the designated register is subjected to arithmetic processing according to the instruction and output. However, for example, VLIW (Very long instru
2. Description of the Related Art In some arithmetic processing devices that perform data processing of a ction word) architecture, a plurality of ALUs are provided and each ALU decodes and processes an instruction consisting of a plurality of instruction codes at once. FIG. 2 shows a block diagram of such a conventional arithmetic processing unit. In FIG. 2, this device has n
Instructions M1, M2, ... Ms composed of individual instruction codes are sequentially input, decoded and processed. These instructions are stored in the main storage device or the like. The main memory device is connected to the instruction bus 10. The instruction bus 10 has n
Descriptors D1, D2 ... Dn are connected. These descriptors D1, D2 ... Dn
Are connected to ALU1, ALU2 ... ALUn, respectively. The arithmetic processing device having the above-described configuration is, for example, the instruction M1.
Each of the instruction codes C1 to Cn configuring the above is stored in the descriptors D1 to Dn one by one, and the instruction codes are decoded by the corresponding ALU1 to ALUn connected to the descriptors and the arithmetic processing is executed. With such a configuration, complex arithmetic processing can be performed at high speed in the same time.

[0003]

By the way, in the arithmetic processing unit of this type, the performance is improved by increasing the number of descriptors and increasing the number of instruction codes that can be decoded at one time. Therefore, the number of descriptors has been gradually increased while maintaining the compatibility of instruction codes, and the performance has been improved. Therefore, in practice, arithmetic processing devices with various descriptor numbers have been put to practical use. However, in the arithmetic processing device having the above-described configuration, even if an instruction used in an arithmetic processing device with a small number of descriptors is directly input to an arithmetic processing device with a large number of descriptors, it is appropriate due to an instruction length mismatch. Arithmetic processing cannot be executed. Therefore, in order to match the number of descriptors in advance,
Preprocessing such as joining a new instruction code to the instruction code was necessary. On the other hand, if an instruction used in a processor with a large number of descriptors is input to a processor with a small number of descriptors, processing cannot be performed and there is a problem in that there is no practical compatibility. It was
The present invention has been made in view of the above points, and provides an arithmetic processing device capable of flexibly coping with an arithmetic processing device having a large number of descriptors and an arithmetic processing device having a small number of descriptors regardless of the configuration of an input instruction. The purpose is to do.

[0004]

According to a first aspect of the present invention, a plurality of ALUs, a plurality of descriptors for storing instructions to be processed by the ALUs, and a plurality of instruction codes for inputting the instructions are input, When one instruction code is stored in one descriptor, the descriptor register that specifies the number of descriptors required to store all instruction codes and the ALU that processes the instruction code are specified, and the instruction of the descriptor register is specified. The arithmetic processing device is characterized by invalidating the output of the surplus ALU exceeding the number of descriptors to be processed. According to a second aspect of the present invention, a plurality of ALUs, a plurality of descriptors for storing instructions to be processed by the ALUs, and the input instruction are made up of a plurality of instruction codes, and one instruction code is assigned to one descriptor. When stored, the descriptor register that specifies the number of descriptors required to store all instruction codes, the all instruction code is divided into a plurality of instruction codes, and the instruction code of the number of descriptors that the descriptor register indicates is stored in the ALU. It is an arithmetic processing unit characterized by using and processing a plurality of times.

[0005]

This device is provided with a descriptor number register 11 for designating the number of descriptors required to store all the instruction codes of the input instruction. If there is a surplus ALU exceeding the number of descriptors indicated by the descriptor number register 11, it is invalidated, and if the number of descriptors is insufficient, all instruction codes are divided into a plurality of ALUs and the ALU is used a plurality of times. To process. As a result, even if an instruction having an arbitrary instruction code number is input, the processing can be executed without error.

[0006]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of an arithmetic processing unit of the first invention of the present invention. This device has the instruction code C
Instructions M1 to Ms composed of 1, C2 ... Cn are sequentially processed. These instructions are stored in memory and read via instruction bus 10. Here, the instruction bus 10 is provided with descriptors D1 to Dm that store the above instruction codes one by one and supply the instruction codes to m ALU1 to ALUm, respectively. Further, in the present invention, the descriptor number register 11 is also connected to the instruction bus 10. The descriptor number register 11 is for designating the number of descriptors required to store the instruction codes forming the instructions M1 to Ms when each instruction code is stored in one descriptor. In the example of FIG. 1, for example, the instruction M1 is composed of n instruction codes C1 to Cn, so that the numerical value n is stored in the descriptor number register 11. Further, in this embodiment, the number n of the instruction codes C1 to Cn forming the instruction M1 is smaller than the number m of descriptors provided in the device.

In the above-mentioned device, first, the numerical value n is stored in the descriptor number register 11 before processing the instruction M1 consisting of n instruction codes. By storing the descriptor number n, the descriptors D1 to Dn among the descriptors D1 to Dm provided in the device and the ALU1 to ALUm connected to the descriptors D1 to Dn are stored.
And ALU1 to ALUn are operated effectively. That is, the contents of n or more descriptors are invalid, and the output of the ALU connected thereto is also invalid. Such a configuration can be realized by, for example, fixing the write strobe signal to an unwritable state for an unnecessary descriptor. It is assumed that such a control signal is supplied from the descriptor number register 11 to a predetermined descriptor. As a modification, an instruction not to perform arithmetic processing may be stored in a descriptor of an unnecessary ALU. In this case, it is necessary to generate and store this type of instruction.

FIG. 3 shows a block diagram of a second embodiment of the arithmetic processing unit of the present invention. The overall configuration of the device shown in the figure is almost the same as that shown in FIG. However, here
The instruction code C whose descriptor constitutes the instruction M1
The number k is smaller than the number n of 1 to Cn. Even in such a case, the descriptor number register 11
Stores the number n of instruction codes that make up an instruction,
The arithmetic processing can be performed by executing the following processing. FIG. 4 shows an operation explanatory diagram of the second invention. In the second invention, first of the n instruction codes, the first k instruction codes C1, C2, ...
Store in k. This state is shown in FIG. In such a state, the first arithmetic processing is executed. The calculation processing result is written in a predetermined address of a memory (not shown). Next, when this operation is completed, the instruction code after the n-th instruction of the instruction M1 is fetched and stored in the descriptor. That is, the instruction codes Ck + 1 ... Cn are stored in the descriptors D1 ... Dn-k. In this case, the number of instruction codes is smaller than the number of descriptors. Therefore, as described in the first aspect of the invention, the excessive descriptors invalidate their output.

In this way, the second processing is performed and the output is stored in a predetermined memory. At the stage where these processes are completed, the same result as the result obtained by using the arithmetic processing device having n descriptors from the beginning is obtained. Therefore, according to the second invention, even when an instruction longer than the actual number of descriptors is input, this can be smoothly processed. According to the above configuration, the VL
With regard to the processor of the IW architecture, the instruction code compatibility is maintained between devices having different descriptor numbers, that is, ALU numbers, and the necessary processing can be executed without changing the instruction configuration. Therefore, for example, an instruction used in a device with a small number of descriptors can be directly processed by a high-performance device with a large number of descriptors, and if high-speed processing is required, it is included in the instruction as usual. The number of instruction codes to be generated may be increased so that the prescribed performance is exhibited.

[0010]

The arithmetic processing unit of the present invention as invented above is
In a processor having a VLIW architecture including a plurality of ALUs, when one instruction code of an input instruction is stored in one descriptor, the descriptor number required for storing all instruction codes is previously stored in the descriptor number register. Store the surplus A that exceeds the number of descriptors
The output of the LU is invalidated, or the instruction code is divided into a plurality of pieces and the ALU is used a plurality of times to perform the processing, so that the compatibility of the instruction code between different devices can be maintained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an arithmetic processing unit of the first invention of the present invention.

FIG. 2 is a block diagram showing a conventional arithmetic processing unit.

FIG. 3 is a block diagram showing an embodiment of an arithmetic processing unit of the second invention of the present invention.

FIG. 4 is an operation explanatory diagram of the second invention of the present invention.

[Explanation of symbols]

 C1 to Cn instruction code D1 to Dn descriptor 11 descriptor number register

Claims (2)

[Claims] 1. A plurality of ALUs, a plurality of descriptors for storing instructions to be processed by the ALUs, and a plurality of instruction codes for inputting the instructions to be input, wherein one instruction code is stored in one descriptor. Then, the descriptor number register that specifies the number of descriptors required to store all the instruction codes, and the ALU that processes the instruction code are specified.
An arithmetic processing unit, which invalidates the output of a surplus ALU exceeding the number of descriptors designated by the descriptor number register. 2. A plurality of ALUs, a plurality of descriptors for storing instructions to be processed by the ALUs, and a plurality of instruction codes for inputting the instructions, wherein one instruction code is stored in one descriptor. In this case, the descriptor number register that specifies the number of descriptors required to store all instruction codes, the all instruction code is divided into a plurality, and the instruction code of the number of descriptors that the descriptor number register indicates is stored in the ALU. An arithmetic processing device characterized by being used a plurality of times for processing.