JPH0551174B2 - - Google Patents
Info
- Publication number
- JPH0551174B2 JPH0551174B2 JP60131594A JP13159485A JPH0551174B2 JP H0551174 B2 JPH0551174 B2 JP H0551174B2 JP 60131594 A JP60131594 A JP 60131594A JP 13159485 A JP13159485 A JP 13159485A JP H0551174 B2 JPH0551174 B2 JP H0551174B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- ion
- angle
- etching rate
- ion beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005530 etching Methods 0.000 claims description 31
- 239000010408 film Substances 0.000 claims description 16
- 238000010884 ion-beam technique Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 238000003801 milling Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔概要〕
イオン・ビーム・ミリングによるエツチ・バツ
クで、表面の平坦化を行なう方法であつて、イオ
ン・ビームの入射角度を段差部における基板に平
行な方向のエツチングを速度が平坦部の深さ方向
エツチング速度に比べて大きくなる角度に設定す
る。それにより、少ない工程で容易に平坦化がで
きる。[Detailed Description of the Invention] [Summary] This is a method for flattening a surface by etching back using ion beam milling, in which the incident angle of the ion beam is changed so that etching is performed in a direction parallel to the substrate at the stepped portion. The etching speed is set at an angle that is higher than the etching speed in the depth direction of the flat portion. Thereby, planarization can be easily achieved with fewer steps.
本発明は、半導体素子の製造工程における表面
平坦化技術としてのイオン・ビーム・ミリングに
よるエツチ・バツク法に関するものである。
The present invention relates to an etchback method using ion beam milling as a surface planarization technique in the manufacturing process of semiconductor devices.
現在、半導体素子の高密度化、高速化のための
多層配線において、段差部における断線を防ぐた
め層間絶縁膜或は、配線金属の平坦化が必須の技
術とされている。平坦化の方法として従来行なわ
れているエツチ・バツク法、スパツタ・エツチ法
について説明する。
Currently, in multilayer wiring for increasing the density and speed of semiconductor devices, planarization of interlayer insulating films or wiring metals is considered to be an essential technique in order to prevent disconnections at stepped portions. The etch-back method and the sputter etch method, which are conventionally used as flattening methods, will be explained.
(1) エツチ・バツク法による平坦化例:第4図a
のように、絶縁膜11上に金属配線パタン12
による段差がある場合、例えば、絶縁膜として
SiO213をスパツタ堆積又はプラズマCVD法
により堆積させ、さらに、レジスト等14を塗
布し、レジストの流動性を利用してレジスト表
面を平坦化する(第4図b)。その後、例えば
CF4/O2プラズマにより、レジスト14とSiO2
13のエツチング速度が等しい条件でエツチン
グを行なう(第4図c)。以上の工程により、
凹領域を絶縁膜で埋めて、表面を平坦化するこ
とができる。しかし、この方法では、深い段差
を平坦化する場合、レジストによる表面の平坦
化が困難であること及びレジストと平坦化すべ
き材料のエツチング速度を等しくしなければな
らないという厳しい制限が課せられる等の問題
が生じる。(1) Example of flattening using the etch-back method: Figure 4a
A metal wiring pattern 12 is formed on the insulating film 11 as shown in FIG.
For example, if there is a difference in level due to
SiO 2 13 is deposited by sputter deposition or plasma CVD, and then a resist 14 is applied, and the resist surface is flattened using the fluidity of the resist (FIG. 4b). Then, for example
Resist 14 and SiO 2 are separated by CF 4 /O 2 plasma.
Etching is carried out under the condition that the etching speed of 13 is equal (FIG. 4c). Through the above process,
The surface can be flattened by filling the recessed region with an insulating film. However, when flattening a deep step, this method has problems such as the difficulty of flattening the surface with resist and the strict restriction that the etching speed of the resist and the material to be flattened must be equal. occurs.
(2) スパツタ・エツチングによる平坦化例:第5
図aのように絶縁膜21上に金属配線パタン2
2による段差がある場合、例えば絶縁膜として
SiO223をスパツタ堆積又はプラズマCVDT
法により堆積させる(第5図b)。その後表面
をArプラズマによりスパツタ・エツチングす
る。スパツタ効率の角度依存性から段差部の角
が選択的にエツチングされ、段差が穏やかにな
る(第5図c)。この方法では段差部の角を選
択的にエツチングするだけに止まり、十分な平
坦化とはならない。(2) Example of flattening by sputter etching: 5th
As shown in figure a, a metal wiring pattern 2 is formed on the insulating film 21.
If there is a step due to 2, for example, as an insulating film
Sputter deposition or plasma CVDT of SiO 2 23
(FIG. 5b). After that, the surface is sputter etched using Ar plasma. Because of the angular dependence of sputtering efficiency, the corners of the stepped portion are selectively etched, making the step gentle (FIG. 5c). This method only selectively etches the corners of the stepped portion and does not result in sufficient flattening.
上述のように、従来法では、深い段差の平坦化
が困難であつたり、エツチングの条件が厳しい、
或は、段差部の角を選択的にエツチングするにと
どまり、十分な平坦化ができない等、尚不十分で
あつた。
As mentioned above, with the conventional method, it is difficult to flatten deep steps, and the etching conditions are harsh.
Alternatively, the etching is still insufficient, such as selectively etching the corners of the stepped portions, and sufficient flattening cannot be achieved.
本発明は従来の問題点を解決するため、表面に
段差を有する基板の該表面に、該段差と同程度乃
至それ以上の膜厚を有する、イオン・ビーム・ミ
リングに対して、平坦な表面の深さ方向エツチン
グ速度が表面の法線とイオン入射方向のなす角度
の増加とともに単調減少する性質を有する物質と
してAuの薄膜を堆積する工程と、前記段差斜面
における前記基板に平行な方向へのエツチング速
度が平坦部の深さ方向エツチング速度に比べ大き
くなるような角度に、基板法線に対するイオン入
射角度を設定した前記イオン・ビーム・ミリング
により、前記薄膜をエツチ・バツクする工程とを
含むことを特徴とする。
In order to solve the conventional problems, the present invention has been proposed to perform ion beam milling on the surface of a substrate having a step on the surface, which has a film thickness comparable to or greater than the step. a step of depositing a thin film of Au as a material whose etching rate in the depth direction monotonically decreases as the angle between the surface normal and the ion incident direction increases; and etching in a direction parallel to the substrate on the stepped slope. etching back the thin film by the ion beam milling, with the ion beam milling setting the ion incidence angle with respect to the normal to the substrate at an angle such that the etching speed is higher than the etching speed in the depth direction of the flat portion; Features.
上記によれば、エツチング速度のイオン・ビー
ム入射角度依存性を利用し、表面の凸部を選択的
にエツチングし、表面を平坦化することができ
る。
According to the above, by utilizing the dependence of the etching rate on the ion beam incident angle, the convex portions of the surface can be selectively etched and the surface can be flattened.
イオン入射角度を第3図aのように、基板法線
に対する角度θで定義すると、一般にイオン・ビ
ーム・ミリングのエツチング速度のビーム入射角
度依存性は、例えばAuのように垂直入射(θ=
0)で最大となるもの(第3図b−31)と、例
えばSiのようにθ=40°〜60°で最大となるもの
(第3図b−32)とに大別される。いずれの場
合でもイオン入射角度θが60°以上ではエツチン
グ速度は入射角度の増大とともに減少し90°でゼ
ロとなる。したがつて、第2図に示すように段差
をもつ表面をイオン入射角度θでエツチ・バツク
する場合、段差斜面への入射角度ΘはΘ<θであ
り、エツチング速度のイオン・ビーム入射角度依
存性と段差形状により段差斜面のエツチング速度
R(Θ)が平坦部でのエツチング速度R(θ)に比
べ大きくなるθが存在する。この入射角度でのエ
ツチ・バツクにより凸部の薄膜を選択的にエツチ
ングすることができる(以下斜めイオン・ビー
ム・ミリングと呼ぶ)。 If the ion incidence angle is defined as the angle θ with respect to the substrate normal, as shown in Figure 3a, then the dependence of the etching rate in ion beam milling on the beam incidence angle is generally determined by the normal incidence (θ=
0) (Fig. 3 b-31) and those such as Si, which reach a maximum at θ = 40° to 60° (Fig. 3 b-32). In any case, when the ion incidence angle θ is 60° or more, the etching rate decreases as the incidence angle increases and becomes zero at 90°. Therefore, when etching back a surface with steps at an ion incidence angle θ as shown in Figure 2, the incidence angle Θ on the step slope is Θ<θ, and the etching rate depends on the ion beam incidence angle. Depending on the nature and shape of the step, there is a value θ at which the etching rate R(Θ) on the stepped slope is greater than the etching rate R(θ) on the flat portion. Etching back at this angle of incidence makes it possible to selectively etch the thin film on the convex portion (hereinafter referred to as oblique ion beam milling).
本発明の実施例として、幅1μm、厚さ0.3μmの
SiO2膜パタンから成る表面に段差を有する基板
の表面の凹領域のみに、段差と同程度乃至それ以
上の膜厚を有する、イオン・ビーム・ミリングに
対して、第2図および第3図により説明したよう
に、平坦な表面の深さ方向エツチング速度が表面
の法線とイオン入射方向のなす角度の増加ととも
に単調減少する性質を有する物質としてAuを残
し、表面を平坦化する場合を第1図に示す。上記
SiO2膜パタン51から成る凹凸表面全面にAu5
2を例えばスパツタ堆積法により0.4μm堆積する
(第1図a)。その後例えば約70°のイオン入射角
度をもつイオン・ビーム・ミリング(イオン・ビ
ーム53)によりエツチ・バツクを行なう。この
時、段差斜面のエツチング速度は平坦部のエツチ
ング速度に比べ約5倍であり、凸部のAuを選択
的にエツチングすることができる(第1図b)。
上述エツチ・バツクをSiO2膜が露出するまで行
なうことにより、SiO2パタンの凹領域のみにAu
を残し、表面は平坦化される(第1図c)。
As an example of the present invention, a width of 1 μm and a thickness of 0.3 μm is shown.
For ion beam milling, which has a film thickness similar to or greater than the step only in the concave area of the surface of a substrate consisting of a SiO 2 film pattern with a step on the surface, Figs. 2 and 3 show that As explained above, the first case is that the etching rate in the depth direction of a flat surface monotonically decreases as the angle between the surface normal and the ion incident direction increases, leaving Au as a material and flattening the surface. As shown in the figure. the above
Au5 is applied to the entire surface of the uneven surface consisting of the SiO 2 film pattern 51.
2 is deposited to a thickness of 0.4 μm by sputter deposition, for example (FIG. 1a). Thereafter, etchback is performed by ion beam milling (ion beam 53) with an ion incidence angle of about 70°, for example. At this time, the etching rate on the stepped slope is about five times as high as the etching rate on the flat area, making it possible to selectively etch the Au on the convex area (FIG. 1b).
By performing the above etchback until the SiO 2 film is exposed, Au is removed only in the concave areas of the SiO 2 pattern.
, and the surface is flattened (Fig. 1c).
以上説明したように、斜めイオン・ビーム・ミ
リングによるエツチ・バツクにより、少ない工程
で、容易に平坦化することができる。この平坦化
エツチ・バツク法は、多層配線に必要な平坦化、
及び凹パタンを利用した自己整合的パタン形成
等、幅広い応用分野をもつという利点がある。
As explained above, by etchback using oblique ion beam milling, planarization can be easily achieved with fewer steps. This planarization etchback method is a method for flattening and
It has the advantage of having a wide range of applications, such as self-aligned pattern formation using concave patterns.
第1図a〜cは本発明の実施例の要部工程断面
図、第2図は本発明の原理を説明するための図、
第3図a,bはそれぞれイオン入射角度の定義を
説明する図及びイオン入射角度とエツチング速度
の関係を示す図、第4図a〜c及び第5図a〜c
はそれぞれ第1の従来例及び第2の従来例の工程
図である。
11……絶縁膜、12……金属配線、13……
層間絶縁膜、21……絶縁膜、22……金属配
線、23……層間絶縁膜、51……SiO2(パタ
ン)、52……Au、53……イオン・ビーム。
1A to 1C are cross-sectional views of main parts of the embodiment of the present invention, and FIG. 2 is a diagram for explaining the principle of the present invention.
Figures 3a and 3b are diagrams explaining the definition of the ion incidence angle and diagrams showing the relationship between the ion incidence angle and the etching rate, Figures 4 a to c, and Figures 5 a to c, respectively.
are process diagrams of the first conventional example and the second conventional example, respectively. 11... Insulating film, 12... Metal wiring, 13...
Interlayer insulating film, 21... Insulating film, 22... Metal wiring, 23... Interlayer insulating film, 51... SiO 2 (pattern), 52... Au, 53... Ion beam.
Claims (1)
と同程度乃至それ以上の膜厚を有する、イオン・
ビーム・ミリングに対して、平坦な表面の深さ方
向エツチング速度が表面の法線とイオン入射方向
のなす角度の増加とともに単調減少する性質を有
する物質としてAuの薄膜を堆積する工程と、 前記段差斜面における前記基板に平行な方向へ
のエツチング速度が平坦部の深さ方向エツチング
速度に比べ大きくなるような角度に、基板法線に
対するイオン入射角度を設定した前記イオン・ビ
ーム・ミリングにより、前記薄膜をエツチ・バツ
クする工程とを含むことを特徴とする表面平坦化
方法。[Claims] 1. An ion film having a film thickness equal to or greater than the step on the surface of a substrate having a step on the surface.
For beam milling, depositing a thin film of Au as a material whose etching rate in the depth direction of a flat surface monotonically decreases as the angle between the surface normal and the ion incidence direction increases; The thin film is etched by the ion beam milling, in which the ion incidence angle with respect to the normal to the substrate is set at an angle such that the etching rate in the direction parallel to the substrate on the slope is greater than the etching rate in the depth direction on the flat part. A method for flattening a surface, comprising the step of etching back.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13159485A JPS61289635A (en) | 1985-06-17 | 1985-06-17 | Surface flatterning |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13159485A JPS61289635A (en) | 1985-06-17 | 1985-06-17 | Surface flatterning |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61289635A JPS61289635A (en) | 1986-12-19 |
JPH0551174B2 true JPH0551174B2 (en) | 1993-07-30 |
Family
ID=15061704
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13159485A Granted JPS61289635A (en) | 1985-06-17 | 1985-06-17 | Surface flatterning |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61289635A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150064567A1 (en) * | 2013-08-29 | 2015-03-05 | Stmicroelectronics (Tours) Sas | Silicon microstructuring method and microbattery |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4966885A (en) * | 1989-08-25 | 1990-10-30 | At&T Bell Laboratories | Method of producing a device comprising a metal oxide superconductor layer |
US5744400A (en) * | 1996-05-06 | 1998-04-28 | Accord Semiconductor Equipment Group | Apparatus and method for dry milling of non-planar features on a semiconductor surface |
JP4008420B2 (en) | 2004-02-23 | 2007-11-14 | Tdk株式会社 | Method for manufacturing magnetic recording medium |
US8597528B1 (en) | 2011-03-30 | 2013-12-03 | Western Digital (Fremont), Llc | Method and system for defining a read sensor using an ion mill planarization |
US8578594B2 (en) | 2011-06-06 | 2013-11-12 | Western Digital (Fremont), Llc | Process for fabricating a magnetic pole and shields |
US9053735B1 (en) | 2014-06-20 | 2015-06-09 | Western Digital (Fremont), Llc | Method for fabricating a magnetic writer using a full-film metal planarization |
JP7382809B2 (en) * | 2019-12-02 | 2023-11-17 | キヤノントッキ株式会社 | Film-forming method and film-forming equipment |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5432985A (en) * | 1977-08-19 | 1979-03-10 | Mitsubishi Electric Corp | Flattening method for substrate surface with protrusion |
JPS55143035A (en) * | 1979-04-24 | 1980-11-08 | Nec Corp | Manufacture of pattern |
JPS5882536A (en) * | 1981-11-10 | 1983-05-18 | Fujitsu Ltd | Preparation of semiconductor device |
-
1985
- 1985-06-17 JP JP13159485A patent/JPS61289635A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5432985A (en) * | 1977-08-19 | 1979-03-10 | Mitsubishi Electric Corp | Flattening method for substrate surface with protrusion |
JPS55143035A (en) * | 1979-04-24 | 1980-11-08 | Nec Corp | Manufacture of pattern |
JPS5882536A (en) * | 1981-11-10 | 1983-05-18 | Fujitsu Ltd | Preparation of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150064567A1 (en) * | 2013-08-29 | 2015-03-05 | Stmicroelectronics (Tours) Sas | Silicon microstructuring method and microbattery |
US9780366B2 (en) * | 2013-08-29 | 2017-10-03 | Stmicroelectronics (Tours) Sas | Silicon microstructuring method and microbattery |
Also Published As
Publication number | Publication date |
---|---|
JPS61289635A (en) | 1986-12-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |