JPH05506764A - Data bus interface device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Data bus interface device field of invention TECHNICAL FIELD This invention relates generally to data bus drivers, and more particularly, to wireless telephones. Self-biased data bus driver for integrated high speed, low amplitude digital data bus Currently, in the field of wireless telephones, wireless telephone transmitters and handsets are There is one way to send voice and data to and from. This method uses two independent Use the bus. The first bus contains data signals and the second bus contains audio or sound signals. Contains voice signals. This is free from electromagnetic interference (EMI) and radio interference (RFI). This allows for a relatively slow data signal bus.

Microprocessors in microprocessor-based systems today and in the future. Digital audio in wireless telephones is becoming faster as communication between wireless devices becomes faster. signal and data signals can be combined onto one bus. This single bus Separates voice and data signals before sending them to the transceiver. Connect peripherals such as answering machines, fax machines, and modems to one bus without having to Enabling new wireless telephone technology development to be added. This includes peripherals and Reduces the number of wires required to connect to the receiver and provides a common interface method enable.

However, this data bus supports high-speed devices with minimal RFI and EMI emissions. data transfer and is highly resistant to interference from other subsystems surrounding the wireless phone. It has to be sexual. Engine control module, electronically controlled suspension system Due to its proximity to other subsystems such as The moving vehicle environment is a world in which interference between subsystems is an important issue.

One way to reduce RFI and EMI emissions is to Change the level amplitude from 5V (beak-beak value) to 0.5V (beak-beak value) It may be reduced. This amplitude reduction significantly reduces radiation, but at the same time cause some problems. First, the system is highly sensitive to EMI and RFI interference. Second, the system becomes sensitive to differences in the reference ground potentials of peripheral devices. high speed Another problem with data bus design is the connection between transceivers and peripheral devices such as handsets. separate installation, differences in the environment between the transceiver and peripheral devices, and The side equipment uses a separate power supply. First, the connection between the transceiver and peripheral devices. Regarding separation, a bus is required to connect the two systems that have been installed separately. child The distance between the two systems allows the bus to pick up noise from other systems. Increases the likelihood of causing changes in ground potential. Second, peripheral devices can be used in a variety of environments. May be subject to conditions. In other words, the transceiver is in the trunk. Each handset may be installed inside the vehicle. temperature difference between two environments can have a significant impact on the operation of some components and their voltage levels. Ru. Finally, each piece of equipment uses a different power source, which creates a difference in ground potential. There is an increased possibility that the

Therefore, it emits a signal with an amplitude of less than 0.5 volts, and environmental characteristics, power supply, grounding A high-speed digital data bus driver that is unaffected by potential and signal level differences is required. The key point.

Summary of the invention The present invention provides a data bus connection between one of a plurality of peripheral units and a data bus. Consists of a bus interface driver. This data bus interface driver The driver can receive data signals with different amplitudes and the induced noise It is not affected by differences in ground potential resulting from variations in environmental conditions. data bus interface – Face drivers are capable of data transfer in excess of IMHz and are free from EMI emissions and RF I radiation is low.

Brief description of the drawing FIG. 1 is a block diagram of a wireless data communication system.

FIG. 2 is a bus driver circuit diagram according to the present invention.

FIG. 3 is an alternative bus driver circuit diagram in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a fixed station transceiver 101 and a vehicle-mounted or portable transceiver 10. 3 shows a wireless (RF) data communication system comprising: In-vehicle or portable trans The receiver 103 transmits and receives RF multiplied signals to and from the fixed station transceiver 101. RF times The signal is combined by antenna 105 and demodulated by transceiver 107. converted into a data signal.

Transceiver 107 communicates with peripheral devices via serial digital data bus 109. Data signals can be sent and received between the two. The peripheral device in this embodiment is a handheld device. set 111 and fax 113, but could be other peripheral devices. stomach.

FIG. 2 shows the relationship between the transceiver 107 and the node set 111, which is a peripheral device. FIG. 2 is a circuit diagram of a digital data bus. Here, transceiver 107 and handle Although only the data bus 111 is shown in the second rflJ, the data bus It can also be used in configurations that correspond to devices. Digital data bus 109 is up Shown as link 211 and downlink 203. These links Enables data transmission between handset 111 and transceiver 107. child The data bus driver circuit 243 is common to all peripheral devices and serves two main purposes. achieve the target. First, the data bus driver circuit 243 used to generate a single voltage bias level for the uplink The direct pressure level of the data bus signal on the bus 211 is provided to the data bus driver 243. Prevents reference point fluctuations at individual peripherals on the data bus by do. Second, the data bus driver is a bus interface chip (BIC) The voltage level of the data signal output from 207 is used on data bus 109. The data signal is divided up to the amplitude of the data signal. Regarding the present invention, the fluctuation of the output voltage of the chip is The width is 5v, which is divided into amplitudes of 0.5v. however , any other similar voltage divider setup can be used.

Because data bus 109 uses small amplitude signals, data bus 109 In order to properly prioritize buses 109, they must be driven around the same reference point. Must be.

Data bus 109 has the lowest Q2 base potential and has priority over all other peripherals. By applying a reverse bias to the base-emitter junction of Q2 on the Controlled by peripherals that prevent devices from driving the bus. for all peripherals The common bias points are Ql) transistor 227 and Q2) transistor 213. This is achieved through feedback between the two. Resistance 231. capacitor 229 and Ql) The circuit containing transistor 227 is connected to the alternating current of the data signal on bus 211. Remove ingredients. The emitter of Ql has a common via of uplink 211 of the bus. voltage exists.

This common bias voltage level is used to bias Q2 Ff1 . As a result of this feedback behavior, parts.

Ground level or power supply potential differences are removed with respect to the uplink 211 of the bus. , and a data voltage signal output from the bus interface chip 207. Level differences are also removed.

Data signal output from bus interface chip 207 on signal line 233 The force has an amplitude that varies depending on the surrounding equipment. In this embodiment, the peripheral device The data signal output from has an amplitude between 0 and 5 volts. resistance 217 and resistor 223 form a voltage divider network, which reduces the amplitude to Ql) The bias voltage is reduced to O,SV, which is approximately the same as the bias voltage present at the emitter of 227. Ru. Resistor 221 and capacitor 219 are filters to remove noise from the line. Configure a filter circuit. Inductor 215 also performs a filtering operation.

The peripheral device lowers 233 to a low level and maintains that state for a predetermined period of time. Therefore, once control of the bus is obtained, Q2) transistor 213 is turned on. , the data exits to transceiver 107 via uplink 211. neighborhood The device voltage supply 225 may be different from the transceiver 237 power source. So Regardless of the difference, the data buses still have a common bias voltage. first buy The low level is generated by transceiver power supply 237 and resistor 239. on/off - Switch 201 and downlink 203 are switched on when the peripheral device is first turned on. turns on.

This grounds the downlink and connects the new peripheral 111 to the serial bus. Transceiver 107 is notified that it is connected to 109. The downlink is Used to send a common lock source from transceiver 107 to all peripherals. be done. All data signals sent by peripheral device 111 are approximately 50% valid. Must have a duty cycle. Effective duty cycle 50% is It is defined as the average value of the data signal equal to half the peak-to-peak voltage.

This stabilizes the bias point at the midpoint of the transfer level and Appropriate data restoration by the server is realized. Output signal line 233 is high or low If the condition is maintained for a considerable period of time, the direct current at the emitter of Q1 transistor 227 The current bias level is finally adjusted to the voltage level at which the data is retained and This will cause a data transmission error. This potential problem does not guarantee the transfer of data signals. The solution is to send Manchester encoded data.

FIG. 3 shows an alternative embodiment to the embodiment of FIG.

The major difference in this embodiment is that the mask or transceiver 107 with reference to the downlink 303 bias level coming from the network transceiver 107. to determine the bias level at the output of Q1 emitter 315. It is to determine the bell. Other circuit parts are the same as those in FIG.

There are two important parts to this embodiment. First, data output from peripheral devices By using the DC voltage level of the data bus to bias the signal, Ru. This biasing reduces environmental characteristics, power supply, ground potential and signal Individual peripheral differences in level are removed from the data signal. Second, the individual Adjusts the amplitude of signals output from different peripheral devices to a common low amplitude signal. Ru.

Adjusting the amplitude in this way provides a pre-existing method for prioritizing bus accesses. A high voltage is generated and EMI and RFI emissions are reduced.

abstract An interface between one of the plurality of peripheral devices (111) and the data bus (109) data bus interface device. data bus interface The bus driver (243) loads the data up to the voltage level of the data bus (109). can be biased and receive data signals (233) with different amplitudes. ground potential resulting from induced noise and a variety of environmental conditions. Not affected by differences. The data bus interface driver (243) is Data transmission exceeding IMHz is possible, and there is little EMI and RFI radiation.

international search report 1'l+-6-^-"""""PCr/US9210129B

Claims (1)

[Claims] 1. A data communication system that: A serial bus containing at least one conductive trace and having a common bias voltage. vinegar; At least the first peripheral device of the at least first and second peripheral devices further: means for coupling with the serial bus; means for requesting use of the serial bus; transmitting a data signal to the serial bus; means; approximately 50% effective duty cycle, amplitude less than 0.5 volts; and means for generating data signals having a transfer rate of up to 5 MHz; A data communication system comprising: 2. The first peripheral device includes means for obtaining power from one of at least two power sources. 2. The data communication system according to claim 1, further comprising: 3. that the serial bus further comprises a second conductive trace; The data communication system according to claim 1, characterized in that: 4. The first peripheral device further includes means for receiving data signals from the serial bus. 4. The data communication system according to claim 3, wherein the data communication system includes: 5. The effective duty cycle of the data signal is approximately 50%, and the transceiver a wireless telephone including a data bus for transmitting data signals and at least one peripheral device; The data bus is: a transceiver having a first ground potential and at least one circuit having a second ground potential; A means of transmitting data to and from a peripheral device; Data signals with amplitudes less than 0.5 volts and transfer rates greater than 1 MHz Means for generating: a first input signal from a first peripheral device of the two or more peripheral devices; a second input receiving a voltage level from a second peripheral device of the two or more peripheral devices; A radiotelephone comprising: means for receiving a signal voltage level; . 6. The data bus notifies the transceiver of the presence of at least one peripheral device. 6. The wireless telephone according to claim 5, further comprising means for configuring the wireless telephone. 7. A bus interface device having a first and a second terminal, the first terminal a terminal is coupled to a data bus, and the second terminal is connected to at least one of the first peripheral devices. coupled to the input and at least one output, the data bus has an amplitude of less than 0.5 volts. the at least one output generates a second signal; a bus interface device, the at least one input being coupled to a data bus; means for biasing a second signal coupled to the data bus; adjusting the amplitude of the second signal to a predetermined level coupled to said filtering means; means; and a second signal coupled to the regulating means and the data bus in response to a second signal; A bus interface characterized in that it is constituted by: a means for accessing Device. 8. 8. The bus interface device according to claim 7, wherein the bias applying means teeth: a base, an emitter and a collector, the collector coupled to a first voltage level; a first transistor, the emitter of which is coupled to a second voltage level; a first and a second terminal, the second terminal being coupled to the second voltage level; 2 capacitors; and first and second terminals, the first terminal of which is connected to the data bus. coupled, the second terminal of which connects the first terminal of the second capacitor and the first terminal. a first resistor coupled to the base of the transistor; A bus interface device comprising: 9. 8. The bus interface device according to claim 7, wherein the adjusting means: first and second terminals, the first terminal being coupled to the filtering means; a third resistor; and first and second terminals, the first terminal being connected to the third resistor; coupled to a second terminal, the second terminal coupled to at least one output of the first peripheral device; A bus interface comprising: a fourth resistor; Device. 10. The access means includes a second track having a base, a collector and an emitter. further comprising a resistor, the base being coupled to the first terminal of the adjusting means, and the base being coupled to the first terminal of the adjusting means; the collector is coupled to a second voltage level and the emitter is coupled to a data bus. 8. The bus interface device according to claim 7, characterized in that: