JPH0548420A - Output circuit - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to prevent the generation of shoot-through current while preventing a decrease in the operating speed of an output circuit. [Structure] Between the high-potential-side power supply Vcc and the low-potential-side power supply G, the first to fourth stages of N-channel MOS transistors Tr1 to
Tr4 is connected in series, and the fourth and first stage transistors T
The complementary input signals IN and IN are input to the gates of r4 and Tr1, and the input signal IN of the same phase as that of the transistor Tr1 of the first stage is delayed and input to the gate of the transistor Tr2 of the second stage. The input signal IN having the same phase as that of the transistor Tr4 of the fourth stage is delayed and input to the gate of the transistor Tr3 of the stage, and the output signal Dout is output from the source of the transistor Tr2 of the second stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit used for outputting a binary logic signal in a semiconductor integrated circuit.

Although an output circuit for outputting a binary logic signal is used in a semiconductor integrated circuit, the power consumption and operation of the output circuit are reduced with the recent increase in speed and power consumption of the semiconductor integrated circuit. There is a demand for higher speed.

[0003]

2. Description of the Related Art An example of a conventional output circuit will be described with reference to FIG. 4. Two stages of N-channel MOS transistors Tr1 and Tr2 are provided between a high potential side power source Vcc and a low potential side power source ground G. Connected in series as
A complementary input signal I is applied to the gates of the transistors Tr1 and Tr2.
By inputting N and bar IN to turn on one of the transistors Tr1 and Tr2, both transistors Tr1 and Tr2 are turned on.
An output signal Dout of H level or L level is output from the output terminal Tout connected between Tr2.

In such an output circuit, when the input signals IN and IN are switched, both transistors Tr1,
Tr2 may momentarily turn on simultaneously and a through current may flow from the power supply Vcc to the ground G. If such a through current flows, power consumption increases and power supply noise occurs.

Therefore, the respective input signals IN and IN are shown in FIG.
, Each of the transistors Tr is connected via the NAND circuits 1a and 1b to which the other output signals are input as input signals and the inverter circuits 2 connected before and after the NAND circuits 1a and 1b.
When input to 1 and Tr2, each NAND circuit 1a, 1b outputs an H level signal regardless of the other input signal when one input signal is at L level, and when one input signal is at H level. Determines whether the output signal is H level or L level depending on whether the other input signal is H level or L level. Therefore, in the output circuit shown in FIG. At the time of switching, one transistor is turned off and then the other transistor is turned on. Therefore, it is possible to prevent a through current flowing from the power source Vcc to the ground G. Each inverter circuit 2 operates as a buffer circuit that stably drives each of the transistors Tr1 and Tr2 based on the input signals IN and IN.

[0006]

However, in the output circuit having the above configuration, the NAND circuits 1a and 1b require an operation time of two stages of the inverter circuit 2 inserted before and after the NAND circuits 1a and 1b. In the output circuit shown, it takes four operating stages of the inverter circuit 2 to input the input signals IN and IN to the gates of the transistors Tr1 and Tr2 to drive the transistors Tr1 and Tr2.
It is a factor that reduces the operation speed.

An object of the present invention is to provide an output circuit capable of preventing a through current of an output transistor while preventing a decrease in operating speed.

[0008]

FIG. 1 illustrates the principle of the present invention. That is, the N-channel MOS transistors Tr1 to Tr4 of the first to fourth stages are connected in series between the high-potential-side power source Vcc and the low-potential-side power source G, and the fourth-stage and first-stage transistors Tr4 and Tr1 are connected. Has a complementary input signal IN,
The input signal bar I having the same phase as the first-stage transistor Tr1 is input to the gate of the second-stage transistor Tr2.
N is delayed and input, and the input signal I of the same phase as the transistor Tr4 of the fourth stage is input to the gate of the transistor Tr3 of the third stage.
N is delayed and input, and the output signal Dout is output from the source of the second-stage transistor Tr2.

Further, as shown in FIG. 2, the high potential side power source Vcc
And the low-potential-side power supply G, the N-channel MOS transistors Tr1 to Tr4 of the first to fourth stages are connected in series, and complementary input signals are applied to the gates of the transistors Tr4 and Tr1 of the fourth and first stages. IN and bar IN are input, the input signal IN of the transistor Tr4 of the fourth stage is input to the gate of the transistor Tr2 of the second stage through the inverter circuits 2a, 2b, 2c of the odd stages, and the transistor Tr3 of the third stage is input. The input signal bar IN of the first-stage transistor Tr1 is input to the gate of Tr3 via the odd-numbered inverter circuits 2d, 2e, 2f, and the output signal Dout is output from the source of the second-stage transistor Tr2. ing.

Further, as shown in FIG. 4, the high potential side power source Vcc
And the low-potential-side power source G between the first-stage P-channel MOS transistor Tr1 and the second-stage and third-stage N-channel MOS transistors.
Transistors Tr2, Tr3 and a fourth-stage P-channel MOS transistor Tr4 are connected in series, and complementary input signals IN, IN are supplied to the gates of the first-stage and fourth-stage transistors Tr1, Tr4.
The input signal bar I having a phase opposite to that of the first-stage transistor Tr1 is input to the gate of the second-stage transistor Tr2.
N is delayed and input, and the input signal I having a phase opposite to that of the transistor Tr4 of the fourth stage is input to the gate of the transistor Tr3 of the third stage.
N is delayed and input, and the output signal Dout is output from the source of the second-stage transistor Tr2.

[0011]

When the input signal IN and the bar IN are switched,
After the transistor Tr1 of the first stage is turned off, the transistors Tr3 and Tr4 of the third and fourth stages are both turned on, or after the transistor Tr4 of the fourth stage is turned off, the first and second stages are turned on. Both transistors Tr1 and Tr2 are turned on.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
And FIG. 3 will be described. The same components as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 2, the number of output transistors is four.
N-channel MOS transistors Tr1 to Tr4 of the stage are the power source V
An output signal Dout is output from an output terminal Tout connected in series between cc and the ground G and connected between the second-stage transistor Tr2 and the third-stage transistor Tr3.

The input signal IN is the transistor Tr4 of the fourth stage.
Is directly input to the gate of the transistor Tr2 of the second stage and is input to the gate of the transistor Tr2 of the second stage via the three-stage inverter circuits 2a, 2b and 2c. The input signal bar IN is directly input to the gate of the transistor Tr1 of the first stage, and the inverter circuit 2 of the three stages is connected to the gate of the transistor Tr3 of the third stage.
It is input via d, 2e, and 2f.

In the output circuit thus constructed, for example, the input signal IN is at the L level and the input signal bar IN is at the H level.
At the level, the transistors Tr of the first and second stages are
When 1 and Tr2 are turned on, the transistors Tr3 and Tr4 in the third and fourth stages are turned off and the output signal Dout becomes H level.

From this state, as shown in FIG. 3, the input signal I
When N rises to the H level and the input signal bar IN falls to the L level, the transistor Tr1 is turned off and the transistor Tr4 is turned on first, and then the transistor Tr2 is turned off after a delay of the operation time of the three-stage inverter circuit. At the same time, the transistor Tr3 is turned on. Therefore, since the transistor Tr3 is also turned off when the transistor Tr1 is turned off, the output signal Dout falls slightly from the H level to the high impedance state, and is lowered to the L level when the transistor Tr3 is turned on. Since the transistor Tr1 is turned off prior to the on operation of the transistor Tr3, the power source V
Generation of a through current from cc to ground G is reliably prevented.

On the other hand, when the input signal IN falls from the H level to the L level and the input signal bar IN rises from the L level to the H level, the reverse operation is performed and the fourth stage transistor Tr4 is turned off. After that, the transistors Tr1 and Tr2 of the first and second stages are both turned on, so that the generation of a through current is prevented.

As described above, in this output circuit, the transistor Tr4 is turned on before the transistors Tr1 and Tr2 are turned on.
Is turned off, and the transistor Tr1 is turned off prior to the on operation of the transistors Tr3 and Tr4. Therefore, the power supply Vcc
The through current from the ground to the ground G is surely prevented, and driving the transistors Tr1 to Tr4 with the input signals IN and IN requires only the operation time of three stages of the inverter circuit. The operating speed can be improved.

In the above embodiment, the transistors Tr2,
In order to reliably delay the ON operation of Tr3 as compared with the OFF operation of the transistors Tr1 and Tr4, the input signals IN and I
N is a transistor Tr2 through a three-stage inverter circuit,
Although input to Tr3, as shown by the broken line in FIG.
N and bar IN may be input to the transistors Tr2 and Tr3 via a one-stage inverter circuit.

Further, as shown in FIG.
1 and Tr4 are P-channel MOS transistors, the input signal IN is input to the gate of the transistor Tr1 and the input signal bar IN is input to the gate of the transistor Tr4. The effect can be L level.

[0021]

As described in detail above, the present invention exerts an excellent effect of preventing the generation of the through current while preventing the decrease of the operating speed of the output circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a waveform diagram showing the operation of the embodiment.

FIG. 4 is a circuit diagram showing another embodiment.

FIG. 5 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 Tr1 1st stage transistor Tr2 2nd stage transistor Tr3 3rd stage transistor Tr4 4th stage transistor Vcc High potential side power supply G Low potential side power supply IN, bar IN Input signal Dout Output signal

Claims (3)

[Claims] 1. N-channel MOS transistors (Tr1 to Tr4) of the first to fourth stages are connected in series between a high potential side power source (Vcc) and a low potential side power source (G) to form a fourth stage. And complementary input signals (IN, IN) are input to the gates of the first-stage transistors (Tr4, Tr1), and the first-stage transistors (Tr) are input to the gates of the second-stage transistors (Tr2).
1) Input the same phase input signal (bar IN) with delay, and input the same phase input signal (IN) as the fourth stage transistor (Tr4) to the gate of the third stage transistor (Tr3). An output circuit which receives and outputs an output signal (Dout) from the source of the transistor (Tr2) of the second stage. 2. N-channel MOS transistors (Tr1 to Tr4) of the first to fourth stages are connected in series between the high potential side power source (Vcc) and the low potential side power source (G) to form a fourth stage. And complementary input signals (IN, IN) are input to the gates of the first-stage transistors (Tr4, Tr1), and the fourth-stage transistors (Tr) are input to the gates of the second-stage transistors (Tr2).
Input the input signal (IN) of 4) to the odd number of inverter circuits (2
a, 2b, 2c), and the first stage transistor (Tr1) is connected to the gate of the third stage transistor (Tr3).
Input signal (bar IN) of the inverter circuit (2
d, 2e, 2f) and outputs an output signal (Dout) from the source of the transistor (Tr2) of the second stage. 3. A P-channel MOS transistor of the first stage (Tr1) and N-channel MOS transistors of the second and third stages (Tr2) between a high potential side power source (Vcc) and a low potential side power source (G). , Tr3) and the fourth-stage P-channel MOS transistor (Tr4) are connected in series, and complementary input signals (IN, IN) are input to the gates of the first-stage and fourth-stage transistors (Tr1, Tr4). , The gate of the second-stage transistor (Tr2) is delayed by the input signal (bar IN) having a phase opposite to that of the first-stage transistor (Tr1), and is input to the gate of the third-stage transistor (Tr3). An output circuit characterized in that an input signal (IN) having a phase opposite to that of the fourth-stage transistor (Tr4) is delayed and inputted, and an output signal (Dout) is outputted from the source of the second-stage transistor (Tr2). ..