JPH0545984B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pipeline type digital computer, and particularly to a digital computer having a main arithmetic unit and a slave arithmetic unit in order to solve address conflicts and speed up conditional branch instructions. The present invention relates to a hierarchical calculation method suitable for further speeding up computers.

[Background of the invention]

In this computer, the execution process of each instruction is divided into a plurality of stages, and different stages of different instructions are executed in parallel, thereby effectively executing a plurality of instructions in parallel.

However, when the data required for processing a certain instruction B is obtained using the calculation result specified by the preceding instruction A, until the calculation result of instruction A is determined,
Execution of instruction B must be delayed. For example, when instruction A is executed, the index register or base register is rewritten, and instruction B
This corresponds to the case where the address for main memory access is calculated by adding the contents of the index register or base register and the address information contained in instruction B. In this way, a state in which the address for executing instruction B must be determined using the operation result of the preceding instruction A is called an address conflict. In this case, the address calculation stage of instruction B is delayed until the operation of instruction A is completed.

Prior application (Patent application 1987-194002 and Patent application 1982-
62143), in order to reduce this delay, in addition to the main processing unit that can execute the operations required by all instructions, the computer uses a A slave arithmetic unit that can only perform arithmetic operations is provided. In this prior application, when the number of cycles required for the operation of an instruction C that can be executed only in the main processing unit is large, when this instruction C is executed in the main processing unit, the operation of this instruction C is performed in the slave processing unit. The address calculation stage of instruction B is skipped and the operation of the next instruction A is executed early, and this result is used as the contents of the index register or base register in the address calculation of the subsequent instruction B. It minimized delays. In other words, in this prior application, the reason why the operation in the slave arithmetic unit of instruction A can be executed earlier than the operation in the main arithmetic unit is that the main arithmetic unit requires a large number of cycles (assumed to be N1) for the operation of instruction C. After the lapse of time, the operation of the next instruction A is started, but the slave operation unit skips the operation of the instruction C in fewer cycles than N1 (NS), and immediately after the skip, the operation of the next instruction A is started. This is because the calculation of A is started. Therefore, conversely, if the number of arithmetic cycles N1 of instruction C in the main arithmetic unit is so small that it is equal to the number of skip cycles NS, or if the number N1 of arithmetic operations is the same as N1 because instruction C also executes arithmetic operations in the slave arithmetic unit. When the operation of the next instruction A is started after the number of cycles has elapsed, it cannot be expected that the operation of the instruction A in the slave arithmetic unit can be executed much more than the operation in the main arithmetic unit.

The same problem occurs with conditional branch instructions.
In the operation execution cycle of this instruction (hereinafter referred to as BC instruction), it is determined whether the branch is successful or not based on the condition code of that cycle. Therefore,
When the operation by the instruction D preceding the branch instruction is an instruction that changes the condition code, the branch cannot be determined until the operation of the preceding instruction D is completed. In this way, a state in which a BC instruction branch decision must be made after the completion of the operation of the preceding instruction D is called a condition code conflict state. in this case,
Branch determination of the BC instruction is delayed until the operation of instruction D is completed.

In order to reduce the delay in branch judgment due to condition code conflicts, the prior patent application No. 1986-194001 and
There was a computer described in No. 58-62143. In this case as well, if the number of cycles (N1) required for the operation of an instruction E that can be executed only in the main processing unit is large, when this instruction E is being executed in the main processing unit, the slave processing unit By skipping the operation in the number of cycles NS smaller than N1, executing the operation of the next instruction D early, and using this result in the branch judgment of the subsequent BC instruction, the delay in branch judgment can be reduced. was. In this prior application, as in the case where the hierarchical arithmetic method is applied to the above-mentioned address conflict, when N1 is small enough to be equal to NS, or when instruction E needs to perform an operation in the slave arithmetic unit, instruction D It cannot be expected that the operation in the slave operation unit will be performed earlier than the main operation.

[Purpose of the invention]

Therefore, an object of the present invention is to solve the above-mentioned problems in the hierarchical arithmetic method of the prior application, and to provide a pipeline-controlled computer with less processing delay due to address conflicts and condition code conflicts, and therefore with higher performance. Our goal is to provide the following.

[Summary of the invention]

In the hierarchical arithmetic method of the earlier application, the operation of subsequent instructions is performed early in the slave arithmetic unit by quickly skipping instructions that require a large number of arithmetic cycles and therefore cannot be operated on the slave arithmetic unit. However, in the present invention, by reducing the number N2 of arithmetic cycles in the slave arithmetic unit of a certain instruction compared to the number N1 of arithmetic cycles in the main arithmetic unit of the instruction, By shortening the number of cycles required for skipping the instruction in the slave arithmetic unit, even for the instruction that has the shortest number of operation cycles among the instructions that are only operated on, the above-mentioned problem of the hierarchical arithmetic method of the earlier application can be solved. This is to solve the problem.

In order to make the slave arithmetic unit operate faster than the main arithmetic unit, it is necessary to configure the latter with a faster circuit, or to implement the latter with a high degree of integration, focusing on the fact that the logic scale of the latter is small. This can be realized by configuring it using a system.

When configuring a data processing device that includes two arithmetic units with different operating pitches, it is easy to synchronize the entire system using timing pulses whose pitch is a common divisor of each pitch. Setting the signal widths of all the control signals to be the same facilitates the logic configuration. As a specific example, in a data processing device where the main processing unit can process instructions at a 2-cycle pitch, and the other parts including the slave processing units can process instructions at a 1-cycle pitch, the entire unit can be synchronized using timing pulses at a 1-cycle pitch, and It is preferable to configure the signal width of all the control signals at one time to be one cycle. Therefore, the operation end signal in the main processing unit is configured to be on for one cycle and off for the next cycle when issued once.

[Embodiments of the invention]

[Overview of the device] 6A and 6B are instruction buffers, 8 is a reading circuit for selectively reading instructions from one of these instruction buffers, 10 is an instruction register, 12 is an instruction decoder, and 500 is a device for reading decoded information. The receiving register 14 is an instruction queue register for storing decoding information from the instruction decoder 12;
14 here consists of three registers for storing decoding information of three instructions. 16A is a selector for selecting an instruction in the instruction queue register 14, and 20A is a first operation execution unit (hereinafter abbreviated as 1E unit) for executing the operation of the instruction selected by the selector 16A. This unit 20A is configured to be able to execute operations specified by all instructions executed by this computer. 18A is the 1st E unit 20A
22A is the first general-purpose register (this is actually a register group consisting of a plurality of general-purpose registers) for storing the operand supplied to the instruction or the operation result therefrom, and 22A is the first general-purpose register for storing the operand supplied to the 1 command control unit (hereinafter referred to as the 1st I unit).

24 is an address adder for calculating the address of the memory operand necessary for the operation;
28 is a cache memory that stores a copy of the main memory or a part thereof; 28 is an operand queue buffer that stores the memory operands read from 26; It consists of three registers to store two operands. Selector 30A selects the operand of buffer 28 and selects the operand of buffer 28.
This is a selector for supplying to the 1E unit 20A. The circuit described above is basic for executing instructions using a pipeline system.

In this embodiment, in addition to the above, a second arithmetic execution unit 20B (hereinafter referred to as the second E unit), a selector 16B for selecting decoding information of an instruction to be executed by this unit 20B from the instruction queue register 14, A second general-purpose register 18B (this is actually a register group consisting of multiple general-purpose registers) and a second general-purpose register 18B for storing the operand to be sent to the second E unit 20B or the operation result of this unit, and the second E unit 20B are required. The memory operand with the operand buffer 28
a selector 30B for selecting from 2E, and a second instruction control unit (hereinafter simply referred to as the second unit) 22B that controls the execution of the second E unit 20B.
and a register 3 for storing condition codes output from the first and second E units 20A and 20B.
4A and 34B, and circuits 32 and 36 that respectively detect address conflicts and condition code conflicts between a plurality of instructions executed in a pipeline manner are provided.

The second E unit 20B performs relatively simple operations such as addition and subtraction. In this embodiment, this unit is configured, for simplicity, to only perform operations that complete in one machine cycle. However, as will become clear from the following description, the present invention is not limited to such a second E unit. Since the second E unit 20B is for executing relatively simple operations at high speed, it has a second general-purpose register 18B and an operand queue buffer 28 rather than the first E unit 20A.
It is desirable to install it near the Further, the first and second general-purpose registers 18A and 18B are composed of the same number of registers.

In this device, all instructions are executed by the first E unit 20A. On the other hand, among these instructions, the 2nd E is an instruction that rewrites general-purpose register 18A.
Instructions that can be executed by unit 20B are also executed by this second E unit 20B. Therefore, such a command is issued to the first and second E units 20A and 20.
It is executed in both B. However, the same operation for the same instruction in the first and second E units 20A and 20B can be activated at different timings. That is, the first and second E units 20A, 2
Two selectors 16A, 16B are provided to separately supply the decoding information required by the 0Bs, and two selectors 16A, 16B are provided to separately supply the memory operands each of these units 20A, 20B requires. 30A, 30B are provided, the 1st E unit 20A, the selector 16A,
30A is controlled by the first I unit 22A,
The 2E unit 20B and selectors 16B and 30B are controlled by the 2nd I unit 22B. As a result, the 1st E unit 2 of a certain instruction
Even in a state where the instruction cannot be executed in 0A, the instruction can be executed in the 2E unit 20B.
This speeds up resolution of address conflicts or condition code conflicts.

[Instruction format]

The instructions used in this device are the same as those used in Hitachi, Ltd.'s M series computers or IBM's 370 series computers. These instructions are classified into several formats, and FIG. 3A shows one format necessary for understanding the present invention. Examples of instructions with this format are add and load instructions, respectively.
For simplicity, these will be referred to as A and L instructions below. Bits 0-7 of these instructions represent the operation code (OPCODE), bits 8-11 are the register part (R), and in the A instruction, the general-purpose register number where the operand to be read for the operation is stored. It also shows the register number in which the calculation result is stored. Further, in the L instruction, this register section indicates the register number in which the operation result is to be stored. Bits 12-15 and 16-19 are an index portion (X) and a base portion (B), respectively, and indicate the number of a general-purpose register used to calculate the address of a storage operand to be read from main memory 26, respectively. In the following, the general-purpose register numbers indicated by the register section, index section, and base section will be referred to as operand register number R _OP , index register number R _X , and base register number R _B , respectively. Furthermore, bits 20-31 are a displacement part (D) indicating the eccentricity value DISP used in the address calculation.

FIG. 3B shows the instruction format of the BC instruction.
Bits 8-11 of this format are a mask part (M), which specifies the value of the condition code that will result in a successful branch.

The index part (X), base part (B), and offset position DISP of the BC instruction are used to calculate the address of the branch destination instruction to be read from the main memory 26.

The following embodiment will be explained using only A, L, and BC instructions. Of these, 2nd E unit 20
The instructions that can be executed by B are A and L instructions, and
The instruction to rewrite the condition code is the A instruction.

[Reading instructions]

One of the instruction buffers 6A and 6B is used to store a continuous instruction sequence in memory (referred to as the main stream) including the instruction that is currently being processed, and the other is used to store branch instructions on the main stream. It is used to store a continuous instruction sequence (called a target stream) in memory starting from the branch destination instruction after processing has started. The processed branch instruction is determined to be a successful branch,
When processing of a branch destination instruction begins, the instruction sequence that was previously considered to be the target stream is then considered to be the main stream. In this way, the instruction buffer storing the main stream is switched every time the branch instruction is successful. Main memory 26
Fetch and buffer the instruction sequence from 6A, 6
Control of storing the instruction sequence into B is performed by an instruction fetch circuit (not shown). The readout circuit 8 sequentially selects instructions from the buffers 6A and 6B that currently store the main stream, and sequentially sends them to the instruction register 10. This readout circuit 8 selects the buffers 6A and 6B depending on whether the value of a flip-flop (hereinafter, a flip-flop may be abbreviated as FF) 9 is 1 or 0.
This flip-flop 9 changes its value every time the branch success signal BCTKN becomes 1, as will be described later.

As will be described later, an instruction output from the readout circuit 8 is set in the instruction register 10 by a control circuit (not shown) each time the decoding stage of the instruction in the instruction register 10 is executed.

(Summary of Instruction Execution Operation) Considering the computer listed in Prior Patent Application No. 1983-62143 as an example of a computer to which the hierarchical arithmetic method is applied, the execution stage of the Load instruction in that computer is as shown in Figure 9D. Become. That is, the D stage is for instruction decoding and address calculation, and the A stage is for reading operands or branch destination instructions.
stages, L1 and L2 stages for setup to the first and second E units, E1 and E2 stages for calculations in the first and second E units, the first,
It consists of P1 and P2 stages for writing operation results to the second general-purpose register. In the above earlier application,
Each of the above stages requires one machine cycle.

On the other hand, the execution stage of the Load instruction in the embodiment of the present invention is as shown in FIG. 9E. That is, D for instruction decoding and address calculation,
D' stage, A for reading operand or branch target instruction, A' stage, 1st, 2nd E
Consists of L1 and L2 stages for setup to the unit, E1 and E2 stages for operations in the first and second E units, and P1 and P2 stages for writing operation results to the first and second general-purpose registers. . That is, the processing at the D stage in the prior application corresponds to the processing at the D and D' stages in this embodiment, and the A stage corresponds to the A and A' stages. Here, in this embodiment, a timing pulse T0' having a pitch of 1/2 of the timing pulse T0 in the above-mentioned prior application is used, and therefore, the machine cycle is set to 1/2. Therefore, in this example, D, D', A, A', L2, E2, P2
Each stage requires one machine cycle, and L1, E1, and P1 require two machine cycles each.

What should be noted here is that although the machine cycles of the above-mentioned prior application and this embodiment are shortened to 1/2 in the latter case, the stages of instruction decoding and address calculation (D, D, D'), operands, etc. The read stage (A and A, A'), the setup stage to the 1st E unit (L1, respectively), the arithmetic stage in the 1st E unit (E1, respectively), the write stage of the operation result to the 1st general-purpose register (respectively) Regarding P1), the real time is the same. Therefore, it can be said that the configuration of these logic circuits can be realized using circuits and mounting techniques of the same level in both the prior application and this embodiment.

On the other hand, in this embodiment, each stage of L2, E2, and P2 can be executed in one machine cycle, so the processing time is 1/2 of the actual time compared to the stages of L2, E2, and P2 in the previous application. That will happen. This means that the circuits related to the execution of L2, E2, and P2 are
Since it is limited to the 2I unit, 2E unit, and 2nd general-purpose register, their logical scale occupies a small proportion of the entire device, and therefore it is possible to place them in an extremely limited space within the entire device. Therefore, it can be realized. Alternatively, it can be realized by configuring only these three logics using high-performance circuits and mounting technology. Even in this case, even if this high-performance circuit and mounting technology is more expensive than the peripheral logic, it only makes up a small percentage of the total, so it is possible to minimize the impact on the overall price increase of the device. .

The instructions set in the instruction register 10 are executed in the following stages.

(D, D' stage) This is the stage of instruction decoding and address calculation. That is, the instruction in the instruction register 10 is decoded by the decoder 12 to generate decoding information, and this is set in one register in the instruction queue register 14. Additionally, the base register number R _B and index register number _R The two data read from the general register 18B based on these register numbers are input to the address adder 24 via line 47, and are added to the deviation value DISP input from the instruction register 10 via line 40. Ru. The address is thus calculated.

In this embodiment, the decoder 12 outputs the following information to the line 42 as decoding information based on the instruction operation code OP CODE and the operand register number R _OP .

(1) OP CODE (2) R _R : Operand read register number, in the above A instruction, the operand register number
Equals R _OP .

(3) R _W : Register number where the operation result is written; in the above two instructions, it is the operand register number.
Equals R _OP .

(4) SUBGR: Second operation display signal indicating whether or not the instruction whose operation result should be stored in the general-purpose register can be executed by the second E unit 20B. For example, this signal becomes 1 in the case of an A command or an L command.

(5) CHGGR: Register change display signal indicating that the instruction should store the operation result in a general-purpose register. For example, this signal becomes 1 for A and L commands.

(6) SUBCC: Of the instructions that change the condition code,
A second operation display signal indicating that the instruction is executable in the second E unit 20B.
For example, this signal becomes 1 in the case of an A command.

(7) CHGCC: CC change display signal indicating that the instruction changes the condition code. for example,
This signal becomes 1 at the time of the A command.

(8) BC: BC command display signal indicating BC command.

(9) MASK: The mask part itself of the BC instruction.

Note that the instruction decoder 12 generates other decoding information necessary for instruction execution control, but this is the same as the conventional technology and is not directly related to the present invention, so a description thereof will be omitted.

Note that the D and D' stages are each completed in one machine cycle.

(A, A' stage) Based on the memory address calculated in the D, D' stage, an operand is read from the main memory 26 and stored in one register of the operand buffer 28. These A and A' stages are also completed in one machine cycle each.

(L1 stage) Instruction decoding information and register operands and memory operands necessary for the operation are set in the 1E unit 20A. That is, the selector 16A selects the decoding information of the instruction to be executed, and the line 44A
Output to. Among the selected decoding information, the read register number R _R is input to the first general-purpose register 18A, and based on this, the necessary operand RDATA1
is read and this operand is sent to the 1E unit 20A via line 46A. On the other hand, among the decoding information, OP CODE, write register number R _W ,
Second calculation display signal SUBGR, register change display signal CHGGR, condition code change display signal CHGCC,
is sent to the first E unit 20A. moreover,
The selector 30A is the operand queue buffer 2.
8 and sends it to the first E unit 20A via line 45A. The first E unit 20A takes in the various data thus input into its internal register. This stage is executed in two machine cycles.

(E1 stage) The 1st E unit 20A executes the desired calculation based on the data taken in at the L1 stage, and the result is
Output WDATA1 to line 50A. At this time, at the same time, the write register number that was immediately captured
R _W , a write signal WC1 of the first general-purpose register is output.

Furthermore, when the operation is to change the condition code, the condition code CC1 is calculated depending on the operation result, and this code CC1 and the set instruction signal SET1 are
is output on line 70A.

Note that the number of machine cycles required for this stage is 2 machine cycles. Depending on the type of instruction,
There are some that require two or more E1 stages.
Therefore, the shortest operation is completed in two machine cycles, and the longest one is completed in multiples of two machine cycles. Incidentally, in the first half machine cycle of the last stage belonging to this E1 stage, an operation end signal EOP1 is outputted to 48A. Therefore, in the case of an operation that completes in the shortest two machine cycles, the signal EOP is output in the cycle in which the operation is started.
1 is output.

(P1 stage) Operation result WDATA1 obtained at E1 stage
is written to a register within the first general purpose register 18A, indicated by write register number _RW .
When this operation cannot be executed by the second E unit 20B, the operation result WDATA1 and the write register number _RW are also input to the second general-purpose register 18B, and a similar write is performed. As already mentioned, the second general-purpose register 18B is designed to write the operation result WDATA2 by the second E unit 20B, but the second E unit 20B can only execute some operations. Therefore, first,
A mismatch in the contents of the second general purpose registers 18A, 18B may occur. This mismatch can be prevented by writing the calculation result WDATA1 by the first E unit 20A also to the second general-purpose register 18B. Therefore, no inconvenience occurs even if the second general-purpose register is used for the above-mentioned address calculation. Further, when performing an operation to change the condition code, the calculated condition code CC1 is set in the register 34A in response to the set signal SET1. Furthermore, this P1
The stage ends in two machine cycles following the E1 stage.

In this manner, execution of one instruction is completed. However, since an instruction that can be executed in the second E unit 20B and that rewrites a general-purpose register or condition code is also executed in the second E unit 20B, the next stage is also executed in addition to the operations described in these stages.

(L2 stage) Deciphering information necessary for calculation in the 2nd E unit 20B,
Set register operands and memory operands. That is, the selector 16B selects the decoding information of the instruction to be executed and outputs it to the line 44B. Of the selected decoding information, the read register number R _R is input to the second general purpose register 18B, based on which the required operand RDATA2 is read and sent to the second E unit 20B via line 46B. On the other hand, among the decryption information,
The OP CODE, write register number R _W , second operation display signals SUBGR and SUBCC, and condition code change display signal CHGCC are sent to the second E unit 20B. Furthermore, the selector 30B selects a necessary memory operand from the operand buffer 28.
MDATA2 is selected and sent to the second E unit 20B via line 45B. The second E unit 20B takes in the various data thus input into its internal register. This stage is executed in one machine cycle.

(E2 stage) The second arithmetic unit 20B executes a desired arithmetic operation based on the data taken in at the L2 stage, and outputs the result WDATA2 to the line 50B. At this time,
At the same time, the already captured write register number
_RW is also output. Furthermore, at this time, if the operation is an instruction that rewrites the condition code, the condition code
CC2 is calculated.

Note that the second E unit 20B only performs relatively simple operations such as addition, subtraction, and loading in one machine cycle, and is configured with a very small number of circuit elements, so it cannot perform somewhat complex operations such as multiplication. It is assumed that there is no such thing. Therefore, this E2
A stage completes in one machine cycle. Generally, the second E unit 20B is not limited to the above, so the E2 stage may be completed in a different machine cycle depending on the operation executed by the second E unit 20B. In that case, in the final cycle of that stage, the operation end signal EOP2 is on line 48.
Since it is output to B, this last cycle is
It can be called EOP2 cycle. Therefore, if the second E unit 20B only performs operations that must be completed in one machine cycle, as currently assumed, then this E2 stage will be the EOP2 stage.
It consists only of cycles.

(P2 stage) Operation result WDATA2 obtained at E2 stage
is written to the register in second general purpose register 18B, indicated by write register number _RW .
Further, the calculated condition code CC2 is set in the register 34B via the line 70B.

[Details of operation I]

In the following, the details of the apparatus will first be explained through the operation of the apparatus when there is an address conflict. The parts of the device involved in the condition code and their operations will be explained together later.

Below, in order to explain the device operation when there is an address conflict, the first L instruction L(1) and the second L instruction L(1) will be explained.
Assume that instructions L(2), A, and the third L instruction L(3) are executed in this order. Further, it is assumed that the operand register number R _OP of the A instruction and the address register number R _X or R _B of the L(3) instruction are equal, and therefore an address conflict occurs between these two instructions. However, between each instruction L(1), L(2), and A,
(1), between L(2) and L(3) or L(1), L(2), A, L
(3) Assume that there is no address conflict between instructions and the instructions preceding them. It is also assumed that no condition code conflicts exist between any instructions.

This will be explained with reference to time charts 9A to 9C.

(Details of D and D' stages) In order to execute the D and D' stages, instruction decoding information must be set in the instruction queue register 14. This setting to the instruction queue register 14 is controlled by the first I unit 22A. This method of control is essentially the same as that of the previous application. That is, new decoding information can be set in the instruction queue register 14 only if a certain instruction is set in the instruction register 10, there is an empty register in the instruction queue register 14, and the instruction has already been set in the instruction queue register 14. This is the case when there is no address conflict or condition code conflict with the instruction currently being executed or the instruction that is already being executed.

For address conflict detection, the address register portions R _B , _R Presence is detected and the detection result ACONF is input to the first I unit 22A via line 58. Similarly, as will be described later, condition code conflict detection is performed in the circuit 36, and the detection result CCONF is sent to the first I unit 22A.
is input via line 72. 1st I unit 22
As shown in FIG. 4, A has a flip-flop 70 which is set by a control circuit (not shown) each time a new instruction is set in the instruction register 10 by the control circuit. Further, the queue control circuit 73 has three flip-flops 518 to 520 for indicating whether or not each register of the instruction queue register 14 is vacant.The set state of these three flip-flops determines whether any register is vacant. At times, the queue busy signal BSY is output from the AND gate 528. Decoding success determining circuit 75
In this case, the output of flip-flop 70 is 1 and the conflict signals ACONF, CCONF, and queue busy signals are output.
When both BSY are 0, decoding success signal
After outputting the DS to the line 56A and adjusting the timing by the FF 511, it is sent to the instruction queue register 14 to instruct the fetching of decoding information from the decoder 12. The input pointer IP for instructing which register in the instruction queue register 14 is to be loaded with this decoding information is outputted to the line 56A by the queue control circuit 73, and after timing adjustment is performed by FFs 505 and 506, the input pointer IP is sent to the instruction queue register 14.
send to To output this input pointer IP,
The queue control circuit 73 has an internal counter 502 that sequentially counts 0, 1, and 2, and outputs the count value as an input pointer IP. Update of this counter is a decoding success signal
It is performed one cycle after the rise of DS.
Further, the flip-flop 70 is reset by the signal DS, and a control circuit (not shown) sets the next instruction in the instruction register 10 in response to this reset.

Now, numbers 0 and 1 in the instruction queue register 14,
Assume that the L(1), L(2), and A instructions described above are set in the No. 2 register in this order. As a result, L(3)
The instruction will be set in register number 0 after the L(1) instruction. Furthermore, the first and middle timings of each cycle will be referred to as T0 and T1. Further, T0 or T1 written beside a register or flip-flop in the attached drawings indicates that the timing at which the contents of these registers or flip-flops are changed is T0 or T1.
Now, the L(1) instruction is set in the instruction register 10 at timings C0 and T0 (that is, at timings T0 and below in cycle C0). Assuming that the L(1) instruction has no address conflict or condition code conflict with other preceding instructions, and that the instruction queue register 14 is not busy, the decoder success signal DS is output at timings C0 and T1, and the input pointer is Since IP then has the value 0 by assumption, these signals cause the decoding information of the L(1) instruction to be stored in instruction queue register 1.
The timing C2 and T0 are set in the register No. 0 in No. 4.

After this, input pointer at timing C1, T1
IP is updated to 1. At timing C1, T0, the L(2) instruction is set in the instruction register 10, and the L(2) instruction is set in the instruction register 10.
(2) The D stage of the instruction is executed in exactly the same way, one cycle later than the D stage of the L(1) instruction.
As a result, the decoding information for the L(2) instruction is set in the first register in the instruction queue register 14, and the input pointer is updated to 2. Similarly, the D stage of the A instruction is executed in cycle C2, its decoding information is set in the second register in the instruction queue register 14, and IP is updated to 0.

At timing C3, T0, the next L(3) instruction is set in the instruction register 10. However, this L(3)
By assumption, the instruction has an address conflict with the A instruction which has already been set in the instruction queue register 14. Therefore, the output ACONF of the address conflict detection circuit 32 becomes 1 as described later, and the decoding success determining circuit 75 does not output the decoding success signal DS until the release of this address conflict is detected. Therefore, the L(3) instruction is not taken into the instruction queue register 14, and execution of the D stage is postponed. In this embodiment, the D stage of the L(3) instruction is executed in cycle C8, as will be described later. Therefore, the input pointer IP continues to hold the value 0 until then.

Note that address calculations in the D and D' stages are performed under the following timing.

After the L(1) instruction is set in the instruction register 10 at timings C0 and T0, the second general-purpose register 1
The address information specified by this instruction is immediately read from 8B, and the address adder 24 stores the input data in an internal register (not shown), performs addition in one cycle, and outputs the result. do. Therefore, the memory address output by the address adder 24 is determined at timing C2, T0.

The address calculation for the L(2) instruction is performed in exactly the same way as the L(1) instruction, one cycle later, and the memory address for the L(2) instruction is calculated at timings C3 and T.
Set to 0.

Each time new decoding information is set in the instruction queue register 14, the queue control circuit 73 in the first I unit 22A selects one of the flip-flops 518 to 520 that indicates whether or not each register in this register 14 is vacant. Set what you want to do.

(Details of Stages A and A') In this stage, a memory operand is read from the main memory 26 based on the memory address obtained in the stages D and D', and is set in the operand buffer 28. As already mentioned, the decoding information for the L(1) instruction is set in register number 0 in the instruction queue register 14. Therefore, the memory operand corresponding to the L(1) instruction is also set in register number 0 in the operand buffer 28. Therefore, the first I unit 22A inputs the input pointer IP and the decoding success signal DS.
are flip-flops 511 to 513, respectively.
Signal IPD delayed by 2.5 cycles from 505 to 510,
DSD is supplied to buffer 28 via line 57A. As a result, the memory operand for the L(1) instruction is set in the No. 0 register in the buffer 28 at timing C4, T0 in response to the signals DSD and IPD. Similarly, the memory operand for the L(2) instruction is set in the first register in the buffer 28 at timing C5, T0.

(Details of L1 stage) The L1 stage of each instruction is
It starts when the E1 stage ends, that is, when the first operation end signal EOP1 is output from the first E unit. In this L1 stage, one piece of decoding information and one memory operand are selected from the instruction queue register 14 and the operand queue buffer 28 by the selectors 16A and 30A, respectively, and set in the 1E unit 20A.

These controls are performed by the first I unit 22A. That is, the queue control circuit 73 in the first I unit 22A sends output pointers indicating the register number or buffer number to be selected to the selectors 16A and 30A.
Counter 53 sending OP1 via line 53A
It has 2. This counter repeatedly counts the values 0, 1, and 2 in sequence. When the first operation end signal EOP1 is output from the first E unit 20A, the queue control circuit 73 outputs the first operation start signal BOP1 for one cycle via the line 52A after one cycle, and also outputs the first operation start signal BOP1 for one cycle through the line 52A.
The output pointer OP1 is updated at timing T0 of the cycle following the cycle in which 1 was output.

As will be described later, the signal EOP1 is outputted from the first E unit 20A every other cycle from the timing T0 of the first half cycle of the final E1 stage of the preceding instruction until the signal BOP1 is input thereafter. Assuming that the E1 stage of the instruction preceding the L(1) instruction (this is now called instruction X) ends in cycles C4 and C5,
The signal EOP1 is output for one cycle from timing C4, T0. At this time, the queue control circuit 7
3 outputs the value 0 for selecting the L(1) instruction by assumption as the output pointer OP1, and also outputs the first operation start signal BOP1 for one cycle from timing C5 and T0. Note that the output pointer OP1 is updated to 1 at timing C6, T0 in response to this BOP1. Therefore, the queue control circuit 73 includes a flip-flop 52 which has a one-cycle delay, a two-cycle delay, and a three-cycle delay from the flip-flops 518 to 520.
There is a selector 527 that selects the value of the signal indicated by the OP1 signal from 1 to 523, 549 to 551, 524 to 526, and 524 to 526. Furthermore, a gate 529 that ANDs the output of this selector and the EOP1 signal and the output of 529 are set to T0.
There is a flip-flop 530 that takes in the data. 5
The output of 30 is the operation start signal BOP1 in the 1st E unit. Also, the output of gate 529 is 1
Then, the above flip-flops 518 to 52
0,521~523,549~551,524~
Of the 526 instruction queues, those corresponding to the instruction queue indicated by the value of OP1 at this time are reset. This reset is performed by a signal generated by decoder 531.

As described above, based on the value 0 of the output pointer OP1 output in cycles C4 and C5,
The decoding information and memory operand of the L(1) instruction are selected from the selectors 16A and 30A.

On the other hand, based on the first calculation start signal BOP1 output in cycle C5, the 1E unit 20
A takes in these selection information. At this time, among the decoding information selected by the selector 16A, the read register number R _R is the first general-purpose register 18A.
The register operand RDATA1 read out based on the data is input to the 1E unit 20A via the line 46A. 1st E unit 20A
also takes in this operand RDATA1.

The 1E unit 20A has a first arithmetic circuit 400 and flip-flops 401 and 4 as shown in FIG.
03 and an AND gate 405. The first arithmetic circuit 400 is connected to the selector 16 via a line 44A.
OP CODE, write register number R _W , register change display signal CHGGR, condition code change display signal CHGCC input from A, register operand RDATA1 input from the first general-purpose register 18A via line 46A, and line 45A. Memory operand input from selector 30A via
MDATA1 in response to the calculation start signal BOP1 inputted from the first I unit via the line 52A.
It is set in its internal register (not shown).
On the other hand, the second calculation instruction signal SUBGR input from the selector 16A via the line 44A is the signal BOP1.
In response to this, the flip-flop 401 is set. In this way, the input data in the first E unit 20A is captured.

In the example currently being considered, data related to the L(1) instruction is taken into the first E unit 20A at timing C6, T0, and the L1 stage of the L(1) instruction is completed. The L1 stage of the next instruction is L(1)
It is executed at the timing when the operation end signal EOP1 for the instruction is output (here, cycle C6). Further, the L1 stage of the A instruction is executed from timing C8 when EOP1 for the L(2) instruction is output.

However, in the C10 cycle when EOP1 of the A instruction is issued, the L(3) instruction has not finished decoding the instruction and reading the operands (the A and A' stages have not been completed before that), so the L1 stage is is not executed. The L1 stage of the L(3) instruction is executed after the C12 stage after the A and A' stages of the L(3) instruction are completed.

(Details of E1 stage) The first arithmetic circuit 400 receives the input OP CODE
For the operation specified by , for example, the A instruction, addition is performed on the register operand RDATA1 and memory operand MDATA1, and the result data WDATA1 is output to line 50A, and the first half cycle of the final E1 stage of the operation is The computation end signal EOP1 is output every other cycle from timing T0 until the signal BOP1 is input. At this time, the write register number R _W in the input decoding information is held in the circuit 400 until the result data WDATA1 is calculated, and is output to the line 50A together with the result data WDATA1. Furthermore, when the input condition code change display signal CHGCC is 1, the circuit 40
0 calculates the condition code CC1 depending on the OPCODE and result data WDATA1, and outputs this signal together with the set signal SET1 in the latter half cycle of the final E1 stage. When the signal CHGCC is 0, the signal SET1 remains 0. Further, the circuit 400 receives a registered register change indication signal.
When CHGGR is 1, the result data WDATA1
The write signal WC1 is connected to the line 50A in synchronization with the output of
is configured to output to . circuit 400
is constituted by, for example, a microinstruction control circuit.

On the other hand, the flip-flop 401 has a timing T
The second calculation display signal SUBGR set to 0 is transferred to the flip-flop 403 at timing T0. The signal inside this flip-flop 403
The inverted signal of SUBGR and the write signal WC1 output from the circuit 400 to the line 50A are connected to the AND gate 40.
5 is input. Therefore, the output WC12 of the gate 405 becomes 1 only when the operation executed by the first operation circuit 400 cannot be executed by the second E unit and the general-purpose register can be rewritten.
This output WC12 is used to write the calculation result WDATA1 into the second general-purpose register 18B.

(Details of P1 stage) The result data WDATA1 output from the 1E unit 20A onto the line 50A is the write register number in the first and second general registers 18A and 18B based on the write signals WC1 and WC12 on that line. It is written to the register with R _W at timing T0. Further, the calculated condition code CC1 is set in the register 34A in response to the set signal SET1.
written to. Therefore, the condition code output by the most recently executed instruction among the instructions that change the condition code is set in the register 34A. In this way, the P1 stage of the L(1) instruction is executed in cycles C8 and C9, the L(2) instruction is executed in cycles C10 and C11, and the A instruction is executed in cycles C12 and C13. However, since these three instructions can all be executed by the second E unit 20B (SUBGR=1), WC12=0, and the result data WDATA1 is not written to the second general-purpose register 18B. Furthermore, since the L(1) and L(2) instructions are not instructions that change the condition code, the contents of the register 34A are not changed. Also, the condition code CC1 obtained by the operation of the A instruction is cycle C1.
It will be set to 0 in register 34A.

As described above, D~ of L(1), L(2), A instruction
P1 stage is executed. However, since there is an address conflict with the next L(3) instruction,
D of L(3) instruction until this conflict is resolved.
Stage is not executed.

According to the earlier application mentioned at the beginning of the above, this conflict is resolved after the operation result in the 2E unit of the A instruction is obtained, but the L(1), L (2) Since the instruction performs an operation in either the first or second E unit, and the operation execution time is the same in the above-mentioned prior application, the time at which the result of the operation in the first or second E unit for the A instruction is obtained is It's the same. Therefore, in the above prior application, A
The result of the operation in the 2nd E unit of the instruction is obtained in the C12 cycle. Therefore, the D stage of the L(3) instruction starts from the C12 cycle.

On the other hand, in this embodiment, in order to hasten the start of the D stage of the L(3) instruction, for an instruction that performs an operation in either the 1st or 2nd E unit, the number of operation cycles in the 2nd E unit is changed to the number of operation cycles in the 1st E unit. shorter than the number of calculation cycles, and
The operation in the 2E unit can be started immediately after the operation of the previous instruction is completed.

This point will be explained in more detail below.

(Details of L2 stage) This stage is a stage where necessary data is set in the second E unit 20B. This stage is controlled by the second I unit 22B. As shown in FIG. 6, the second I unit 22B has registers #0 to #0 in the instruction queue register 14.
Flip-flops 101 to 103 corresponding to #2
These flip-flops are used to indicate whether or not valid decoding information is set in the corresponding register in the instruction queue register 14. That is, decoder 1
00 is activated by the decoding success signal DS, and flip-flops 101 to 1 correspond to the register number indicated by the input pointer IP input thereto.
1 signal is output for any one of 03. This signal is transmitted to the flip-flops 101-103.
It is input to the data terminal of one flip-flop corresponding to the input pointer IP, and is further input to the clock terminal of that one flip-flop via one of OR gates 107-109. In this way, one of the flip-flops 101-103 is set corresponding to the input pointer IP. It is assumed that these flip-flops 101 to 103 take in input data only at timing T0. Furthermore, flip-flop 538~
540 are flip-flops 101 to 10, respectively.
The flip-flops 546 to 548 output the outputs of the flip-flops 538 to 540, respectively, and the flip-flops 120 to 122 delay the outputs of the flip-flops 546 to 548 by one cycle. , 546-548, 120-1
22 also changes its output only at timing T0.

Flip-flop 149, 150, 153, 1
54, the incrementer 148 constitutes a counter that sequentially counts 0, 1, and 2, and the outputs of the flip-flops 153 and 154 are sent to the second E unit 20.
It is used as output pointer OP2 for selection of information regarding the instruction to be executed in B. That is, this output pointer OP2 is input to selectors 16B and 30B via line 53B, and contains decoding information and memory operands of the instruction to be executed.
MDATA2 is selectively output to lines 44B and 45B by these selectors. However, this information cannot be transferred to the 2nd E unit 20.
The unit that may be set to B is the 2nd E unit 20B.
This is a case where the operation for the preceding instruction has been completed and the information for the next instruction to be executed in the L2 stage has been set in the instruction queue register 14 and operand queue buffer 28. As described later, the second E unit 20B responds to the second operation start signal BOP2 by selecting the selector 16B,
30B is set, and an end signal EOP2 is output from the final cycle of calculation.
In the second I unit 22B, one of the outputs of the flip-flops 120 to 122 is selected by the selector 129 according to the output pointer OP2. This selected signal indicates that the instruction to be executed is set in the register in the instruction queue register 14 indicated by the output pointer OP2. Therefore, the second I unit 22B performs an AND operation between the signal EOP2 inputted through the line 48B and the output signal of the selector 129, and sends the calculation start signal BOP2 to the line 52B only when both signals are 1. It is now output to .

In the end, in this L2 stage, do the following,
Necessary information is set in the second E unit 20B. Among the decoding information selected by the selector 16B, OP CODE, write register number R _W , and second
The calculation display signals SUBGR, SUBCC and the condition code change display signal CHGCC are sent directly to the second E unit 20B via the line 44B, and the read register number R _R is input to the second general-purpose register 18B.
Used to read register operand RDATA2. This operand is connected to the second E via line 46B.
The signal is input to unit 20B. The memory operand MDATA2 selected by selector 30B is sent directly to second E unit 20B via line 45B. The second E unit 20B takes in this information in response to the signal BOP2.

In the second I unit 22B, as shown in FIG. 6, the incrementer 148 is activated in response to the signal BOP2, and the output pointer OP at that time is
A signal indicating a value obtained by counting up 2 is output to flip-flops 149 and 150. In this way, the output pointer OP2 is updated every time the signal BOP2 is output. Also, signal BOP2
The decoder 113 is activated. This decoder 113 sends a signal 1 to one of the OR gates 107 to 109 depending on the value of the output pointer at that time. At this time, the decoding success signal DS is not input to the decoder 100, or even if the signal DS is input, the value of the input pointer at that time is different from the value of the output pointer OP2, so the flip-flop 101 corresponding to the output pointer OP2 Alternatively, the signal 1 from the decoder 100 is never input to the data terminal 102 or 103. Therefore, one of the flip-flops 101-103 is reset corresponding to the output pointer OP2.

As already mentioned, the assumption is that D of the L(1) instruction
The decoding success signal DS for the stage is output at timing C0, T1, and the input pointer IP at this time is 0, but the flip-flop 10
1 is set at timings C1 and T0, and flip-flops 538, 546, and 120 are set at timings C2, C3, and C3, which are delayed by one cycle from this, in order.
It is set at each T0 of C4 and C4. At this time, the output pointer OP2 output from the flip-flops 153 and 154 must be for the L(1) instruction to execute the L2 stage, and indicates the value 0. Therefore, the output of the selector 129 is 1 at timing C4, T0, and at this time L
(1) Since it is assumed that the operation in the 2E unit for the instruction X before the instruction has been completed, the signal
EOP2 is 1. Therefore, the signal BOP2 also becomes 1. In this way, data necessary for executing the L(1) instruction is set in the second E unit 20B. Thus, the L2 stage of the L(1) instruction is performed in cycle C4. Also, the incrementer 148 is activated by this signal BOP2, and the value 1 which counts up the output pointer OP2 at that time is 1.
Output. This value is the flip-flop 149,
150 at timings C4 and T1, and further captured into flip-flops 153 and 154 at timings C5 and T0. Therefore, output pointer OP2 is next L(2) in cycle C5.
Updated to value 1 for instructions.

The decoder 113 is activated at timing C4 and T0 by the signal BOP2, and outputs a 1 signal to the OR gate 107 and the reset input terminals R of the flip-flops 538, 546, and 120 for the value 0 of the output pointer OP2 at that time. As a result, flip-flops 101, 538, 546,
120 is reset at timing C5, T0.

The L2 stage of the L(2) and A instructions are performed in exactly the same way, and the signal BOP2 for this instruction is output in cycles C5 and C6, respectively.

During this time, the output pointer OP2 is set at timing C5,
It becomes 1 at T0, then becomes 2 at timing C6 and T0.
Furthermore, it is updated to 0 at C7 and T0.

However, since the next L(3) instruction has an address conflict with the A instruction, the decoding success signal DS for this instruction is output at timing C8, T1, so the L2 stage of the L instruction is until cycle C12. Postponed. Therefore, the output pointer OP2 continues to hold the value 0 at timings C7 and T0, respectively.

When the decoding success signal DS for the L(3) instruction is output at timing C8, T1, timing C8
At 9, T0, the flip-flop 101 is set. Thereafter, the calculation start signal BOP2 for the L(3) instruction is output at timing C12, T0, just as in the case of the L(1), L(2), and A instructions.

(Operation of E2 stage) In the second E unit 20B, as shown in FIG.
CHGCC operation start signal BOP2, register change signal
SUBGR, write register number R _W , operation code OP CODE, register operand
RDATA2, memory operand MDATA2 is a signal
It is set by the operation of the L2 stage in response to BOP2. The second arithmetic circuit 307 receives the signal BOP
2 and set in register 303.
It performs the operation specified by the OP CODE and sends the operation result WDATA2 to the register 310. Furthermore, when OP CODE indicates an operation that changes the condition code, the condition code CC2 is calculated and output depending on the operation result WDATA2 and the type of operation. Further, in the final cycle of calculation, a calculation end signal EOP2 is outputted to line 48B.
This signal is output every cycle until the next BOP2 signal is input. Also, the input OP
This second calculation circuit 30 performs the calculation specified by CODE.
7 cannot be executed, this circuit 307 outputs this signal EOP2 every cycle until the next signal BOP2 is input. Therefore, it is currently assumed that the second arithmetic circuit 307 executes only one machine cycle of arithmetic operations, so the signal
EOP2 will be output every cycle. Further, the calculation result WDATA2 is set in the register 310 at timing T0, the write register number R _W set in the register 302 is set in the register 309 at timing T0, and the signal BOP2 similarly set in the registers 300 and 301, respectively. and SUBGR are set in the register 308 at timing T0 via an AND gate.
The output of register 308 is 1 when its value is 1.
This is a write signal WC2 indicating that the result WDATA2 should be written to the general-purpose register 18B.

The output VALID of register 298 is the condition code CC
2 is a signal indicating that it is valid, and becomes 1 when the L2 stage of an instruction whose second operation display signal SUBCC is 1 is executed. In other words, the operation of the instruction executed by the L2 stage is executed by the 2E unit 2.
The signal VALID becomes 1 when the instruction is executable with 0B and changes the condition code, and becomes 0 for other instructions.

Also, the output of register 299 and register 300
The AND gate outputs the AND gate.
This logical product SET2 becomes 1 in the E stage of an instruction that changes the condition code, and becomes 0 in other instructions. This signal SET2 has condition code CC2
and valid display signal VALID to condition code register 3
4B (Figure 1B).

Cycle C for L(1), L(2), and A instructions, respectively.
Calculation is performed in 5, C6, and C7, and the result data
WDATA2, write register number R _W , write signal
WC2 is output to line 50B at timings C6, C7, and C8, respectively, at T0. The same calculation is performed for the L(3) instruction in cycle C13.

Further, in the A instruction, the condition code CC2, its set signal SET2, and valid signal VALID are output to the line 70B at timings C7 and T0.

(Details of the P2 stage) The result data WDATA2 obtained in this way at the E2 stage is sent to the second general-purpose register 18B via the line 50B, and when the write signal WC2 is 1, it is written to the register indicated by the number R _W. be included.

Further, when the set signal SET2 is 1, the condition code CC2 and the valid display signal VALID are set in the condition code register 34B (FIG. 1B).
When set signal SET2 is 0, register 3
The contents of 4B remain unchanged. Therefore, when the instruction executed in the E2 stage is an instruction that changes the condition code, the contents of the register 34B are rewritten. Therefore, when this instruction is executable in the 2nd E unit, the new contents of register 34B are the VALID signal with the value 1 and the 2nd E unit 2
This is the newly found condition code CC2 in 0B.
However, if this instruction is one that cannot be executed by the second E unit 20B, the new contents of the register 34B are the VALID signal with a value of 0 and meaningless data being output from the second E unit 20B on line 70B. On the other hand, if the instruction executed in the E2 stage is an instruction that does not change the condition code, the contents of the register 34B cannot be rewritten.

For the L(1), L(2), and A instructions, the operation results are written to the second general-purpose register at timings C7, C8, and C9, respectively, and for the L(3) instructions, they are written at timings C15 and T0. is written. Furthermore, for the A instruction, timing C8,
At T0, a condition code and a VALID signal having a value of 1 are set in register 34B.

Therefore, in this embodiment, the result of the A instruction is C
9, written to the second general-purpose register at T0, the address conflict with the L(3) instruction, which requires using this result in address calculation, is resolved at this point, and the address conflict detection circuit 32 The output ACONF becomes 0, and the first I unit 20A can start the D stage of the next L(3) instruction. Therefore, the D stage of the subsequent L(3) instruction is C8.
4 compared to the earlier application mentioned above.
The stage (2 cycles in the earlier application) can be accelerated.

The breakdown of this 4-cycle reduction is 2 cycles from the start of the D stage until the end of writing to the second general-purpose register, and 2 cycles from the start of the D stage until the end of writing to the second general-purpose register
Since the unit can perform calculations on L(1) and L(2) instructions at half the pitch compared to the 1st E unit, calculations in the 2nd E unit can start 1 cycle for each instruction, a total of 2 cycles earlier. This is a reduction of 2 cycles.

Here, in addition to the fact that the 2E unit can actually perform operations with half the pitch compared to the earlier application, the instruction decoding itself needs to be performed with half the pitch compared to the earlier application, and in this embodiment, Needless to say, it is configured in this way.

(Address conflict detection operation) The configuration of the address conflict detection circuit 32 is as follows.
As shown in FIG. 8, it may be the same as that in the above-mentioned prior application, and only the outline will be explained here.

Flip-flops 200 to 202 correspond to registers #0 to #2 of the instruction queue register 14, and the instructions contained therein are instructions that modify general-purpose registers, and the modification has not yet been completed. shows. Registers 218-22
0 corresponds to each register #0 to #2 of the instruction queue register 14, and if an instruction to change a general-purpose register is contained therein, the write register number _RW is held therein. The comparator 224 compares the index register and base register numbers R _X and R _B of the instruction held in the instruction register with the write register number of the instruction whose general register in the instruction queue register has not yet been changed. , and outputs the comparison result to the OR gate 235.

The selector 256 selects flip-flops 200~
Among the values 202, the one whose calculation has started in the first E unit is selected and output to the flip-flop 258.

Further, the selector 227 selects the registers 218 to 22.
Among the write register numbers stored in 0, the one whose operation has started in the 1E unit is selected and output to the register 228. Comparator 230
is the instruction R _X held in the instruction register,
It compares R _B with the write register number of an instruction that has not yet finished changing a general-purpose register during an operation in the 1E unit, and outputs the comparison result to the OR gate 235. OR gate 235 outputs an ACONF signal on line 58 indicating the occurrence of an address conflict.

The flip-flops 200-202 and registers 218-220 are set by set circuits 250 and 225, respectively, when the DS signal rises.
This is done for the number indicated by the IP signal.
To reset flip-flops 200-202,
The reset circuit 254 writes the calculation result of the 2nd E unit to the 2nd general-purpose register when the signal WC2G rises, and when the calculation is started in the 1st E unit for an instruction that is not performed in the 2nd E unit. This is done by the reset circuit 252.

Registers 237 and 542 create a delayed signal for OP1. Registers 236 and 543 are BOP1
Create a delayed signal.

FIG. 9C shows flip-flops 200-20
2,258, registers 218 to 220,228,
A time chart of the comparators 224, 230 and the ACONF signal 58 is shown.

[Details of operation] When there is a condition code conflict, L(1),
It is assumed that A and BC are executed in this order, and the L(2) instruction is executed. It is also assumed that there are no address conflicts between these instructions or between the instructions preceding them and these instructions.

(Processing of BC command) The time chart of this operation is from 11A to
11B. However, this diagram only shows the signals necessary to understand the behavior of condition code conflicts.

The L(1) and A instructions are executed exactly as described above, and the D stage of the BC instruction is cycle C2.
Assume that it is executed in

In the D and D' stages of the BC instruction, L(1),
As with the A instruction, an address is calculated by the adder 24, and this address is the address of the branch destination instruction. The decoding information of the BC instruction by the instruction decoder 12 is the same as the decoder success signal as for other instructions.
DS (This is output at timing C2, T1)
The command is stored in the instruction queue register 14 in response to the command. Further, among the outputs of the instruction decoder 12, a branch instruction display signal BC and a mask signal MASK are sent to the condition code conflict detection circuit 36 via a line 42. The circuit 36 outputs the condition code conflict signal CCONF at timings C3 and T, as will be described later.
Set 0 to 1. In response to this signal, the 1st I unit 22A outputs a decoding success signal for subsequent instructions.
Prevent the occurrence of DS. Thus, the D of the BC command,
D′ stage ends. In the A and A' stages of the BC instruction, the L(2) instruction read from the main memory 26 at timings C5 and T0 based on the above-mentioned instruction address is transferred to the instruction buffers 6A and 6B under the control of a fetch circuit (not shown). The data is stored on the target stream side at timing C6, T0. The fetch circuit further sequentially reads out the instruction sequence following this L(2) instruction from the main memory 26 and stores it in the instruction buffer 6A on the target stream side.
Or sequentially store in 6B.

In cycle C6, since the operation of the A instruction in the second E unit 20B is completed, the signal EOP is
2 is output in this cycle. Therefore, the signal BOP2 is output from the second I unit 22B in this cycle C6. Therefore, the L2 stage of the BC instruction becomes possible in cycle C6.

In the L2 stage of the BC instruction, selector 1
The BC instruction decoding information selected by 6B is
2E unit 20B is set. The operation required by the BC instruction is to determine branch success based on this decoding information. However, unlike other instructions, this determination is made by the condition code conflict detection circuit 36 in this embodiment. The output of selector 16B is therefore sent via line 44B to this detection circuit 36 and set therein. Note that the output of the selector 16B is also sent to the second E unit 20B like other commands.

Furthermore, in the L2 stage, the selector 30B is controlled to select data related to the BC instruction.
In the next stage after the L2 stage, as mentioned above,
A branch success determination is made in the circuit 36, and the second E unit 20B does not substantially operate and receives an operation end signal.
EOP2 is only output from cycle C7.
However, like other instructions, this stage will be called the E2 unit stage.

In this E2 stage, the condition code conflict detection circuit 36 detects whether a branch success determination is possible based on the output of the register 34B.
This branch judgment is possible at the E2 stage because
The instruction before the BC instruction is an instruction that changes the condition code and can be executed by the second E unit 20B. Therefore, the signal in register 34B
This is when VALID is 1. When a branch decision is possible, a conflict signal is generated at the end of the decision.
Set CCONF to 0. Further, if the result of the determination is that the branch is successful, a branch success signal BCTKN is output to the line 74. On the other hand, when branch determination is not possible, the signal CCONF does not change and the signal BCTKN is not output.

In this case, the preceding A instruction is the 2nd E unit 2.
Since it is an instruction that can be executed in 0B and changes the condition code, A
After completing the E2 stage of the instruction, register 34
The signal VALID in B has the value 1. Therefore,
The circuit 36 is capable of making a branch decision and makes a branch decision based on the condition code CC2 inputted from the register 34B and the mask signal MASK already inputted from the instruction decoder 12. As a result, assuming that the branch is successful, the signal BCTKN
becomes 1. This causes flip-flop 9 (FIG. 1A) to be inverted. Also, the condition code conflict signal CCONF is at timing C9, T0.
becomes zero. In this way, the E2 stage of the BC instruction ends.

In the next stage (this is called the P2 stage), the following operations are performed. That is, as the flip-flop 9 is inverted, the readout circuit 8 (first A
Figure) shows the branch destination L(2) instruction at timing C8, T0.
is set in instruction register 10. Also, the signal
Since CCONF is 0 and it is assumed that there is no address conflict, the first I unit 22A outputs the decoding success signal DS for the next instruction at timing C8 and T1. In this way, if the branch is successful, the D stage of the L(2) instruction at the branch destination can be executed in cycle C8. In addition,
After the start of the D stage of the BC instruction, the readout circuit 8
Instructions to be executed when a branch fails are stored in instruction register 1.
Preset to 0. Therefore, when the result of branch determination is that the branch is unsuccessful, the instruction on the side of the unsuccessful branch is executed in response to the signal DS.

On the other hand, in the above-mentioned prior application, the operation of the 2nd E unit of the A instruction is performed in the C8 and C9 cycles,
Branch determination is made in the C10 cycle, and therefore the D stage of the branch destination instruction L(2) starts from C12.

Therefore, according to the present invention, the D stage of L(2) can be advanced by 4 cycles compared to the conventional example. This 4-cycle reduction consists of 2 cycles reduction in the number of cycles from the start of the D stage until the condition code is obtained by the 2nd E unit, and 2 cycles reduction in the number of cycles required for the 2nd E unit to obtain the condition code, and ) instruction at half the pitch, the operation in the 2E unit of the A instruction can be started one cycle earlier, which saves one cycle, and the branch decision and branch to the instruction register are made after the condition code is obtained. This is one cycle due to the reduction in the number of cycles until the first instruction is extracted.

(Condition Code Conflict Detection Circuit and Its Operation) As shown in FIG. 10, the configuration of the condition code conflict detection circuit 36 may be substantially the same as that in the conventional example, and only the outline will be described here.

Flip-flop 406 outputs a CCONF signal on line 72 indicating the occurrence of a condition code conflict. 406 is set when the DS signal rises for the BC instruction, and in response to the branch judgment end signal END from the branch judgment circuit 417, the control circuit 404
It is set by

The AND gate 409 inputs the operation start condition in the 1st E unit of the BC instruction to the flip-flop 413. 413 outputs this to the branch determination circuit 417 as a determination command signal J1 when branch determination is performed using CC1.

The AND gate 410 inputs the operation start condition in the second E unit of the BC instruction to the flip-flop 414. 414 outputs this to the branch determination circuit 417 as a determination command signal J2 when performing branch determination using CC2.

Register 403 contains the mask value MASK of the BC instruction.
is stored and output to the branch determination circuit 417.

Branch determination circuit 417 outputs an END signal indicating the end of branch determination and a BCTKN signal indicating branch success.

The time chart of CCONF, J1, J2, END, BCTKN and their related signals is shown in 11B.
As shown in the figure.

〔Effect of the invention〕

According to the invention, like the system program
Even in programs where the majority of instructions have short calculation stages, such as Load and Add, the 2nd E unit can obtain the calculation results earlier than the 1st E unit, which eliminates address conflicts and increases the speed of BC instructions. realizable. In recent large-scale general-purpose computers, it is thought that address conflicts and BC instruction branch decisions each account for about 10% of the average processing time per instruction when executing a system program. It has the effect of significantly reducing the amount of time required, and is considered effective in speeding up large general-purpose computers.

[Brief explanation of drawings]

1A and 1B are block circuit diagrams of different parts of an embodiment of the present invention, and FIG. 2 shows the arrangement of FIGS. 1A and 1B for constructing a digital computer. 3A and 3B each illustrate one example of an instruction format used in an embodiment of the present invention. FIG. 4 is a schematic circuit diagram of the first instruction control unit used in the above embodiment. FIG. 5 is a schematic diagram of the first arithmetic execution unit used in the above embodiment. FIG. 6 is a schematic diagram of the second instruction control unit used in the above embodiment. FIG. 7 is a schematic diagram of the second arithmetic execution unit used in the above embodiment. FIG. 8 is a schematic diagram of the address conflict detection circuit used in the above embodiment. 9A to 9C are time charts when there is an address conflict in the above embodiment. 9D and 9E show the instruction processing stages in the prior application and this embodiment, respectively. FIG. 10 shows a schematic configuration diagram of a condition code conflict detection circuit used in the above embodiment. Figures 11A and 11B are
This is a time chart when there is a condition code conflict in the above embodiment.

Claims (1)

[Claims] 1. A data processing device that divides each instruction to be executed into a plurality of stages and executes them in a pipeline mode, which is capable of executing a plurality of operations in a first time interval at the shortest. a first arithmetic device; a second arithmetic device capable of executing some of the plurality of arithmetic operations with a relatively short execution time in a second time interval smaller than the first time interval; means for decoding a plurality of instructions to be executed in chronological order so as to decode a subsequent instruction in parallel with the execution of the operation of the previously decoded instruction; means for temporarily holding a plurality of instructions; and a means for sequentially causing the first arithmetic unit to execute operations requested by each of the plurality of instructions held in the holding means at the first time interval at the shortest. a first instruction execution control means for instructing, the holding means in synchronization with the end of the operation being executed in the first arithmetic device and asynchronously with the end of the operation in the second arithmetic device; having means for instructing the execution of the next instruction held by the holding means; and among the plurality of instructions held by the holding means,
Select a part of a plurality of instructions that require operations that can be executed by the second arithmetic unit, and have the second arithmetic unit execute the operations required by each instruction within the second time interval at the shortest. a second instruction execution control means operating in parallel with the first instruction execution control means that sequentially instructs the second instruction execution control means, the second instruction execution control means operating in parallel with the first instruction execution control means; , asynchronously with the completion of the operation by the first arithmetic unit, instructing the execution of the operation of the next instruction that requests an operation that can be executed by the second arithmetic unit, among the instructions held in the holding means. 1. A data processing device having means for: 2. Among the plurality of instructions to be executed, in response to the plurality of instructions using memory operands in the calculation stage being decoded by the decoding means, The first instruction execution control means further comprises means for generating an instruction at a time interval, when the first instruction execution control means instructs the first arithmetic unit to execute an instruction to be executed next, The second instruction execution control means supplies the memory operand generated by the generation means or the register operand specified by the instruction to the first arithmetic unit, and the second instruction execution control means causes the second arithmetic unit to perform the next operation. 2. The second arithmetic unit according to claim 1, wherein when instructing execution of an instruction to be executed, a memory operand generated by the generating means for the instruction or a register operand specified by the instruction is supplied to the second arithmetic unit. Data processing equipment. 3. The data processing apparatus according to claim 1 or 2, wherein the first time interval is a multiple of the second time interval. 4 the first time interval is 2 machine cycles;
4. The data processing apparatus of claim 3, wherein the second time interval is one machine cycle. 5. A data processing device that divides each instruction to be executed into a plurality of stages and executes them in a pipeline mode, the first arithmetic device being capable of executing a plurality of operations in a first time interval at the shortest; , a second arithmetic unit capable of executing some of the plurality of operations with a relatively short execution time in a second time interval smaller than the first time interval; and the previously decoded instruction. means for chronologically decoding a plurality of instructions to be executed so as to decode subsequent instructions in parallel with the execution of an operation; a first instruction that sequentially instructs the first arithmetic unit to execute the operation requested by each of the plurality of instructions held by the holding means, at the first time interval at the shortest; Execution control means, in synchronization with the end of the operation being executed in the first arithmetic device and asynchronously with the end of the operation in the second arithmetic device, the next one held in the holding device. one having a means for instructing the execution of an operation of an instruction; and among the plurality of instructions held by the holding means,
The execution of some operations required by some of the plurality of instructions that request operations that can be executed by the second arithmetic unit is performed sequentially on the second arithmetic unit at the second time interval at the shortest. a second instruction execution control means for instructing, the holding means in synchronization with the end of the operation being executed in the second arithmetic device and asynchronously with the end of the operation in the first arithmetic device; Among the instructions held in the second arithmetic unit, one has means for instructing the execution of the next instruction that requires an operation executable by the second arithmetic unit, and the plurality of instructions decoded by the decoding means are For instructions that use memory operands in the arithmetic stage, means for calculating the addresses of the memory operands required by each instruction and reading those memory operands at the earliest in a second time interval; Either one of the first
It is determined whether or not the operation result of the preceding instruction being executed or waiting to be executed is needed in the arithmetic unit or the second arithmetic unit, and when the result of the operation is needed, the result of the operation is transferred to the first arithmetic unit. and means for inhibiting the reading means from generating an address of a memory operand for an instruction until it becomes usable by the arithmetic unit or the second arithmetic unit. 6. The data processing apparatus according to claim 5, wherein the first time interval is a multiple of the second time interval. 7 the first time interval is 2 machine cycles;
7. The data processing apparatus of claim 6, wherein the second time interval is one machine cycle. 8. A first arithmetic device that is a data processing device that divides each instruction to be executed into a plurality of stages and executes them in a pipeline mode, and that is capable of executing a plurality of operations in a first time interval at the shortest; a second arithmetic unit capable of executing some of the plurality of operations with a relatively short execution time in a second time interval smaller than the second time interval; means for chronologically decoding a plurality of instructions to be executed so as to decode subsequent instructions in parallel with the execution of an operation; holding means; and first instruction execution for sequentially instructing the first arithmetic unit to execute operations requested by each of the plurality of instructions held by the holding means, at the first time interval at the shortest. A control means that executes the next instruction held in the holding means in synchronization with the end of the operation being executed in the first arithmetic device and asynchronously with the end of the operation in the second arithmetic device. Among the plurality of instructions held by the holding means,
The execution of some operations required by some of the plurality of instructions that request operations that can be executed by the second arithmetic unit is performed sequentially on the second arithmetic unit at the second time interval at the shortest. a second instruction execution control means for instructing, the holding means in synchronization with the end of the operation being executed in the second arithmetic device and asynchronously with the end of the operation in the first arithmetic device; Among the instructions held in the second arithmetic unit, the instructions decoded by the decoding means have means for instructing the execution of the next instruction that requires an operation executable by the second arithmetic unit, and the instruction decoded by the decoding means means for determining whether or not the branch is successful based on the value of a condition code for branch determination held in the data processing device when a branch instruction is executed; means for calculating the address of a branch destination instruction and reading the branch destination instruction; It is determined whether the condition code is rewritten by the operation of the instruction, and if it is determined that the condition code is rewritten by the operation of one of the preceding instructions, the condition code is rewritten by the operation of one of the preceding instructions. and means for inhibiting the reading means from generating an address for a branch destination instruction for the branch instruction until a condition code for the branch instruction becomes available. 9. Among the plurality of instructions to be executed, in response to the plurality of instructions using memory operands in the calculation stage being decoded by the decoding means, The first instruction execution control means further includes means for generating the instruction at a time interval, and when instructing the first arithmetic unit to execute an instruction to be executed next, the first instruction execution control means generates a The second instruction execution control means supplies the memory operand generated by the generation means or the register operand specified by the instruction to the first arithmetic unit, and the second instruction execution control means causes the second arithmetic unit to perform the next operation. 9. When instructing the execution of an instruction to be executed, the memory operand generated by the generating means for the instruction or the register operand specified by the instruction is supplied to the second arithmetic unit. Data processing equipment. 10. The data processing apparatus according to claim 8 or 9, wherein the first time interval is a multiple of the second time interval. 11. The data processing apparatus according to claim 10, wherein the first time interval is two machine cycles and the second time interval is one machine cycle.